CN112596506A - Fault injection method, fault injector, storage medium and fault injection system - Google Patents
Fault injection method, fault injector, storage medium and fault injection system Download PDFInfo
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- CN112596506A CN112596506A CN202011603468.1A CN202011603468A CN112596506A CN 112596506 A CN112596506 A CN 112596506A CN 202011603468 A CN202011603468 A CN 202011603468A CN 112596506 A CN112596506 A CN 112596506A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0259—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the response to fault detection
- G05B23/0262—Confirmation of fault detection, e.g. extra checks to confirm that a failure has indeed occurred
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The present disclosure provides a fault injection method, a fault injector, a storage medium, and a fault injection system, where the fault injector is in communication connection with an SRAM-type FPGA, the FPGA includes a circuit to be injected, and the method includes: receiving a fault injection mode selected by a user and fault parameters corresponding to the fault injection mode input by the user, generating a fault configuration file according to the fault injection mode and the fault parameters corresponding to the fault injection mode, and injecting the fault configuration file into a circuit to be injected of the FPGA to realize fault injection, wherein the fault injection mode is any one of a manual injection mode, a bit-by-bit injection mode and an accumulative injection mode.
Description
Technical Field
The present application relates to the field of technologies, and in particular, to a fault injection method, a fault injector, a storage medium, and a fault injection system.
Background
Static Random-Access Memory (SRAM) type Field Programmable Gate Array (FPGA) is widely used in the Field of aviation due to its advantages of repeatable configuration, high flexibility, rich resources, etc., the internal resources of SRAM type FPFA are realized by SRAM type storage units, which are very sensitive to spatial radiation, and the normal operation of FPGA is seriously threatened by the single event upset generated by the spatial heavy ions and protons.
The single event upset refers to a change in logic state of a circuit caused by single event radiation, i.e., a logic "1" changes to a logic "0", or a logic "0" changes to a logic "1", which may cause a disorder in the logic function of the circuit. The fault mode which can be simulated by the existing fault injection technology is single, only single-bit upset fault simulation under the single event effect is concerned, and the same common double-bit upset error is not realized.
Disclosure of Invention
It is a primary object of the present application to provide a fault injection method, a fault injector, a storage medium and a fault injection system, which can solve at least one of the above problems.
In order to achieve the above object, a first aspect of the embodiments of the present application provides a fault injection method applied to a fault injector, where the fault injector is communicatively connected to an SRAM-type FPGA, and the FPGA includes a circuit to be injected, where the method includes:
receiving a fault injection mode selected by a user and fault parameters corresponding to the fault injection mode input by the user;
generating a fault configuration file according to the fault injection mode and the fault parameters corresponding to the fault injection mode;
injecting the fault configuration file into a circuit to be injected of the FPGA to realize fault injection;
wherein the fault injection mode is any one of a manual injection mode, a bitwise injection mode and an accumulation injection mode.
Optionally, when the fault injection mode is a manual injection mode, the fault parameters corresponding to the manual injection mode include a fault frame, a fault bit, and a fault type;
when the fault injection mode is a bitwise injection mode, fault parameters corresponding to the bitwise injection mode comprise a fault frame range, waiting time and a fault type, wherein the waiting time is a time interval between two fault injections;
when the fault injection mode is an accumulated injection mode, the fault parameters corresponding to the accumulated injection mode include a fault frame range, an LET value, a fault injection speed, a fluence and a fault type.
Optionally, the fault type in the fault parameter corresponding to the manual injection mode, the bitwise injection mode, and the accumulative injection mode is any one of single bit flipping, adjacent column double bit flipping, adjacent row double bit flipping, and diagonal double bit flipping.
Optionally, the FPGA further includes a fault injection circuit, and the method further includes:
generating a bit stream file, wherein the bit stream file comprises bit stream data of the fault injection circuit and bit stream data of a circuit to be injected, the bit stream data of the fault injection circuit is used for enabling the fault injection circuit to realize fault injection on the circuit to be injected, the bit stream data of the circuit to be injected is used for dividing a reconfigurable area in the FPGA, and the reconfigurable area is used for laying out the circuit to be injected;
and downloading the bit stream file into the FPGA.
Optionally, the fault configuration file includes a fault injection mode, a fault type, a total number of faults, a waiting time, a fault injection speed, and a fault address, where the fault address includes a frame address where the fault is located and a bit address where the fault is located.
Optionally, the method further includes:
when the fault injection mode is an accumulated injection mode, acquiring the times of fault injection to the circuit to be injected and the equivalent injection quantity when the circuit to be injected has function interruption after the fault is injected to the circuit to be injected each time;
adding equivalent fluence when the circuit to be injected has functional interruption after each fault is injected into the circuit to be injected to obtain equivalent total fluence under the times;
and dividing the times by the equivalent total fluence to obtain a function interruption section of the circuit to be injected.
A second aspect of embodiments of the present application provides a fault injector, communicatively connected to an SRAM-type FPGA, where the FPGA includes a circuit to be injected, and the fault injector includes:
the system comprises a receiving module, a judging module and a judging module, wherein the receiving module is used for receiving a fault injection mode selected by a user and fault parameters which are input by the user and correspond to the fault injection mode;
the generating module is used for generating a fault configuration file according to the fault injection mode and the fault parameters corresponding to the fault injection mode;
the injection module is used for injecting the fault configuration file into a circuit to be injected of the FPGA to realize fault injection;
wherein the fault injection mode is any one of a manual injection mode, a bitwise injection mode and an accumulation injection mode.
A third aspect of embodiments of the present application provides a fault injector, comprising:
the fault injection method includes a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the program to implement the fault injection method provided by the first aspect of the embodiment of the present application.
A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the fault injection method provided in the first aspect of the embodiments of the present application.
A second aspect of the embodiments of the present application provides a fault injection system, including a fault injector and an SRAM-type FPGA as described in the second or third aspect, where the fault injector is communicatively connected to the FPGA;
the FPGA comprises a fault injection circuit and a circuit to be injected, the fault injection circuit is connected with the circuit to be injected, the fault injection circuit is used for realizing fault injection on the circuit to be injected, and the circuit to be injected is arranged in a reconfigurable area.
As can be seen from the foregoing embodiments of the present application, the fault injection method, the fault injector, the storage medium, and the fault injection system provided in the present application include a manual injection mode, a bit-by-bit injection mode, and an accumulative injection mode, which can make up for the defect that the fault mode that can be simulated by the existing internal fault injection technology is relatively single. And the more strict and complete simulation of the single event effect under different irradiation environments and the evaluation and calculation of the function interruption section of the FPGA under different irradiation environments are realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flowchart of a fault injection method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a fault injector according to an embodiment of the present application;
fig. 3 is a schematic hardware structure diagram of a fault injector according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a fault injection system according to an embodiment of the present application.
Detailed Description
In order to make the purpose, features and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart of a fault injection method according to an embodiment of the present application, where the fault injection method is applied to a fault injector, the fault injector is in communication connection with an SRAM-type FPGA, the FPGA includes a circuit to be injected, and the method includes:
s101, receiving a fault injection mode selected by a user and a fault parameter corresponding to the fault injection mode input by the user.
And S102, generating a fault configuration file according to the fault injection mode and the fault parameters corresponding to the fault injection mode.
S103, injecting the fault configuration file into a circuit to be injected of the FPGA to realize fault injection.
The fault injection mode is any one of a manual injection mode, a bitwise injection mode and an accumulation injection mode.
In the present disclosure, the fault injector provides three fault injection modes, i.e., manual injection mode, bitwise injection mode, cumulative injection mode. The manual injection mode is used for generating a fault of a specified type in a position specified by a user; and generating the fault of the instruction type bit by bit sequentially in the frame address range specified by the user according to the ascending order of the addresses in the bit-by-bit injection mode. Under the mode of bit-by-bit injection, the fault generated at the last time can be repaired while the fault is generated every time; and in the accumulative injection mode, faults of a specified type are randomly generated in a frame address range specified by a user, and the faults injected last time cannot be repaired while the faults are injected each time.
In the disclosure, more circuits to be injected can be externally connected with an LED indicator lamp, so that whether the circuits to be injected have functional faults or not after the faults are injected can be more intuitively indicated.
In the present disclosure, the model of the FPGA and the specific type of the circuit to be injected are not limited.
In one embodiment of the present disclosure, when the fault injection mode is a manual injection mode, the fault parameters corresponding to the manual injection mode include a fault frame, a fault bit, and a fault type; when the fault injection mode is a bitwise injection mode, fault parameters corresponding to the bitwise injection mode comprise a fault frame range, waiting time and a fault type, wherein the waiting time is a time interval between two fault injections; when the fault injection mode is the accumulation injection mode, the fault parameters corresponding to the accumulation injection mode comprise a fault frame range, an LET value, a fault injection speed, a fluence and a fault type.
In one embodiment of the present disclosure, the fault types in the fault parameters corresponding to the manual injection mode, the bitwise injection mode, and the accumulative injection mode are any one of single bit flipping, adjacent column double bit flipping, adjacent row double bit flipping, and diagonal bit double bit flipping. Namely, under the three fault modes, four fault types of single-bit turnover, adjacent-column double-bit turnover, adjacent-row double-bit turnover and diagonal double-bit turnover are supported.
In this disclosure, a single bit upset refers to a certain bit injection failure within a certain frame specified by the user; the adjacent column double-bit flipping means that a fault is injected at a bit position designated by a user and the next bit position in the same frame; the adjacent row double-bit overturning means that faults are injected at the same bit position in the appointed bit position and the next frame; diagonal double bit flipping refers to injecting a fault at a specified bit position and the next bit in the next frame.
In one embodiment of the present disclosure, the FPGA further includes a fault injection circuit, and the fault injection method further includes:
generating a bit stream file, wherein the bit stream file comprises bit stream data of the fault injection circuit and bit stream data of a circuit to be injected, the bit stream data of the fault injection circuit is used for enabling the fault injection circuit to realize fault injection on the circuit to be injected, the bit stream data of the circuit to be injected is used for dividing a reconfigurable area in the FPGA, and the reconfigurable area is used for laying out the circuit to be injected; the bitstream file is downloaded into the FPGA.
Wherein, understandably, the circuit to be injected can be refreshed and replaced in the reconfigurable area under the condition of not influencing the operation of the fault injection circuit.
In the present disclosure, the specific process of fault injection of the fault injection circuit is as follows: acquiring a frame address where the fault is located and a bit address where the fault is located in the fault configuration file; acquiring a frame where the fault is located in the circuit to be injected according to the frame address where the fault is located; obtaining a value corresponding to a bit address where the fault is located in the circuit to be injected; performing XOR between the value corresponding to the bit address of the fault in the circuit to be injected and the '1' to realize the bit inversion and obtain the modified frame; and writing the modified frame into the frame address where the fault is located to realize fault injection.
In the method, the NGC netlist file of the fault injection circuit and the NGC netlist file of the circuit to be injected are synthesized, the circuit to be injected is arranged in a defined reconfigurable area, and finally a bit stream file is generated.
In the present disclosure, the fault injection circuit uses MicroBlaze as a processor, and implements fault injection by controlling ICAP to rewrite configuration frames of reconfigurable regions.
In the present disclosure, for example, a planhead design tool may be used to generate a bitstream file, and the Xilinx SDK may be used to download the generated bitstream file into the FPGA to configure the FPGA. Understandably, the Xilinx SDK can control the operation of the fault injection circuit according to the fault configuration file, and can also display the state information of the current fault injection process.
In one embodiment of the present disclosure, the fault profile includes a fault injection mode, a fault type, a total number of faults, a waiting time, a fault injection speed, and a fault address, where the fault address includes a frame address where the fault is located and a bit address where the fault is located.
In the present disclosure, running the Xilinx SDK, for example, can inject a fault described by a fault profile into the circuit to be injected,
in one embodiment of the present disclosure, the fault injection method further includes: when the fault injection mode is an accumulation injection mode, acquiring the times of fault injection to the circuit to be injected and the equivalent injection quantity when the circuit to be injected has function interruption after the fault is injected to the circuit to be injected each time; adding equivalent fluence when the circuit to be injected has function interruption after each fault is injected into the circuit to be injected to obtain equivalent total fluence at the times; dividing the number by the equivalent total fluence to obtain the functional interruption cross section of the circuit to be injected.
In the present disclosure, a calculator may also be provided in the fault injector for performing the above-described calculation of the functional interruption section. In the above calculation process of the functional interruption section, for example, assuming that three fault injection experiments are performed in the cumulative injection mode, and the equivalent fluences are n1, n2 and n3 respectively when the functional interruption occurs in each fault injection, the number of times of functional interruption is 3, the equivalent total fluences are (n1+ n2+ n3), and the functional interruption section is 3/(n1+ n2+ n 3).
Furthermore, the fault injector can also realize a result evaluation function, namely track prediction according to the function interruption section calculated by the steps.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a fault injector communicatively connected to an SRAM-type FPGA including a circuit to be injected according to an embodiment of the present application, the fault injector including:
a receiving module 201, configured to receive a fault injection mode selected by a user and a fault parameter corresponding to the fault injection mode input by the user;
a generating module 202, configured to generate a fault configuration file according to the fault injection mode and a fault parameter corresponding to the fault injection mode;
the injection module 203 is configured to inject the fault configuration file into a circuit to be injected of the FPGA to implement fault injection;
the fault injection mode is any one of a manual injection mode, a bitwise injection mode and an accumulation injection mode.
In one embodiment of the present disclosure, when the fault injection mode is a manual injection mode, the fault parameters corresponding to the manual injection mode include a fault frame, a fault bit, and a fault type;
when the fault injection mode is a bitwise injection mode, fault parameters corresponding to the bitwise injection mode comprise a fault frame range, waiting time and a fault type, wherein the waiting time is a time interval between two fault injections;
when the fault injection mode is the accumulation injection mode, the fault parameters corresponding to the accumulation injection mode comprise a fault frame range, an LET value, a fault injection speed, a fluence and a fault type.
In one embodiment of the present disclosure, the fault types in the fault parameters corresponding to the manual injection mode, the bitwise injection mode, and the accumulative injection mode are any one of single bit flipping, adjacent column double bit flipping, adjacent row double bit flipping, and diagonal double bit flipping.
In one embodiment of the present disclosure, the FPGA further includes a fault injection circuit, and the fault injection apparatus further includes:
a file generating module, configured to generate a bitstream file, where the bitstream file includes bitstream data of the fault injection circuit and bitstream data of a circuit to be injected, where the bitstream data of the fault injection circuit is used to enable the fault injection circuit to perform fault injection on the circuit to be injected, and the bitstream data of the circuit to be injected is used to partition a reconfigurable area in the FPGA, where the reconfigurable area is used to lay out the circuit to be injected;
and the downloading module is used for downloading the bit stream file into the FPGA.
In one embodiment of the present disclosure, the fault profile includes a fault injection mode, a fault type, a total number of faults, a waiting time, a fault injection speed, and a fault address, where the fault address includes a frame address where the fault is located and a bit address where the fault is located.
In one embodiment of the present disclosure, the fault injection apparatus further includes:
the acquisition module is used for acquiring the times of fault injection to the circuit to be injected and the equivalent fluence of the circuit to be injected when the function of the circuit to be injected is interrupted after the fault injection to the circuit to be injected each time;
the adding module is used for adding equivalent fluence of the circuit to be injected when the circuit to be injected has function interruption after each fault is injected into the circuit to be injected to obtain equivalent total fluence at the times;
and the division module is used for dividing the times by the equivalent total fluence to obtain the function interruption section of the circuit to be injected.
Referring to fig. 3, fig. 3 shows a hardware structure diagram of a fault injector.
The electronic device described in this embodiment includes:
a memory 31, a processor 32 and a computer program stored on the memory 31 and executable on the processor, the processor implementing the synchronous control method of the multi-axis motion system described in the foregoing embodiment shown in fig. 1 when executing the program.
Further, the electronic device further includes:
at least one input device 33; at least one output device 34.
The memory 31, processor 32 input device 33 and output device 34 are connected by a bus 35.
The input device 33 may be a camera, a touch panel, a physical button, or a mouse. The output device 34 may specifically be a display screen.
The Memory 31 may be a high-speed Random Access Memory (RAM) Memory or a non-volatile Memory (non-volatile Memory), such as a disk Memory. The memory 31 is used for storing a set of executable program code, and the processor 32 is coupled to the memory 31.
Further, the embodiment of the present disclosure also provides a computer-readable storage medium, which may be disposed in the electronic device in the foregoing embodiments, and the computer-readable storage medium may be the fault injector in the foregoing embodiment shown in fig. 3. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the fault injection method described in the foregoing illustrated embodiments. Further, the computer-readable storage medium may be various media that can store program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a fault injection system according to an embodiment of the present application, the fault injection system includes a fault injector and an SRAM-type FPGA as described in any one of the above, and the fault injector 100 is communicatively connected to the FPGA 200; the FPGA200 includes a fault injection circuit 210 and a circuit to be injected 220, the fault injection circuit 210 is connected to the circuit to be injected 220, the fault injection circuit 210 is configured to implement fault injection on the circuit to be injected 210, and the circuit to be injected 220 is disposed in the reconfigurable area.
It should be noted that each functional module in each embodiment of the present disclosure may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially embodied in the form of a software product, or all or part of the technical solution that contributes to the prior art.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above description is provided for the fault injection method, the fault injector, the storage medium and the fault injection system, and for those skilled in the art, there may be variations in the specific implementation and application scope according to the ideas of the embodiments of the present invention, and in summary, the content of the present specification should not be construed as limiting the present invention.
Claims (10)
1. A fault injection method applied to a fault injector communicatively connected to an FPGA of the SRAM type, said FPGA comprising a circuit to be injected, said method comprising:
receiving a fault injection mode selected by a user and fault parameters corresponding to the fault injection mode input by the user;
generating a fault configuration file according to the fault injection mode and the fault parameters corresponding to the fault injection mode;
injecting the fault configuration file into a circuit to be injected of the FPGA to realize fault injection;
wherein the fault injection mode is any one of a manual injection mode, a bitwise injection mode and an accumulation injection mode.
2. The fault injection method of claim 1,
when the fault injection mode is a manual injection mode, fault parameters corresponding to the manual injection mode comprise a fault frame, a fault bit and a fault type;
when the fault injection mode is a bitwise injection mode, fault parameters corresponding to the bitwise injection mode comprise a fault frame range, waiting time and a fault type, wherein the waiting time is a time interval between two fault injections;
when the fault injection mode is an accumulated injection mode, the fault parameters corresponding to the accumulated injection mode include a fault frame range, an LET value, a fault injection speed, a fluence and a fault type.
3. The fault injection method according to claim 2, wherein the fault types in the fault parameters corresponding to the manual injection mode, the bitwise injection mode and the accumulative injection mode are any one of single bit flipping, adjacent column double bit flipping, adjacent row double bit flipping and diagonal bit double bit flipping.
4. The fault injection method of claim 1, wherein the FPGA further comprises fault injection circuitry, the method further comprising:
generating a bit stream file, wherein the bit stream file comprises bit stream data of the fault injection circuit and bit stream data of a circuit to be injected, the bit stream data of the fault injection circuit is used for enabling the fault injection circuit to realize fault injection on the circuit to be injected, the bit stream data of the circuit to be injected is used for dividing a reconfigurable area in the FPGA, and the reconfigurable area is used for laying out the circuit to be injected;
and downloading the bit stream file into the FPGA.
5. The fault injection method according to claim 1, wherein the fault configuration file comprises fault injection modes, fault types, total number of faults, waiting time, fault injection speed and fault addresses, and the fault addresses comprise a frame address where the fault is located and a bit address where the fault is located.
6. The fault injection method of claim 1, further comprising:
when the fault injection mode is an accumulated injection mode, acquiring the times of fault injection to the circuit to be injected and the equivalent injection quantity when the circuit to be injected has function interruption after the fault is injected to the circuit to be injected each time;
adding equivalent fluence when the circuit to be injected has functional interruption after each fault is injected into the circuit to be injected to obtain equivalent total fluence under the times;
and dividing the times by the equivalent total fluence to obtain a function interruption section of the circuit to be injected.
7. A fault injector communicatively connected to an SRAM-type FPGA, the FPGA including circuitry to be injected, the fault injector comprising:
the system comprises a receiving module, a judging module and a judging module, wherein the receiving module is used for receiving a fault injection mode selected by a user and fault parameters which are input by the user and correspond to the fault injection mode;
the generating module is used for generating a fault configuration file according to the fault injection mode and the fault parameters corresponding to the fault injection mode;
the injection module is used for injecting the fault configuration file into a circuit to be injected of the FPGA to realize fault injection;
wherein the fault injection mode is any one of a manual injection mode, a bitwise injection mode and an accumulation injection mode.
8. A fault injector, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the fault injection method according to any of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the fault injection method of any one of claims 1 to 6.
10. A fault injection system comprising a fault injector according to claim 8 or 9 and an SRAM type FPGA, said fault injector being communicatively connected to said FPGA;
the FPGA comprises a fault injection circuit and a circuit to be injected, the fault injection circuit is connected with the circuit to be injected, the fault injection circuit is used for realizing fault injection on the circuit to be injected, and the circuit to be injected is arranged in a reconfigurable area.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113254288A (en) * | 2021-06-02 | 2021-08-13 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050050393A1 (en) * | 2003-08-26 | 2005-03-03 | Chakraborty Tapan J. | Fault injection method and system |
| US7409610B1 (en) * | 2005-07-20 | 2008-08-05 | Xilinx, Inc. | Total configuration memory cell validation built in self test (BIST) circuit |
| US20120144244A1 (en) * | 2010-12-07 | 2012-06-07 | Yie-Fong Dan | Single-event-upset controller wrapper that facilitates fault injection |
| CN103198868A (en) * | 2013-04-16 | 2013-07-10 | 西北核技术研究所 | Fault simulation system and fault analysis method for single event upset |
| CN103473159A (en) * | 2013-10-13 | 2013-12-25 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) configuration information turnover testing platform based on dynamic reconfiguration and testing method |
| CN103617121A (en) * | 2013-12-09 | 2014-03-05 | 北京京航计算通讯研究所 | Method for building AD/DA interface fault model on basis of NI platform |
| CN105548866A (en) * | 2015-12-08 | 2016-05-04 | 中国科学院电子学研究所 | SRAM type FPGA test method based on irradiation test environment simulation |
| CN105974905A (en) * | 2016-05-10 | 2016-09-28 | 中国民航大学 | Simulated test system and method for single-particle overturn fault of aviation data bus |
| CN106124970A (en) * | 2016-06-17 | 2016-11-16 | 工业和信息化部电子第五研究所 | The fault filling method of SRAM type FPGA and device |
| CN107092539A (en) * | 2017-02-24 | 2017-08-25 | 北京时代民芯科技有限公司 | A kind of FPGA direct fault location composite models based on configuration bit stream |
| CN107144783A (en) * | 2017-05-10 | 2017-09-08 | 哈尔滨工业大学 | Support unit and the SRAM type FPGA appraisal procedures of multidigit direct fault location |
| CN107741559A (en) * | 2017-10-12 | 2018-02-27 | 电子科技大学 | Single-particle inversion test system and method under a kind of space-oriented radiation environment |
| CN107895087A (en) * | 2017-11-29 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | The method and system that the emulation of PLD module level automatically generates with code |
| CN108228454A (en) * | 2017-12-29 | 2018-06-29 | 中国船舶工业综合技术经济研究院 | A kind of electronic product software reliability assessment method based on environmental bug injection |
| CN110188441A (en) * | 2019-05-23 | 2019-08-30 | 西北核技术研究院 | Without Multiple-bit upsets information extracting method under the conditions of layout information |
| CN111651715A (en) * | 2020-06-01 | 2020-09-11 | 中国科学院空天信息创新研究院 | Data processing method, processor, device and medium based on FPGA |
| GB202011901D0 (en) * | 2020-07-30 | 2020-09-16 | Imagination Tech Ltd | Methods and systems for fault injection testing of an integrated circuit hardware design |
-
2020
- 2020-12-30 CN CN202011603468.1A patent/CN112596506A/en active Pending
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050050393A1 (en) * | 2003-08-26 | 2005-03-03 | Chakraborty Tapan J. | Fault injection method and system |
| US7409610B1 (en) * | 2005-07-20 | 2008-08-05 | Xilinx, Inc. | Total configuration memory cell validation built in self test (BIST) circuit |
| US20120144244A1 (en) * | 2010-12-07 | 2012-06-07 | Yie-Fong Dan | Single-event-upset controller wrapper that facilitates fault injection |
| CN103198868A (en) * | 2013-04-16 | 2013-07-10 | 西北核技术研究所 | Fault simulation system and fault analysis method for single event upset |
| CN103473159A (en) * | 2013-10-13 | 2013-12-25 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) configuration information turnover testing platform based on dynamic reconfiguration and testing method |
| CN103617121A (en) * | 2013-12-09 | 2014-03-05 | 北京京航计算通讯研究所 | Method for building AD/DA interface fault model on basis of NI platform |
| CN105548866A (en) * | 2015-12-08 | 2016-05-04 | 中国科学院电子学研究所 | SRAM type FPGA test method based on irradiation test environment simulation |
| CN105974905A (en) * | 2016-05-10 | 2016-09-28 | 中国民航大学 | Simulated test system and method for single-particle overturn fault of aviation data bus |
| CN106124970A (en) * | 2016-06-17 | 2016-11-16 | 工业和信息化部电子第五研究所 | The fault filling method of SRAM type FPGA and device |
| CN107092539A (en) * | 2017-02-24 | 2017-08-25 | 北京时代民芯科技有限公司 | A kind of FPGA direct fault location composite models based on configuration bit stream |
| CN107144783A (en) * | 2017-05-10 | 2017-09-08 | 哈尔滨工业大学 | Support unit and the SRAM type FPGA appraisal procedures of multidigit direct fault location |
| CN107741559A (en) * | 2017-10-12 | 2018-02-27 | 电子科技大学 | Single-particle inversion test system and method under a kind of space-oriented radiation environment |
| CN107895087A (en) * | 2017-11-29 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | The method and system that the emulation of PLD module level automatically generates with code |
| CN108228454A (en) * | 2017-12-29 | 2018-06-29 | 中国船舶工业综合技术经济研究院 | A kind of electronic product software reliability assessment method based on environmental bug injection |
| CN110188441A (en) * | 2019-05-23 | 2019-08-30 | 西北核技术研究院 | Without Multiple-bit upsets information extracting method under the conditions of layout information |
| CN111651715A (en) * | 2020-06-01 | 2020-09-11 | 中国科学院空天信息创新研究院 | Data processing method, processor, device and medium based on FPGA |
| GB202011901D0 (en) * | 2020-07-30 | 2020-09-16 | Imagination Tech Ltd | Methods and systems for fault injection testing of an integrated circuit hardware design |
Non-Patent Citations (3)
| Title |
|---|
| 李 林，徐 宇，卢凌云，贾海涛，: "基于SRAM型FPGA的数字系统容错机制研究", 《微电子学与计算机》, vol. 32, no. 12, 5 December 2015 (2015-12-05), pages 95 - 99 * |
| 舒德刚: "SRAM型FPGA单粒子翻转定向故障注入技术研究", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》 * |
| 舒德刚: "SRAM型FPGA单粒子翻转定向故障注入技术研究", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》, no. 02, 15 February 2020 (2020-02-15) * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113254288A (en) * | 2021-06-02 | 2021-08-13 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
| CN113254288B (en) * | 2021-06-02 | 2021-09-21 | 中国人民解放军国防科技大学 | FPGA single event upset fault injection method in satellite-borne equipment |
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