CN106057822A - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN106057822A CN106057822A CN201610618971.1A CN201610618971A CN106057822A CN 106057822 A CN106057822 A CN 106057822A CN 201610618971 A CN201610618971 A CN 201610618971A CN 106057822 A CN106057822 A CN 106057822A
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- Prior art keywords
- cushion
- ito
- array base
- base palte
- noncrystal
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a passivation layer, buffer layers and a metal reflective layer orderly arranged from bottom to top. The buffer layers comprise at least one first buffer layer and at least one second buffer layer arranged on the first layer, and the first buffer layer and the second buffer layer have different densities. The invention provides an array substrate, the problem of the corrosion of a lower metal layer by a metal corrosion liquid can be avoided, thus the yield of products is improved, and the cost of the products is reduced.
Description
Technical field
The present invention relates to Display Technique field, in particular it relates to a kind of array base palte and preparation method thereof, display device.
Background technology
At present, Thin Film Transistor-LCD (TFT-LCD) has been widely used in various flat pannel display, movement shows
Show, in the product such as TV.
Fig. 1 is the structural representation of existing array base palte.Referring to Fig. 1, array base palte includes grid the most successively
Electrode layer 1, gate insulation layer 2, active layer 3, S/D metal level (4,5), 6, two ITO layer (7,8) of passivation layer and metallic reflector 9.
During making above-mentioned array base palte, two ITO layer (7,8) are arranged on crimp region, and cover in passivation
The via 10 of layer 6, in order to as cabling bonding layer, overlap joint control circuit (IC).Metallic reflector 9 is used as reflecting layer and electrode
Layer, it is provided only on viewing area, and is not arranged in crimp region (not covering the via 10 at passivation layer 6), to avoid controlling
Circuit crimping departs from, and therefore, during making metallic reflector 9, needs to use metal etch liquid by crimp region
Metal level is removed.
But, owing to the film quality (consistency) of two ITO layer (7,8) is identical, using metal etch liquid etching crimping district
During the metal level in territory (via 10 is positioned at this region), metal etch liquid can pass through two ITO layer (7,8), corrodes lower metal
Layer, such as, penetrate into S/D metal level by via 10, thus cause wiring circuit contact bad, produces the defects such as concealed wire.
Summary of the invention
It is contemplated that at least solve one of technical problem present in prior art, it is proposed that a kind of array base palte and
Manufacture method, display device, its can avoid lower metal layer by the problem of metal etch corrosion, such that it is able to improve product
Yield, reduces product cost.
A kind of array base palte is provided for realizing the purpose of the present invention, including the passivation layer from bottom to top set gradually, delays
Rushing layer and metallic reflector, described cushion includes that at least one of which the first cushion and at least one of which second being disposed thereon are delayed
Rushing layer, the consistency of the two is different.
Optionally, described first cushion is the crystalline solid of ITO;Described second cushion is the noncrystal of ITO.
Optionally, described first cushion and the second cushion are the crystalline solid of ITO;Or,
Described first cushion and the second cushion are the noncrystal of ITO.
Optionally, described first cushion is crystalline solid or the noncrystal of ITO of ITO, and buffers described first
Layer the surface contacted with described second cushion be formed plasma treated after levelling blanket;
Described second cushion is crystalline solid or the noncrystal of ITO of ITO, and described levelling blanket delays with described second
The consistency rushing layer is different.
Optionally, described metallic reflector includes any one or any at least two group in Al, Mo, Cu, Ti, Nb
The alloy become.
Optionally, described passivation layer includes SiNx, SiOx or SiON.
As another technical scheme, the present invention also provides for the manufacture method of a kind of array base palte, comprises the following steps:
Described passivation layer is formed cushion;
Described cushion is formed metallic reflector;
Wherein, described cushion includes that at least one of which the first cushion and at least one of which second being disposed thereon buffer
Layer, the consistency of the two is different.
Optionally, described first cushion is the crystalline solid of ITO;Described second cushion is the noncrystal of ITO.
Optionally, described first cushion and the second cushion are the crystalline solid of ITO;Or,
Described first cushion and the second cushion are the noncrystal of ITO.
Optionally, form the film forming power that described first cushion used to be used less than forming described second cushion
Film forming power;Meanwhile, form the film forming air pressure that described first cushion used to be adopted higher than forming described second cushion
Film forming air pressure.
Optionally, described first cushion is crystalline solid or the noncrystal of ITO of ITO;Described second cushion is
The crystalline solid of ITO or the noncrystal of ITO;
Before being formed after described first cushion, and forming described second cushion, also include:
The surface contacted with described second cushion of described first cushion is carried out plasma treatment, flat to be formed
Flood;Further, described levelling blanket is different from the consistency of described second cushion.
As another technical scheme, the present invention also provides for a kind of display device, including array base palte, described array base palte
Use the above-mentioned array base palte that the present invention provides.
The method have the advantages that
The array base palte that the present invention provides, its cushion being arranged between passivation layer and metallic reflector includes at least one
Layer the first cushion and at least one of which the second cushion being disposed thereon, and by making the consistency difference of the two, permissible
The grain boundary defects avoiding the first cushion and the second cushion is overlapping, such that it is able to avoid metal etch liquid to pass cushion, and
Corrosion lower metal layer, and then product yield can be improved, reduce product cost.
The manufacture method of the array base palte that the present invention provides, it is arranged on the cushion between passivation layer and metallic reflector
Including at least one of which the first cushion and at least one of which the second cushion being disposed thereon, and by making the consistency of the two
Difference, the grain boundary defects that can avoid the first cushion and the second cushion is overlapping, such that it is able to avoid metal etch liquid to pass
Cushion, and corrode lower metal layer, and then product yield can be improved, reduce product cost.
The display device that the present invention provides, its above-mentioned array base palte provided by using the present invention, metal can be avoided
Etching liquid passes cushion, and corrodes lower metal layer, and then can improve product yield, reduces product cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing array base palte;
The structural representation of the array base palte that Fig. 2 provides for the embodiment of the present invention.
Detailed description of the invention
For making those skilled in the art be more fully understood that technical scheme, come the present invention below in conjunction with the accompanying drawings
Array base palte provided and preparation method thereof is described in detail.
The structural representation of the array base palte that Fig. 2 provides for the embodiment of the present invention.Refer to Fig. 2, array base palte by lower and
On include gate electrode layer 1, gate insulation layer 2, active layer 3, S/D metal level (4,5), passivation layer 6, cushion and metallic reflection successively
Layer 9.Wherein, metallic reflector 9 is positioned at the echo area of array base palte, and is positioned at the right side of the via 10 of passivation layer 6.
In the present embodiment, cushion includes the first cushion 11 and the second cushion 12 being disposed thereon, the two
Consistency is different.This can be avoided the grain boundary defects overlap of the first cushion 11 and the second cushion 12, such that it is able to avoid position
The etching liquid of the metallic reflector 9 on cushion passes this cushion, and corrodes lower metal layer, and then can improve product
Product yield, reduces product cost.
Below the detailed description of the invention of the first cushion 11 and the second cushion 12 is described in detail.Specifically,
A kind of embodiment, the first cushion 11 is the crystalline solid (P-ITO) of ITO;Second cushion 12 is the noncrystal (A-of ITO
ITO).Owing to the consistency of crystalline solid of ITO is higher than the noncrystal of ITO, the consistency of the two is different, such that it is able to avoid the
The grain boundary defects of one cushion 11 and the second cushion 12 is overlapping, and owing to the consistency of the crystalline solid of ITO is higher, by making
It is closer to the passivation layer 6 of lower floor, is more beneficial for protecting lower metal layer, such that it is able to further enhance metal etch liquid
Barrier effect.
The second embodiment, the first cushion 11 and the second cushion 12 are the crystalline solid of ITO;Or, first delays
Rush layer and the second cushion is the noncrystal of ITO.It is to say, the first cushion 11 and the second cushion 12 all use
The crystalline solid of ITO or the noncrystal of ITO, but the consistency of the two is different, and this is equally avoided the first cushion 11 He
The grain boundary defects of the second cushion 12 is overlapping.Preferably, the consistency of the first cushion 11 can be made to be higher than the second cushion 12,
To further enhance the barrier effect to metal etch liquid.
The third embodiment, the first cushion 11 is crystalline solid or the noncrystal of ITO of ITO, and delays first
Rush the surface contacted with the second cushion 12 of layer 11 be formed plasma treated after levelling blanket.Second cushion 12 is
The crystalline solid of ITO or the noncrystal of ITO, and the consistency of this levelling blanket and the second cushion 12 is different, such that it is able to keep away
The grain boundary defects exempting from the first cushion 11 and the second cushion 12 is overlapping.So-called Cement Composite Treated by Plasma, refers to pass through plasma
Physics, chemical reaction is there is with the surface contacted with the second cushion 12 of the first cushion 11, thus shape on a surface
One-tenth surface is more cleaned, smooth levelling blanket.
It should be noted that in above-mentioned three kinds of embodiments, the first cushion 11 and the second respective quantity of cushion 12
Can be more than one layer or two-layer.
In actual applications, optionally, metallic reflector 9 include in Al, Mo, Cu, Ti, Nb any one or arbitrarily
The alloy of at least two composition.
In actual applications, optionally, passivation layer 6 includes SiNx, SiOx or SiON etc..
As another technical scheme, the present invention also provides for the manufacture method of a kind of array base palte, and it comprises the following steps:
Form cushion over the passivation layer.
Form metallic reflector on the buffer layer.
Wherein, cushion includes at least one of which the first cushion and at least one of which the second cushion being disposed thereon, two
The consistency of person is different.This can be avoided the grain boundary defects overlap of the first cushion and the second cushion, such that it is able to avoid position
The etching liquid of the metallic reflector on cushion passes this cushion, and corrodes lower metal layer, and then can improve product
Product yield, reduces product cost.
Optionally, above-mentioned first cushion is the crystalline solid of ITO;Second cushion is the noncrystal of ITO.Due to ITO
The consistency of crystalline solid higher than the noncrystal of ITO, the consistency of the two is different, such that it is able to avoid the first cushion and the
The grain boundary defects of two cushions is overlapping, and owing to the consistency of the crystalline solid of ITO is higher, by being disposed at the non-of ITO
The lower floor of crystalline solid, can further enhance the barrier effect to metal etch liquid.
Optionally, the first cushion and the second cushion are the crystalline solid of ITO;Or, the first cushion and second delays
Rush layer and be the noncrystal of ITO.It is to say, the first cushion and the second cushion all use the crystalline solid of ITO or ITO's
Noncrystal, but the consistency of the two is different, and this is equally avoided the first cushion and the grain boundary defects of the second cushion
Overlapping.Preferably, the consistency that can make the first cushion is higher than the second cushion, to further enhance metal etch liquid
Barrier effect.
Preferably, the consistency making the first cushion is higher than the method for the second cushion particularly as follows: form the first cushion
The film forming power used is less than forming the film forming power that the second cushion is used;Meanwhile, form the first cushion to be used
Film forming air pressure higher than forming the film forming air pressure that used of the second cushion.
Optionally, the first cushion is crystalline solid or the noncrystal of ITO of ITO;Second cushion is the crystallization of ITO
Body or the noncrystal of ITO.And, after forming the first cushion, and before formation the second cushion, also include:
The surface contacted with the second cushion of the first cushion is carried out plasma treatment, to form levelling blanket, should
The consistency of levelling blanket and the second cushion is different, such that it is able to avoid the grain boundary defects weight of the first cushion and the second cushion
Folded.So-called Cement Composite Treated by Plasma, refers to be sent out by the surface contacted with the second cushion of plasma and the first cushion
Biological reason, chemical reaction, thus formed on a surface surface more clean, smooth levelling blanket.
Structure and the present invention of the array base palte of the manufacture method acquisition of the array base palte of embodiment of the present invention offer are provided
The structure of the array base palte that embodiment provides is identical, as in figure 2 it is shown, due to before the array base palte that the embodiment of the present invention provides
State and technical scheme there has been detailed description, be not described in detail at this.
The manufacture method of the array base palte that the embodiment of the present invention provides, it can avoid the first cushion and the second cushion
Grain boundary defects overlapping, such that it is able to avoid metal etch liquid through cushion, and corrode lower metal layer, and then can improve
Product yield, reduces product cost.
As another technical scheme, the embodiment of the present invention also provides for a kind of display device, including array base palte, this array
Substrate uses the above-mentioned array base palte that the embodiment of the present invention provides.
The display device that the embodiment of the present invention provides, its above-mentioned array base palte provided by using the embodiment of the present invention,
Metal etch liquid can be avoided to pass cushion, and corrode lower metal layer, and then product yield can be improved, reduce product and become
This.
It is understood that the principle that is intended to be merely illustrative of the present of embodiment of above and the exemplary enforcement that uses
Mode, but the invention is not limited in this.For those skilled in the art, in the essence without departing from the present invention
In the case of god and essence, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (12)
1. an array base palte, including the passivation layer from bottom to top set gradually, cushion and metallic reflector, its feature exists
In, described cushion includes at least one of which the first cushion and at least one of which the second cushion being disposed thereon, the cause of the two
Density is different.
Array base palte the most according to claim 1, it is characterised in that described first cushion is the crystalline solid of ITO;Described
Second cushion is the noncrystal of ITO.
Array base palte the most according to claim 1, it is characterised in that described first cushion and the second cushion are
The crystalline solid of ITO;Or,
Described first cushion and the second cushion are the noncrystal of ITO.
Array base palte the most according to claim 1, it is characterised in that described first cushion be ITO crystalline solid or
The noncrystal of ITO, and be formed through plasma on the surface contacted with described second cushion of described first cushion
Levelling blanket after process;
Described second cushion is crystalline solid or the noncrystal of ITO of ITO, and described levelling blanket and described second cushion
Consistency different.
5. according to the array base palte described in claim 1-4 any one, it is characterised in that described metallic reflector include Al,
Any one or the alloy of any at least two composition in Mo, Cu, Ti, Nb.
6. according to the array base palte described in claim 1-4 any one, it is characterised in that described passivation layer include SiNx,
SiOx or SiON.
7. the manufacture method of an array base palte, it is characterised in that comprise the following steps:
Described passivation layer is formed cushion;
Described cushion is formed metallic reflector;
Wherein, described cushion includes at least one of which the first cushion and at least one of which the second cushion being disposed thereon, two
The consistency of person is different.
The manufacture method of array base palte the most according to claim 7, it is characterised in that described first cushion is ITO's
Crystalline solid;Described second cushion is the noncrystal of ITO.
The manufacture method of array base palte the most according to claim 7, it is characterised in that described first cushion and second delays
Rush layer and be the crystalline solid of ITO;Or,
Described first cushion and the second cushion are the noncrystal of ITO.
The manufacture method of array base palte the most according to claim 9, it is characterised in that form described first cushion institute
The film forming power used is less than forming the film forming power that described second cushion is used;Meanwhile, described first cushion is formed
The film forming air pressure used is higher than forming the film forming air pressure that described second cushion is used.
The manufacture method of 11. array base paltes according to claim 7, it is characterised in that described first cushion is ITO's
Crystalline solid or the noncrystal of ITO;Described second cushion is crystalline solid or the noncrystal of ITO of ITO;
Before being formed after described first cushion, and forming described second cushion, also include:
The surface contacted with described second cushion of described first cushion is carried out plasma treatment, smooth to be formed
Layer;Further, described levelling blanket is different from the consistency of described second cushion.
12. 1 kinds of display devices, including array base palte, it is characterised in that described array base palte is claim 1-6 any one
Described array base palte.
Priority Applications (1)
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CN201610618971.1A CN106057822A (en) | 2016-07-29 | 2016-07-29 | Array substrate, manufacturing method thereof and display device |
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CN201610618971.1A CN106057822A (en) | 2016-07-29 | 2016-07-29 | Array substrate, manufacturing method thereof and display device |
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CN201610618971.1A Pending CN106057822A (en) | 2016-07-29 | 2016-07-29 | Array substrate, manufacturing method thereof and display device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022099862A1 (en) * | 2020-11-13 | 2022-05-19 | Tcl华星光电技术有限公司 | Backplane and led panel |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060108587A1 (en) * | 2004-10-26 | 2006-05-25 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
CN1855399A (en) * | 2005-04-28 | 2006-11-01 | 株式会社半导体能源研究所 | Semiconductor and method for manufacturing same |
CN104183602A (en) * | 2013-05-24 | 2014-12-03 | 三星显示有限公司 | Thin-film transistor array substrate, organic light-emitting display device including the same, and method of manufacturing the thin-film transistor array substrate |
-
2016
- 2016-07-29 CN CN201610618971.1A patent/CN106057822A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060108587A1 (en) * | 2004-10-26 | 2006-05-25 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
CN1855399A (en) * | 2005-04-28 | 2006-11-01 | 株式会社半导体能源研究所 | Semiconductor and method for manufacturing same |
CN104183602A (en) * | 2013-05-24 | 2014-12-03 | 三星显示有限公司 | Thin-film transistor array substrate, organic light-emitting display device including the same, and method of manufacturing the thin-film transistor array substrate |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022099862A1 (en) * | 2020-11-13 | 2022-05-19 | Tcl华星光电技术有限公司 | Backplane and led panel |
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