CN104701315B - A kind of thin-film transistor array base-plate and preparation method thereof, display device - Google Patents
A kind of thin-film transistor array base-plate and preparation method thereof, display device Download PDFInfo
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Abstract
The present invention provides a kind of thin-film transistor array base-plate and preparation method thereof, display device, belong to display technology field, it can solve existing thin-film transistor array base-plate and preparation method thereof, and the more production cost of mask plate is high in the preparation of display device, grid is easily corroded, the problem of grid switching Electro-static Driven Comb.Thin-film transistor array base-plate of the invention and preparation method thereof, display device uses same mask plate when the second insulating barrier is prepared with etching barrier layer, saves a mask plate, reduces production cost；Meanwhile, the figure of the second insulating barrier is identical with the figure of the etching barrier layer described in the viewing area, it is ensured that pixel electrode is connected by via with drain electrode；Grid is directly covered in frame region source-drain electrode, when source-drain electrode uses corrosion resistant metal, the risk of the risk of grid corrosion and the Electro-static Driven Comb of grid switching can be reduced.
Description
Technical field
The invention belongs to display technology field, and in particular to a kind of thin-film transistor array base-plate and preparation method thereof, aobvious
Showing device.
Background technology
Oxide thin film transistor has electron mobility high, and characteristic uniformity is good, and technique is relatively easy, can large area
The advantages of, it is considered as the thin film transistor (TFT) Display Technique of a new generation.6 mask plate techniques are generally used at present prepares film crystalline substance
Body pipe array base palte, including prepare on substrate 1 successively：Grid 2, the first insulating barrier 3, active layer 4, etching barrier layer 5, source and drain
Pole 6, the second insulating barrier 7 and pixel electrode 8；In order to improve product reliability and yield, also occur in that the technique of 7 mask plates is (more
One the first insulating barrier mask plate).But it is more all to there is mask plate number in above-mentioned 6 mask plates or 7 mask plate techniques, production
Relatively costly problem.
The thin-film transistor array base-plate prepared by above-mentioned 6 mask plate technique is included viewing area and surrounds viewing area
Frame region in, wherein, frame region is used to set various peripheral signal lines, and is formed and control chip or flexible printing electricity
The holding wire bonding pad of road plate connection；
Further, since the peripheral wiring of frame region is more, same holding wire cannot be arranged in single metal level, past
Toward needs signal transmission is carried out by other metal levels；Now, different metal layer needs to be attached by via, i.e., with the 3rd
Metal is planted to be transferred (bridge joint).
As shown in figure 1, grid 2 conducts because a variety of causes generation is difficult when grid layer is arranged, it is necessary to borrow source-drain electrode 6
The signal of grid 2, is transferred using pixel electrode metal (tin indium oxide), i.e., pixel electrode 8 is connected by via with grid 2,
But there are following two shortcomings in this substitute mode：
1. this substitute mode increased the risk of Electro-static Driven Comb；
2. because tin indium oxide obtains its low density using plasma deposition, easily passed through by moisture, gate metal is produced
Raw corrosion (usual gate metal is prepared using the aluminium and aluminium-containing alloy being easily corroded under the conditions of hot and humid).
As shown in Fig. 2 in the holding wire bonding pad (6 mask plate technique) of frame region, preparing the etching of the second insulating barrier 7
The middle method using continuous etching, while the first insulating barrier 3 is also cut through, forms via, and pixel electrode 8 passes through the via and grid
The connection of pole 2 forms switching；This switching equally exists the risk of corrosion gate metal.
Even if in addition, the pixel electrode 8 in Fig. 2 replaces with more corrosion resistant source-drain electrode metal, although grid can be reduced
The risk that metal corrodes, but the fanout area of the control chip being connected with holding wire bonding pad will not generally use individual layer source
The wire laying mode of drain metal, so, relates to the switching of grid 2 and source-drain electrode metal, can equally there is the risk of corrosion；
Flexible print circuit board generally uses grid 2 and source-drain electrode metal bi with the connecting line of the input of control chip
Wiring, relates equally to switching problem, the risk that can equally there is the corrosion of grid 2.
Although by increase the first insulating barrier mask plate can solve the problems, such as it is above-mentioned, as shown in figure 3, in the first insulating barrier
3 form via by patterning processes, and source-drain electrode metal is directly transferred with grid 2, can reduce the risk of Electro-static Driven Comb.
In holding wire bonding pad (7 mask plate technique), as shown in figure 4, the first insulating barrier 3 has via, if source-drain electrode
Metal uses corrosion resistant metal, source-drain electrode metal to cover gate metal and can reduce the risk that gate metal corrodes.
However, due to increased gate insulation layer mask plate so that many mask plate techniques of whole production technology, increase
Production cost.
The content of the invention
Thin-film transistor array base-plate present invention aim to address prior art and preparation method thereof, display device
The more production cost of mask plate is high in preparation, grid is easily corroded, the problem of grid switching Electro-static Driven Comb.
The technical scheme that solution present invention problem is used is a kind of thin-film transistor array base-plate, including：Display
Region and the frame region of the encirclement viewing area, wherein, the viewing area includes：
Substrate and the grid sequentially formed on substrate, the first insulating barrier, active layer 4, etching barrier layer, source-drain electrode,
Two insulating barriers and pixel electrode, the figure of the figure of the second insulating barrier described in the viewing area and the etching barrier layer
It is identical.
Preferably, the frame region includes the etching barrier layer being disposed adjacent and the first insulating barrier, described
Figure of the figure of one insulating barrier with the etching barrier layer in the frame region is identical.
Preferably, the source-drain electrode described in the frame region is by through the etching barrier layer and first insulation
The via of layer is connected with the grid.
Preferably, the frame region includes holding wire bonding pad, and pixel electrode described in the holding wire bonding pad leads to
The via for crossing second insulating barrier is connected with the source-drain electrode.
Another object of the present invention also includes providing a kind of preparation method of above-mentioned thin-film transistor array base-plate, bag
The frame region using following steps in the viewing area of thin-film transistor array base-plate and the encirclement viewing area is included to be formed
Each functional layer：
Grid is formed on substrate by patterning processes；
The depositing first insulator layer on the substrate for forming grid；
By patterning processes active layer is formed on the substrate of depositing first insulator layer；
By patterning processes etching barrier layer is formed on the substrate for forming active layer；
By patterning processes source-drain electrode is formed on the substrate for forming etching barrier layer；
By patterning processes the second insulating barrier is formed on the substrate for forming source-drain electrode；
Wherein, the etching barrier layer and second insulating barrier use same mask plate.
It is preferably, described that by patterning processes, formation etching barrier layer includes on the substrate for forming active layer：Described
Frame region continuously etches the etching barrier layer and first insulating barrier and is formed through the etching barrier layer and described the
The step of via of one insulating barrier.
It is preferably, described that by patterning processes, formation source-drain electrode includes on the substrate for forming etching barrier layer：Described
The step of source-drain electrode of the connection grid is formed in via.
Preferably, also include：By patterning processes pixel electrode is formed on the substrate for forming the second insulating barrier.
Preferably, the frame region includes holding wire bonding pad, the pixel electrode described in the holding wire bonding pad
It is connected with the source-drain electrode by the via of second insulating barrier.
Another object of the present invention also includes providing a kind of display device, including above-mentioned thin film transistor (TFT) array base
Plate.
Thin-film transistor array base-plate of the invention and preparation method thereof, display device is preparing the second insulating barrier and is carving
Same mask plate is used during erosion barrier layer, a mask plate is saved, production cost is reduced；Meanwhile, in the viewing area
The figure of the second insulating barrier is identical with the figure of the etching barrier layer described in domain, it is ensured that pixel electrode is by via and leakage
Pole connects；Grid is directly covered in frame region source-drain electrode, when source-drain electrode uses corrosion resistant metal, grid corrosion can be reduced
Risk and grid switching Electro-static Driven Comb risk.
Brief description of the drawings
Fig. 1 is the frame region signal that 6 (7) mask plate techniques prepare thin-film transistor array base-plate in the prior art
The schematic diagram of exchanging structure.
Fig. 2 is the holding wire bonding pad grid letter that 6 mask plate techniques prepare thin-film transistor array base-plate in the prior art
The schematic diagram of number exchanging structure.
Fig. 3 is the frame region signal turn that 7 mask plate techniques prepare thin-film transistor array base-plate in the prior art
The schematic diagram of binding structure.
Fig. 4 is the holding wire bonding pad grid letter that 7 mask plate techniques prepare thin-film transistor array base-plate in the prior art
The schematic diagram of number exchanging structure.
Fig. 5 is that 5 mask plate techniques prepare the structural representation of thin-film transistor array base-plate in the embodiment of the present invention 1.
Fig. 6 be the embodiment of the present invention 1 in 5 mask plate techniques prepare thin-film transistor array base-plate frame region structure
Schematic diagram.
Fig. 7 be the embodiment of the present invention 1 in 5 mask plate techniques prepare thin-film transistor array base-plate holding wire bonding pad knot
Structure schematic diagram.
Fig. 8 be the embodiment of the present invention 2 in 5 mask plate techniques prepare thin-film transistor array base-plate grid schematic diagram.
Fig. 9 is that 5 mask plate techniques prepare the first insulating barrier of thin-film transistor array base-plate and show in the embodiment of the present invention 2
It is intended to.
Figure 10 be the embodiment of the present invention 2 in 5 mask plate techniques prepare thin-film transistor array base-plate active layer signal
Figure.
Figure 11 is the etching barrier layer that 5 mask plate techniques prepare thin-film transistor array base-plate in the embodiment of the present invention 2
Schematic diagram.
Figure 12 be the embodiment of the present invention 2 in 5 mask plate techniques prepare thin-film transistor array base-plate source-drain electrode signal
Figure.
Figure 13 is the etching barrier layer that 5 mask plate techniques prepare thin-film transistor array base-plate in the embodiment of the present invention 2
Schematic diagram.
Figure 14 is that 5 mask plate techniques prepare the pixel electrode of thin-film transistor array base-plate and show in the embodiment of the present invention 2
It is intended to.
Wherein：
1. substrate；2. grid；3. the first insulating barrier (gate insulator)；4. active layer；5. etching barrier layer；6. source and drain
Pole；7. the second insulating barrier；8. pixel electrode.
Specific embodiment
To make those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and specific embodiment party
Formula is described in further detail to the present invention.
Embodiment 1
As shown in figure 5, the present embodiment provides a kind of thin-film transistor array base-plate, including：Viewing area and encirclement are described
The frame region of viewing area, wherein, the viewing area includes：
Substrate 1 and the grid 2 for sequentially forming on substrate 1, the first insulating barrier 3, active layer 4, etching barrier layer 5, source and drain
Pole 6, the second insulating barrier 7 and pixel electrode 8, the figure of the second insulating barrier 7 described in the viewing area and the etching resistance
The figure of barrier 5 is identical.
The present embodiment uses same mask plate when the second insulating barrier 7 is prepared with etching barrier layer 5, saves one and covers
Lamina membranacea, reduces production cost；Meanwhile, the figure of the second insulating barrier 7 described in the viewing area and the etch stopper
The figure of layer 5 is identical, it is ensured that pixel electrode 8 is connected by via with drain electrode.
As shown in fig. 6-7, specifically, the frame region includes the etching barrier layer 5 and first being disposed adjacent
Insulating barrier 3, the figure of the figure of first insulating barrier 3 with the etching barrier layer 5 in the frame region is identical.So
First insulating barrier 3 and etching barrier layer 5 can be prepared by same mask plate.A mask plate can be saved (relative to be covered with 7
Lamina membranacea technique).
As shown in fig. 6, specifically, the source-drain electrode 6 described in the frame region is by through the He of the etching barrier layer 5
The via of first insulating barrier 3 is connected with the grid 2.
So source-drain electrode 6 directly covers grid 2, when source-drain electrode 6 is using corrosion resistant metal, can reduce grid 2 and corrode
Risk and grid 2 switching Electro-static Driven Comb risk.
As shown in fig. 7, specifically, the frame region includes holding wire bonding pad, described in the holding wire bonding pad
Pixel electrode 8 is connected by the via of second insulating barrier 7 with the source-drain electrode 6.
Because the second insulating barrier 7 and etching barrier layer 5 are prepared using same mask plate, can be in the He of the second insulating barrier 7
The via of same shape is formed in etching barrier layer 5, pixel electrode 8 is connected by the via with source-drain electrode metal.
Embodiment 2
The present embodiment provides a kind of preparation method of above-mentioned thin-film transistor array base-plate, including using following steps thin
The viewing area of film transistor array base palte and the frame region of the encirclement viewing area form each functional layer：Specifically,
As shown in figure 8, forming grid 2 on substrate 1 by patterning processes, gate mask plate can be used in the step；
As shown in figure 9, formed grid 2 substrate 1 on depositing first insulator layer 3 (gate insulator)；Make in the step
With the first insulating barrier mask plate (being now referred to as 6 mask plate techniques), it is also possible to do not use this step to be then referred to as 5 mask plate techniques.
As shown in Figure 10, active layer 4 is formed on the substrate 1 of depositing first insulator layer 3 by patterning processes, in the step
Use active layer mask plate；
As shown in figure 11, etching barrier layer 5 is formed on the substrate 1 for forming active layer 4 by patterning processes, in the step
Use etching barrier layer mask plate；
As shown in figure 12, source-drain electrode 6 is formed on the substrate 1 for forming etching barrier layer 5 by patterning processes, in the step
Use source-drain electrode mask plate；
As shown in figure 13, the second insulating barrier 7 is formed on the substrate 1 for forming source-drain electrode 6 by patterning processes；
Wherein, the etching barrier layer 5 and second insulating barrier 7 use same mask plate.
A mask plate can be so saved, the manufacturing cost of thin-film transistor array base-plate is reduced.
It is specifically, described that by patterning processes, formation etching barrier layer 5 includes on the substrate 1 for forming active layer 4：Institute
State frame region and continuously etch the etching barrier layer 5 and first insulating barrier 3 formation through the etching barrier layer 5 and institute
The step of stating the via of the first insulating barrier 3.
That is, after photoresist developing in the patterning processes of etching barrier layer 5, etching barrier layer 5 is first etched, then,
Continue to etch the first insulating barrier 3.
It is preferably, described that by patterning processes, formation source-drain electrode 6 includes on the substrate 1 for forming etching barrier layer 5：Institute
The step of stating source-drain electrode 6 of the formation connection grid 2 in via.
So source-drain electrode 6 (corrosion resistant metal) can be just covered on grid 2 by the via, be prevented from when grid 2
When being made using perishable metal, moisture corrodes gate metal by source-drain electrode 6.
As shown in figure 14, it is preferred that also include：By patterning processes picture is formed on the substrate 1 for forming the second insulating barrier 7
Plain electrode 8.
Accordingly even when the low density of pixel electrode 8, moisture is stopped by source-drain electrode metal can not be passed through, it is impossible to grid
Metal causes corrosion.
Preferably, the frame region includes holding wire bonding pad, the pixel electrode 8 described in the holding wire bonding pad
It is connected with the source-drain electrode 6 by the via of second insulating barrier 7.
Optionally, can continue to prepare other necessary functions layer of thin-film transistor array base-plate, no longer go to live in the household of one's in-laws on getting married one by one herein
State.
The preparation method of the thin-film transistor array base-plate of the present embodiment, reduces a mask plate, reduces film brilliant
The production cost of body pipe array base palte；Meanwhile, the figure of the second insulating barrier 7 described in the viewing area and the etching hinder
The figure of barrier 5 is identical, it is ensured that pixel electrode 8 is connected by via with drain electrode；In the direct cover grid of frame region source-drain electrode 6
Pole 2, when source-drain electrode 6 is using corrosion resistant metal, can reduce the risk of the corrosion of grid 2 and the Electro-static Driven Comb of the switching of grid 2
Risk.
Embodiment 3
The present embodiment provides a kind of display device, and the display device includes above-mentioned thin-film transistor array base-plate.
Thin-film transistor array base-plate of the invention and preparation method thereof, display device is preparing the second insulating barrier 7 and is carving
Same mask plate is used during erosion barrier layer 5, a mask plate is saved, production cost is reduced；Meanwhile, in the viewing area
The figure of the second insulating barrier 7 is identical with the figure of the etching barrier layer 5 described in domain, it is ensured that pixel electrode 8 passes through via
It is connected with drain electrode；Grid 2 is directly covered in frame region source-drain electrode 6, when source-drain electrode 6 is using corrosion resistant metal, can be reduced
The risk of the risk of the corrosion of grid 2 and the Electro-static Driven Comb of the switching of grid 2.
It is understood that the embodiment of above principle being intended to be merely illustrative of the present and the exemplary implementation for using
Mode, but the invention is not limited in this.The display device can be：Mobile phone, panel computer, television set, display, notes
Any product or part with display function such as this computer, DPF, navigator.The implementation of the display device may refer to
Above-described embodiment, repeats part and repeats no more.For those skilled in the art, essence of the invention is not being departed from
In the case of god and essence, various changes and modifications can be made therein, and these variations and modifications are also considered as protection scope of the present invention.
Claims (7)
1. a kind of thin-film transistor array base-plate, including：Viewing area and the frame region of the encirclement viewing area, wherein,
The viewing area includes：
Substrate and the grid sequentially formed on substrate, the first insulating barrier, active layer, etching barrier layer, source-drain electrode, the second insulation
Layer and pixel electrode, it is characterised in that the figure of the second insulating barrier described in the viewing area and the etching barrier layer
Figure it is identical；
The frame region includes the etching barrier layer being disposed adjacent and the first insulating barrier, the figure of first insulating barrier
Figure of the shape with the etching barrier layer in the frame region is identical；
The source-drain electrode described in the frame region by the via through the etching barrier layer and first insulating barrier with
The grid connection.
2. thin-film transistor array base-plate as claimed in claim 1, it is characterised in that the frame region includes that holding wire connects
Area is met, pixel electrode described in the holding wire bonding pad is connected by the via of second insulating barrier with the source-drain electrode.
3. a kind of preparation method of thin-film transistor array base-plate as described in claim any one of 1-2, it is characterised in that bag
The frame region using following steps in the viewing area of thin-film transistor array base-plate and the encirclement viewing area is included to be formed
Each functional layer：
Grid is formed on substrate by patterning processes；
The depositing first insulator layer on the substrate for forming grid；
By patterning processes active layer is formed on the substrate of depositing first insulator layer；
By patterning processes etching barrier layer is formed on the substrate for forming active layer；
By patterning processes source-drain electrode is formed on the substrate for forming etching barrier layer；
By patterning processes the second insulating barrier is formed on the substrate for forming source-drain electrode；
Wherein, the etching barrier layer and second insulating barrier use same mask plate；
It is described that by patterning processes, formation etching barrier layer includes on the substrate for forming active layer：It is continuous in the frame region
Etch the etching barrier layer and first insulating barrier forms the mistake for running through the etching barrier layer and first insulating barrier
The step of hole.
4. the preparation method of thin-film transistor array base-plate as claimed in claim 3, it is characterised in that described by composition work
Skill forms source-drain electrode on the substrate for forming etching barrier layer to be included：The source-drain electrode of the connection grid is formed in the via
The step of.
5. the preparation method of thin-film transistor array base-plate as claimed in claim 3, it is characterised in that also include：By structure
Figure technique forms pixel electrode on the substrate for forming the second insulating barrier.
6. the preparation method of thin-film transistor array base-plate as claimed in claim 5, it is characterised in that the frame region bag
Include holding wire bonding pad, the pixel electrode described in the holding wire bonding pad by the via of second insulating barrier with it is described
Source-drain electrode is connected.
7. a kind of display device, it is characterised in that including the thin film transistor (TFT) array base as described in claim any one of 1-2
Plate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106773258A (en) * | 2017-01-03 | 2017-05-31 | 京东方科技集团股份有限公司 | Display panel, display device |
| CN107591413B (en) * | 2017-08-09 | 2020-02-07 | 武汉华星光电半导体显示技术有限公司 | Preparation method of TFT substrate, TFT substrate and OLED display panel |
| CN110349978A (en) * | 2019-07-25 | 2019-10-18 | 京东方科技集团股份有限公司 | A kind of array substrate and preparation method thereof, display panel and display device |
| CN110473835B (en) * | 2019-08-30 | 2022-08-23 | 上海中航光电子有限公司 | Display panel, preparation method thereof and display device |
| CN111048527B (en) * | 2019-12-18 | 2022-04-15 | 京东方科技集团股份有限公司 | Display back plate, manufacturing method thereof and display device |
| CN111211137B (en) * | 2020-01-13 | 2022-12-27 | 京东方科技集团股份有限公司 | Display panel and display device |
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| CN103915444A (en) * | 2013-04-10 | 2014-07-09 | 上海天马微电子有限公司 | Array substrate, preparation method thereof and liquid crystal display panel |
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