CN106057657A - Multiple imaging method - Google Patents
Multiple imaging method Download PDFInfo
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- CN106057657A CN106057657A CN201610585518.5A CN201610585518A CN106057657A CN 106057657 A CN106057657 A CN 106057657A CN 201610585518 A CN201610585518 A CN 201610585518A CN 106057657 A CN106057657 A CN 106057657A
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- China
- Prior art keywords
- polysilicon
- fin structure
- layer
- silicon
- side wall
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
The present invention provides a multiple imaging method. The method comprises: the first step: forming a hard mask layer and a polysilicon layer on a substrate in order; performing imaging of the polysilicon layer to form a polysilicon fin structure; performing surface processing of the top surface and the surface of a first side wall of the polysilicon fin structure while without the surface processing of the surface of the second side wall of the olysilicon fin structure; forming side wall material layers, and forming side wall material layers with different thicknesses on two side walls of the polysilicon; etching the side wall material layers so as to form the first side wall portion with the first thickness on the first side wall of the polysilicon fin structure, forming the second side wall portion with the second thickness different from the first thickness on the second side wall of the polysilicon fin structure; and removing the polysilicon fin structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of multiple patterning methods.
Background technology
Side wall transfer (Spacer transfer) is a kind of method of Dual graphing (double patterning), uses
To overcome the limit of photoetching.By the width of the side wall that control is formed, obtain homogeneous hard mask.
United States Patent (USP) US7187042B2 proposes to be processed by the surface of fin structure side, can be formed in fin structure both sides
The gate dielectric layer of different-thickness.This dissymmetrical structure is used for rear grid (back gate) structure.
But, the processing procedure of prior art is relatively complicated, can't obtain difference by a Dual graphing
The hard mask of side wall of width.
Wish to improve the hard mask of side wall that a kind of technical scheme obtains different in width by Dual graphing.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one can be multiple
Graphic method, the hard mask of side wall obtaining different in width by Dual graphing.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of multiple patterning methods, including:
First step: sequentially form hard mask layer and polysilicon layer on substrate；
Second step: be patterned polysilicon layer to form polysilicon fin structure；
Third step: top surface and the first side wall surface to polysilicon fin structure carry out surface process, to polysilicon
Second sidewall surfaces of fin structure does not carry out surface process；
4th step: form spacer material layer, form the spacer material layer of different-thickness on two sidewalls of polysilicon；
5th step: the offside walling bed of material performs etching, thus on the first side wall of polysilicon fin structure, form first
First sidewall section of thickness, and on the second sidewall of polysilicon fin structure, form second thickness different from the first thickness
The second sidewall section；
6th step: remove polysilicon fin structure.
Preferably, described surface processes is that nitrogen gas plasma surface processes.
Preferably, the process of described surface is the ion implanting of silicon or argon.
Preferably, the material of hard mask layer is silicon nitride, and the material of spacer material layer is silicon oxide.
Preferably, the material of hard mask layer is silicon oxide, and the material of spacer material layer is silicon nitride.
In order to realize above-mentioned technical purpose, according to the present invention, additionally provide a kind of multiple patterning methods, including:
First step: sequentially form hard mask layer and polysilicon layer on substrate；
Second step: be patterned polysilicon layer to form polysilicon fin structure；
Third step: top surface and the first side wall surface to polysilicon fin structure carry out first surface process, to many
Second sidewall surfaces of crystal silicon fin structure carries out second surface process.
4th step: form spacer material layer；Owing to the process of nitrogen gas plasma surface can make the spacer material of formation
Layer is thinning, and the spacer material layer that the introducing of silicon or argon can make formation is thickening, thus can on the two of polysilicon sidewall shape
Become the spacer material layer of different-thickness；
5th step: the offside walling bed of material performs etching, thus on the first side wall of polysilicon fin structure, form first
First sidewall section of thickness, and on the second sidewall of polysilicon fin structure, form second thickness different from the first thickness
The second sidewall section；
6th step: remove polysilicon fin structure.
Preferably, described first surface processes is that nitrogen gas plasma surface processes.
Preferably, the process of described second surface is the ion implanting of silicon or argon.
Preferably, the material of hard mask layer is silicon nitride, and the material of spacer material layer is silicon oxide.
Preferably, the material of hard mask layer is silicon oxide, and the material of spacer material layer is silicon nitride.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding
And its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the first step of multiple patterning methods according to the preferred embodiment of the invention.
Fig. 2 schematically shows the second step of multiple patterning methods according to the preferred embodiment of the invention.
Fig. 3 schematically shows the third step of multiple patterning methods according to the preferred embodiment of the invention.
Fig. 4 schematically shows the 4th step of multiple patterning methods according to the preferred embodiment of the invention.
Fig. 5 schematically shows the 5th step of multiple patterning methods according to the preferred embodiment of the invention.
Fig. 6 schematically shows the 6th step of multiple patterning methods according to the preferred embodiment of the invention.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings in the present invention
Appearance is described in detail.
<first embodiment>
Fig. 1 to Fig. 6 schematically shows each step of multiple patterning methods according to the preferred embodiment of the invention.
Specifically, as shown in Figures 1 to 6, multiple patterning methods includes according to the preferred embodiment of the invention:
First step: sequentially form hard mask layer 200 and polysilicon layer 300 on the substrate 100；
Second step: be patterned to form polysilicon fin structure 400 to polysilicon layer 300；
Third step: top surface and the first side wall surface to polysilicon fin structure 400 carry out surface process；To polycrystalline
Second sidewall surfaces of silicon fin structure 400 does not carry out surface process.
Such as, described surface processes is that nitrogen gas plasma surface processes.Or, such as, described surface process be silicon or
The ion implanting of argon.
4th step: form spacer material layer 500；Owing to the process of nitrogen gas plasma surface can make the side wall material of formation
The bed of material is thinning, and the spacer material layer that the introducing of silicon or argon can make formation is thickening, so can be on the two of polysilicon sidewall
Form the spacer material layer of different-thickness；
Preferably, the material of hard mask layer 200 is silicon nitride, and the material of spacer material layer 500 is silicon oxide.Or,
Preferably, the material of hard mask layer 200 is silicon oxide, and the material of spacer material layer 500 is silicon nitride.
5th step: the offside walling bed of material 500 performs etching, thus shape on the first side wall of polysilicon fin structure 400
Become the first sidewall section 600 of the first thickness, and formed with the first thickness not on the second sidewall of polysilicon fin structure 400
Second sidewall section 700 of the second same thickness；
6th step: remove polysilicon fin structure 400.
The present invention, with polysilicon as core, carries out surface process, thus changes the deposition of thick of spacer material layer in its side
Degree, obtains the side wall of different in width by Dual graphing.
<the second embodiment>
Impurity can be introduced, it is also possible to introduce the impurity of not same-action in the both sides of polysilicon to increase not with polysilicon side
Symmetry.Thus presently describe the impurity introducing not same-action in the both sides of polysilicon to increase being embodied as of unsymmetry
Example.
Multiple patterning methods according to second preferred embodiment of the invention includes:
First step: sequentially form hard mask layer 200 and polysilicon layer 300 on the substrate 100；
Second step: be patterned to form polysilicon fin structure 400 to polysilicon layer 300；
Third step: top surface and the first side wall surface to polysilicon fin structure 400 carry out first surface process, right
Second sidewall surfaces of polysilicon fin structure 400 carries out second surface process.
Such as, described first surface processes is that nitrogen gas plasma surface processes.Such as, described second surface processes is silicon
Or the ion implanting of argon.
4th step: form spacer material layer 500；Owing to the process of nitrogen gas plasma surface can make the side wall material of formation
The bed of material is thinning, and the spacer material layer that the introducing of silicon or argon can make formation is thickening, so can be on the two of polysilicon sidewall
Form the spacer material layer of different-thickness；
Preferably, the material of hard mask layer 200 is silicon nitride, and the material of spacer material layer 500 is silicon oxide.Or,
Preferably, the material of hard mask layer 200 is silicon oxide, and the material of spacer material layer 500 is silicon nitride.
5th step: the offside walling bed of material 500 performs etching, thus shape on the first side wall of polysilicon fin structure 400
Become the first sidewall section 600 of the first thickness, and formed with the first thickness not on the second sidewall of polysilicon fin structure 400
Second sidewall section 700 of the second same thickness；
6th step: remove polysilicon fin structure 400.
The present invention, with polysilicon as core, introduces the impurity of not same-action to increase unsymmetry in the both sides of polysilicon,
Thus change the deposit thickness of spacer material layer, the side wall of different in width is obtained by Dual graphing.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ", " the
Two ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing each
Logical relation between assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
Technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
In.
Claims (10)
1. a multiple patterning methods, it is characterised in that including:
First step: sequentially form hard mask layer and polysilicon layer on substrate；
Second step: be patterned polysilicon layer to form polysilicon fin structure；
Third step: top surface and the first side wall surface to polysilicon fin structure carry out surface process, ties polycrystalline silicon fin
Second sidewall surfaces of structure does not carry out surface process；
4th step: form spacer material layer, form the spacer material layer of different-thickness on two sidewalls of polysilicon；
5th step: the offside walling bed of material performs etching, thus on the first side wall of polysilicon fin structure, form the first thickness
The first sidewall section, and on the second sidewall of polysilicon fin structure, form the of second thickness different from the first thickness
Two sidewall section；
6th step: remove polysilicon fin structure.
Multiple patterning methods the most according to claim 1, it is characterised in that it is nitrogen gas plasma that described surface processes
Surface processes.
Multiple patterning methods the most according to claim 1, it is characterised in that the process of described surface is the ion of silicon or argon
Inject.
Multiple patterning methods the most according to claim 1 and 2, it is characterised in that the material of hard mask layer is nitridation
Silicon, the material of spacer material layer is silicon oxide.
Multiple patterning methods the most according to claim 1 and 2, it is characterised in that the material of hard mask layer is oxidation
Silicon, the material of spacer material layer is silicon nitride.
6. a multiple patterning methods, it is characterised in that including:
First step: sequentially form hard mask layer and polysilicon layer on substrate；
Second step: be patterned polysilicon layer to form polysilicon fin structure；
Third step: top surface and the first side wall surface to polysilicon fin structure carry out first surface process, to polysilicon
Second sidewall surfaces of fin structure carries out second surface process.
4th step: form spacer material layer；The spacer material layer of formation can be made to become owing to nitrogen gas plasma surface processes
Thin, and the spacer material layer that the introducing of silicon or argon can make formation is thickening, so can be formed not on the two of polysilicon sidewall
The spacer material layer of stack pile；
5th step: the offside walling bed of material performs etching, thus on the first side wall of polysilicon fin structure, form the first thickness
The first sidewall section, and on the second sidewall of polysilicon fin structure, form the of second thickness different from the first thickness
Two sidewall section；
6th step: remove polysilicon fin structure.
Multiple patterning methods the most according to claim 6, it is characterised in that described first surface processes be nitrogen etc. from
Daughter surface processes.
8. according to the multiple patterning methods described in claim 6 or 7, it is characterised in that described second surface process be silicon or
The ion implanting of argon.
9. according to the multiple patterning methods described in claim 6 or 7, it is characterised in that the material of hard mask layer is nitridation
Silicon, the material of spacer material layer is silicon oxide.
10. according to the multiple patterning methods described in claim 6 or 7, it is characterised in that the material of hard mask layer is oxidation
Silicon, the material of spacer material layer is silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610585518.5A CN106057657A (en) | 2016-07-22 | 2016-07-22 | Multiple imaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610585518.5A CN106057657A (en) | 2016-07-22 | 2016-07-22 | Multiple imaging method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216165A (en) * | 2017-07-06 | 2019-01-15 | 中芯国际集成电路制造（天津）有限公司 | The manufacturing method of multiple graphics and semiconductor devices |
| CN109309005A (en) * | 2017-07-27 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112563200A (en) * | 2019-09-26 | 2021-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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| CN1691294A (en) * | 2004-04-28 | 2005-11-02 | 国际商业机器公司 | Backgated finfet having diferent oxide thicknesses |
| CN102420574A (en) * | 2011-11-22 | 2012-04-18 | 上海华力微电子有限公司 | Method for improving frequency characteristic of common-source operational amplifier |
| US20120235247A1 (en) * | 2011-03-17 | 2012-09-20 | International Business Machines Corporation | Fin field effect transistor with variable channel thickness for threshold voltage tuning |
| CN103578930A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Forming method for multiple graphical mask layer and semiconductor structure |
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2016
- 2016-07-22 CN CN201610585518.5A patent/CN106057657A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691294A (en) * | 2004-04-28 | 2005-11-02 | 国际商业机器公司 | Backgated finfet having diferent oxide thicknesses |
| US20120235247A1 (en) * | 2011-03-17 | 2012-09-20 | International Business Machines Corporation | Fin field effect transistor with variable channel thickness for threshold voltage tuning |
| CN102420574A (en) * | 2011-11-22 | 2012-04-18 | 上海华力微电子有限公司 | Method for improving frequency characteristic of common-source operational amplifier |
| CN103578930A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Forming method for multiple graphical mask layer and semiconductor structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216165A (en) * | 2017-07-06 | 2019-01-15 | 中芯国际集成电路制造（天津）有限公司 | The manufacturing method of multiple graphics and semiconductor devices |
| CN109216165B (en) * | 2017-07-06 | 2020-11-03 | 中芯国际集成电路制造（天津）有限公司 | Method for manufacturing multiple patterns and semiconductor device |
| CN109309005A (en) * | 2017-07-27 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109309005B (en) * | 2017-07-27 | 2022-03-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112563200A (en) * | 2019-09-26 | 2021-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112563200B (en) * | 2019-09-26 | 2023-12-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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Application publication date: 20161026 |