CN106055382B - A kind of emulator for supporting NVM power-down protection to test - Google Patents
A kind of emulator for supporting NVM power-down protection to test Download PDFInfo
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- CN106055382B CN106055382B CN201610352699.7A CN201610352699A CN106055382B CN 106055382 B CN106055382 B CN 106055382B CN 201610352699 A CN201610352699 A CN 201610352699A CN 106055382 B CN106055382 B CN 106055382B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
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Abstract
The invention discloses a kind of emulators for supporting NVM power-down protection to test, and are related to chip emulation technical field.Emulator includes emulator management module and emulator hardware, and emulator hardware includes debugging/operation control module, interface up/down electro-detection module, resets control module and chip emulation module.Emulator management module controls emulator hardware work and after interface re-powers, executes power down protection program if electric emulator hardware under interface during execution NVM is erasable, occurs for program is in reset state immediately in operational mode and complete the erasable operation of NVM；Emulator management module controls emulator hardware and works in debugging mode, the debugging of program when supporting interface powers on or is lower electric.Emulator of the invention is able to satisfy the requirement of NVM power-down protection test, can also carry out program debugging in the power supply of no card reader, facilitate exploitation and test of the user to types of applications program, improve program development efficiency.
Description
Technical field
The present invention relates to a kind of chip emulator, in particular to a kind of emulator for supporting NVM power-down protection to test.
Background technique
Current existing emulator is realized with FPGA emulation chip function.In this kind of chip emulator, when imitative
When true device powers on, the function that chip emulation is completed in configuration will be carried out to FPGA, this configuration process generally requires the used time in the second
Grade or more.It is tested on emulator in order to simulate financial IC card power-down protection, it is necessary to meet and held after electricity under interface VCC
Capable program stops immediately, especially to keep the read-write operation state currently to NVM, when next interface VCC is powered on into
Row NVM data recovery operation.In view of electricity is longer to setup time is re-powered under FPGA on emulator, it is unable to satisfy interface and falls
The time requirement of Electricity Functional test.
In order to meet the needs of financial IC card emulator power-down protection test, the present invention is using JTAG debugging standard letter
Number and nRST signal, realize emulator IDE software and emulator hardware data interaction.When electric under emulator interface, emulation
Device is in reset state, does not execute program；When carrying out normal procedure debugging, and the state independent of interface power-on and power-off.When
When emulator is communicated with contact (or non-contact) card reader, the interface VCC signal on emulator is provided by card reader.
When card reader is powered on (prologue) operation, emulator detects that interface VCC signal is effective, and emulator generates hard
Operation is resetted, realizes the reset function in interface protocol；When electricity (closing field) operation under card reader, emulator detects interface
VCC is invalid, on the one hand can satisfy power failure test demand, and emulator will always be in reset state, until interface VCC is powered on,
Emulator executes program after carrying out hard reset.On the other hand it can satisfy debugging demand, carry out power supply switching inside emulator, produce
Stiff reset operation, supports down-stream debugging.
Summary of the invention
Technical problem solved by the invention is how to design a kind of emulator for supporting NVM power-down protection to test.
Emulator of the invention includes emulator management module and emulator hardware.Emulator management module, with emulator
Hardware is connected, and realizes the function of emulator program downloading, operation and debugging, is sent out by JTAG_nRST signal to emulator hardware
Mode setting command, program downloading and program debugging order are sent, emulator hardware is soft/hard reset order.
Emulator hardware, including debugging/operation control module, interface up/down electro-detection module, reset control module and core
Piece emulation module.Debugging/operation control module is connected with emulator management module, realizes connecing for emulator management module order
It receives and responds；Debugging/operation control module is connected to chip emulation module, transmits emulator management module by JTAG signal
Debug command and response；Debugging/operation control module is connected to reset control module, exports RUN_EN signal and gives reset control mould
Block；Interface up/down electro-detection module is connected to reset control module, realizes the electric control of interface up/down, exports VCC_SEL signal
Give reset control module；Interface up/down electro-detection module is connected with interface VCC signal, detects the state of interface VCC power supply；It is multiple
Position control module, is connected to chip emulation module, on the RUN_EN signal and interface exported according to debugging/operation control module/
The VCC_SEL signal of lower electro-detection module generates reset nRST signal and gives chip emulation module, controls the operation shape of emulation chip
State；Chip emulation module is connect with control module is resetted, and realizes chip functions emulation, is controlled wherein resetting nRST signal with NVM
Module is connected.
Emulator is by JTAG_nRST signal, and when emulator management module and emulator hardware are attached, control is imitative
True device hardware immediately enters debugging mode.
After emulator completes program downloading, emulator hardware is in operational mode.NVM can be executed in the operating mode to fall
Electric protection functional test program.
In the operating mode, when emulator hardware detects that interface VCC is invalid, emulator hardware is constantly in multiple emulator
Position state；After detecting that interface VCC is powered on, emulator hardware carries out hard reset and runs program from initial address is resetted.
Emulator executes interface communication program under debugging mode, when program is parked in breakpoint, if detect interface VCC without
Effect, emulator hardware automatically switch to non-reset state, and user is supported to continue the single-step debug to program.
The method that emulator realizes operation debugging mode switching:
After emulator management module downloads NVM program, emulator is in operational mode.First by emulator management module
Control emulator hardware enters debugging mode, and emulator management module downloads program to emulator hardware, emulator hardware is arranged
For operating status, power down program test is carried out.
When emulator management module debugs NVM program, emulator is in debugging mode.First by emulator management module
Control emulator hardware enters debugging mode, and emulator management module downloads program to emulator hardware, emulator hardware is arranged
For debugging mode, the debugging of program is carried out into Debugging interface.
Detailed description of the invention
Fig. 1 is the emulator structure chart for supporting the test of NVM power-down protection.
Fig. 2 is to reset control waveform diagram.
Fig. 3 is program downloading flow diagram.
Fig. 4 is program debugging flow diagram.
Specific embodiment
Emulator of the present invention is described in detail with reference to the accompanying drawing.
As shown in Figure 1, providing emulator structure chart.Emulator 1 includes emulator management module 2 and emulator hardware 3.It is imitative
True device management module 2, is connected with emulator hardware 3, realizes the function of emulator program downloading and operation, program debugging, passes through
JTAG_nRST signal sends debugging mode and operational mode order, program downloading and program debugging order to emulator hardware 3,
3 hard reset of emulator hardware and warm reset order.
Emulator hardware 3, including debugging/operation control module 4, interface up/down electro-detection module 5, reset control module 6
With chip emulation module 7.Debugging/operation control module 4 is connected with emulator management module 2, realizes emulator management module 2
The reception and response of order；Debugging/operation control module 4 is connected to chip emulation module 7, transmits emulator by JTAG signal
The debug command of management module 2；Debugging/operation control module 4, which is connected to, resets control module 6, exports RUN_EN signal to multiple
Position control module 6；
Interface up/down electro-detection module 5 is connected to and resets control module 6, realizes the electric control of interface up/down, exports VCC_
SEL signal gives reset control module 6；Interface up/down electro-detection module 5 is connected with interface VCC signal, detects interface VCC power supply
State；
Control module 6 is resetted, chip emulation module 7 is connected to, the RUN_EN exported according to debugging/operation control module 4
The VCC_SEL signal of signal and interface up/down electro-detection module 5 generates and resets nRST signal to chip emulation module 7, control
The operating status of emulation chip；
Chip emulation module 7, with reset control module 6 connect, realize chip functions emulation, wherein reset nRST signal and
NVM control module 8 is connected.
As shown in Fig. 2, providing reset control waveform diagram.JTAG_nRST signal is generated by emulator management module 2,
Low level effectively indicates to reset emulator hardware 3；DBG_EN signal is generated by chip emulation module 7, and high level indicates
CPU in chip emulation module 7 is in debugging mode；RUN_MODE and RUN_MODE_EN signal is debugging/operation control module
4 internal signal；RUN_EN signal is generated by debugging/operation control module 4.When RUN_EN signal is low level, indicate imitative
True device hardware 3 is in operational mode；When RUN_EN signal is high level, indicate that emulator hardware 3 is in debugging mode.
When emulator management module 2 and emulator hardware 3 are attached, emulator management module 2 generates JTAG_ first
For nRST reset signal to emulator hardware 3, debugging/operation control module 4 in emulator hardware 3 is detecting JTAG_nRST
After effective low level, set RUN_EN signal makes emulator hardware be in debugging mode immediately, completes the downloading of down-stream.It is imitative
True device management module 2 is after having downloaded program, and setting 4 inside RUN_MODE signal of debugging/operation control module is low level, together
When to emulator hardware 3 send operation order.Inside debugging/operation control module 4, detecting that RUN_MODE is low level
Effectively after, enable RUN_MODE_EN signal, by judge whether it is JTAG_nRST reset after first time (emulator manage mould
Block 2) operation order, output RUN_EN signal is low level, and emulator hardware is made to enter operational mode.
As shown in figure 3, providing emulator program downloading flow diagram, emulator hardware is realized in program download process
Pattern switching control.It is operated according to the following steps:
Step 1, emulator management module control program downloading starts, and resets emulator hardware by JTAG_nRST signal,
So that emulator is in debugging mode, the download command of emulator management module can be received；
Step 2, emulator carry out NVM program downloading, if NVM downloading terminate if enter step 3, if downloading be not finished after
It is continuous to execute step 2；
Step 3, emulator verification download to emulator hardware NVM data it is whether consistent with source data, if downloading data
It is correct then enter step 4,5 are entered step if downloading data mistake；
Step 4, setting emulator is operational mode, and setting RUN_MODE signal is 0；Emulator carries out hard reset and enters
Operational mode；
Step 5, emulator display downloading success or failure information terminates program and downloads process.
As shown in figure 4, providing emulator program debugging flow diagram realizes emulation during entering Debugging interface
The pattern switching control and NVM program downloading of device hardware.It is operated according to the following steps:
Step 1, emulator management module control program debugging starts, and resets emulator hardware by JTAG_nRST signal,
So that emulator is in debugging mode, the debugging download command of emulator management module can be received；
Step 2, emulator judges whether to NVM program downloading, if desired downloads NVM program and then enters step 3, if not
It needs to download NVM program and then enters step 5；
Step 3, emulator carry out NVM program downloading, if NVM downloading terminate if enter step 4, if downloading be not finished after
It is continuous to execute step 3；
Step 4, emulator verification download to emulator hardware NVM data it is whether consistent with source data, if downloading data
It is correct then enter step 5,6 are entered step if downloading data mistake；
Step 5, setting emulator is debugging mode, and setting RUN_MODE signal is 1；Emulator carries out hard reset and enters
Debugging mode；
Step 6, emulator enters normal procedure Debugging interface, or display NVM program downloads error message.
Claims (5)
1. a kind of emulator for supporting NVM power-down protection to test, which is characterized in that the emulator includes emulator management
Module and emulator hardware, in which:
Emulator management module is connected with emulator hardware, realizes the function of emulator program downloading-running and program debugging, leads to
It is hard to emulator hardware sending mode setting command, program downloading and program debugging order and emulator to cross JTAG_nRST signal
Hard/warm reset order of part；
Emulator hardware includes that debugging/operation control module, interface up/down electro-detection module, reset control module and chip are imitative
True module；
Debugging/operation control module is connected with emulator management module, realizes the reception and response of the order of emulator management module,
Debugging/operation control module is connected to chip emulation module, and the debug command of emulator management module is transmitted by JTAG signal
And response；Debugging/operation control module is connected to reset control module, exports RUN_EN signal and gives reset control module；
Interface up/down electro-detection module is connected to reset control module, realizes the electric control of interface up/down, exports VCC_SEL signal
Give reset control module；Interface up/down electro-detection module is connected with interface VCC signal, detects the state of interface VCC power supply, this
In interface VCC signal refer in particular to 7816 interface power signals and Type A interface in/out field ionization source indication signal；
It resets control module and is connected to chip emulation module, according to debugging/operation control module output RUN_EN signal and connect
The VCC_SEL signal of mouth up/down electro-detection module generates reset nRST signal and gives chip emulation module, controls emulation chip
Operating status；
Chip emulation module is connect with control module is resetted, and realizes chip functions emulation.
2. a kind of emulator for supporting NVM power-down protection to test according to claim 1, which is characterized in that described
Emulator controls emulator hardware when emulator management module and emulator hardware are attached by JTAG_nRST signal
Immediately enter debugging mode.
3. a kind of emulator for supporting NVM power-down protection to test according to claim 1, which is characterized in that described
After emulator completes program downloading, emulator hardware is in operational mode, can execute NVM power down protection function in the operating mode
The test program of energy.
4. a kind of emulator for supporting NVM power-down protection to test according to claim 1, it is characterised in that emulator
In the operating mode, when emulator hardware detects that interface VCC is invalid, emulator hardware is constantly in reset state；Work as detection
After powering on to interface VCC, emulator hardware executes program from initial address is resetted.
5. a kind of emulator for supporting NVM power-down protection to test according to claim 1, which is characterized in that described
Emulator executes interface communication program under debugging mode, and when program is parked in breakpoint, if detecting, interface VCC is invalid, emulation
Device hardware automatically switches to non-reset state, and user is supported to continue the single-step debug to program.
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| CN201610352699.7A CN106055382B (en) | 2016-05-26 | 2016-05-26 | A kind of emulator for supporting NVM power-down protection to test |
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| CN106055382B true CN106055382B (en) | 2019-03-08 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101968759A (en) * | 2009-07-27 | 2011-02-09 | 上海华虹集成电路有限责任公司 | Processor chip simulator with break-point function |
| CN103914331A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | Emulator supporting multi-chip configuration function |
| CN104346208A (en) * | 2013-07-31 | 2015-02-11 | 上海华虹集成电路有限责任公司 | Emulator system and emulation chip |
| CN104346207A (en) * | 2013-07-31 | 2015-02-11 | 上海华虹集成电路有限责任公司 | Simulator |
| CN104461859A (en) * | 2014-08-27 | 2015-03-25 | 北京中电华大电子设计有限责任公司 | Emulator and method for supporting NVM soft breakpoint debugging |
| CN104680059A (en) * | 2013-12-03 | 2015-06-03 | 北京中电华大电子设计有限责任公司 | Emulator for protecting chip firmware program and method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008226083A (en) * | 2007-03-15 | 2008-09-25 | Nec Electronics Corp | On-chip debug emulator, debugging method and microcomputer |
| US7983893B2 (en) * | 2008-01-08 | 2011-07-19 | Mentor Graphics Corporation | Fault support in an emulation environment |
-
2016
- 2016-05-26 CN CN201610352699.7A patent/CN106055382B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101968759A (en) * | 2009-07-27 | 2011-02-09 | 上海华虹集成电路有限责任公司 | Processor chip simulator with break-point function |
| CN103914331A (en) * | 2012-12-28 | 2014-07-09 | 北京中电华大电子设计有限责任公司 | Emulator supporting multi-chip configuration function |
| CN104346208A (en) * | 2013-07-31 | 2015-02-11 | 上海华虹集成电路有限责任公司 | Emulator system and emulation chip |
| CN104346207A (en) * | 2013-07-31 | 2015-02-11 | 上海华虹集成电路有限责任公司 | Simulator |
| CN104680059A (en) * | 2013-12-03 | 2015-06-03 | 北京中电华大电子设计有限责任公司 | Emulator for protecting chip firmware program and method thereof |
| CN104461859A (en) * | 2014-08-27 | 2015-03-25 | 北京中电华大电子设计有限责任公司 | Emulator and method for supporting NVM soft breakpoint debugging |
Non-Patent Citations (1)
| Title |
|---|
| "基于FPGA与Cortex-M3的仿真验证平台设计";李效白 等;《中国集成电路》;20131205(第12期);第43-47页 |
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