CN106054484A - Array substrate and liquid crystal display panel using same - Google Patents
Array substrate and liquid crystal display panel using same Download PDFInfo
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- CN106054484A CN106054484A CN201610692765.5A CN201610692765A CN106054484A CN 106054484 A CN106054484 A CN 106054484A CN 201610692765 A CN201610692765 A CN 201610692765A CN 106054484 A CN106054484 A CN 106054484A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
- G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides an array substrate. The array substrate comprises a plurality of subpixels. Each subpixel comprises a thin film transistor. At least one part of the subpixels forms groups of two subpixels, each group of two subpixels serves as a repeating unit, at least two repeating units are arranged in an adjacent manner, the two subpixel in each repeating unit have a joint first passivation layer via hole, a pixel electrode is connected with the drains of the thin film transistors of the two subpixels through the first passivation layer via hole, each subpixel in each repeating unit is provided with an outer data line located at the edge of the repeating unit and an inner data line located in the repeating unit, and the distance from each drain to the corresponding outer data line is larger than that from the drain to the corresponding inner data line. The array substrate has the advantages that sufficient space on the lateral side of the array substrate is guaranteed during the attaching of a support column, so that the support column can support Cell in a high-PPI panel, and the normal display of the panel is guaranteed.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly relate to a kind of array base palte and use the liquid crystal display of this array base palte
Panel.
Background technology
PS (support column) is the part in Thin Film Transistor-LCD (TFT-LCD) CF processing procedure, mainly to box
(Cell) playing a supporting role, it is ensured that Cell is thick, thus ensure the thickness of required liquid crystal, wherein support column includes main support column
(Main PS) and secondary support column (Sub PS).Existing frequently-used way is will to support according to required support column distribution density
Post is arranged between the color blocking of CF side (between R and B, B and G, or G and R), corresponding at array base palte (Array) collateral dagger
Appear between the passivation layer via hole (PLN hole) of two sub-pixs (Sub Pixel).
Seeing shown in Fig. 1 and Fig. 2, it is the situation of two sub-pixs, and each sub-pix is a repetitive, at array
Substrate-side, support column 10 occurs in passivation layer via hole 13 and the passivation layer via hole of another adjacent sub-pix 11 of sub-pix 11
Between 14, cell is played a supporting role, due to passivation layer via hole 13 and the passivation layer of another sub-pix 11 of sub-pix 11
The spacing of via 14 is relatively large, and therefore corresponding in array base palte side support column can occur according to design needs arbitrarily
Between the passivation layer via hole of two sub-pixs.Seeing shown in Fig. 3 and Fig. 4, it is the situation of four sub-pixs, with two sub-pixs
Situation similar, each sub-pix is a repetitive, and in array base palte side, support column 10 occurs in the sub-picture of adjacent two
Element 11 passivation layer via hole between, cell is played a supporting role, due to two adjacent sub-pixs 11 passivation layer via hole it
Spacing is relatively large, and therefore corresponding in array base palte side support column can need to occur in two of arbitrary neighborhood according to design
Between the passivation layer via hole of sub-pix 11.
This way is when PPI (per inch pixel count) is relatively low, due to the spacing of the passivation layer via hole of two sub-pixs
Relatively large, the support column of design can be met between two passivation layer via hole, thus cell is played a supporting role, but
It is that it is sub-for WQHD (WQHD be a kind of resolution be the high definition screen parameter of 2560x 1440), the panel of the highest PPI
The size of pixel can become less, such that the distance between the passivation layer via hole of two sub-pixs is less, adds work
Deviation on skill processing procedure can cause the distance between actual passivation layer via hole less, and the support column chi that high PPI panel is corresponding
Very little again can not be the least, so ensureing on the premise of support column size constancy, design according to existing support column position distribution
It is likely to result in support column and appears in passivation layer via hole edge when Cell fits, even can be directly inserted into passivation layer via hole
In, shown in Figure 5, each sub-pix 11 is a repetitive, due to the passivation layer via hole of two adjacent sub-pixs 11
Distance between 13 and 14 is little, and support column 10 occurs in the edge of passivation layer via hole 13 and 14, support column 10 when Cell fits
Supporting role to Cell reduces accordingly, may affect the normal display of display panels.
Therefore the design of a kind of new array base palte is needed badly, to avoid drawbacks described above to occur.
Summary of the invention
The technical problem to be solved is to provide a kind of array base palte and uses the liquid crystal display of this array base palte
Panel, it ensure that in high PPI panel, Cell is played a supporting role by support column, it is ensured that the normal display of panel.
In order to solve the problems referred to above, the invention provides a kind of array base palte, including multiple sub-pixs, each sub-pix bag
Including a thin film transistor (TFT), at least one of sub-pix is grouped two-by-two as a repetitive, at least two repetitive phase
Adjacent arrangement, two described sub-pixs in each repetitive have the first common passivation layer via hole, and pixel electrode passes through institute
State the first passivation layer via hole to be connected with the drain electrode of the thin film transistor (TFT) of these two sub-pixs, in each described repetitive, often
One sub-pix has an outer data line and being positioned at repetitive edge and is positioned at the inner data line within repetitive, institute
State the distance distance more than described drain electrode to described inner data line of drain electrode extremely described outer data line.
Further, two described sub-pixs in each repetitive have common pixel electrode via.
Further, each described sub-pix has a pixel electrode via, described pixel electrode layer and data line layer it
Between be provided with a passivation layer.
Further, each sub-pix has one second passivation layer via hole, with at described pixel electrode layer and described data wire
Described passivation layer is formed between Ceng.
Further, the distance between two the first passivation layer via hole of two adjacent repetitives is more than a color membrane substrates
On support column end face width.
The present invention also provides for a kind of display panels, and including color membrane substrates and array base palte, described color membrane substrates includes
Multiple support columns for keeping cell-gap extended towards described array base palte, described array base palte includes multiple sub-picture
Element, each sub-pix includes that a thin film transistor (TFT), at least one of sub-pix are grouped as a repetitive two-by-two, at least
Two repetitive arranged adjacent, two described sub-pixs in each repetitive have the first common passivation layer via hole,
Described first passivation layer via hole allows pixel electrode to be connected with the drain electrode of the thin film transistor (TFT) of these two sub-pixs, described support column
Position between two the first passivation layer via hole of corresponding two adjacent repetitives is arranged.
Further, two described sub-pixs in each repetitive have common pixel electrode via.
Further, each described sub-pix has a pixel electrode via, described pixel electrode layer and data line layer it
Between be provided with a passivation layer.
Further, each sub-pix has one second passivation layer via hole, with at described pixel electrode layer and described data wire
Described passivation layer is formed between Ceng.
Further, the distance between two the first passivation layer via hole of two adjacent repetitives is more than described color film base
The end face width of the support column on plate.
It is an advantage of the current invention that in the sub-pix of high PPI panel, drain electrode made to two data line Unequal distance,
And two sub-pixs are shared a first passivation layer mistake as a repetitive, two sub-pixs of same repetitive
Hole, the position between two the first passivation layer via hole of corresponding two the adjacent repetitives of the collateral dagger of CF is arranged, this
Design may insure that support column has enough spaces when laminating in array base palte side, and is unlikely to fall into due to insufficient space
In via, thus ensure that in high PPI panel, Cell is played a supporting role by support column, it is ensured that the normal display of panel.
Accompanying drawing explanation
Fig. 1 is the support column distribution schematic diagram that the array base palte side of existing display panels is corresponding；
Fig. 2 is the actual distribution situation in wiring of the schematic diagram shown in Fig. 1；
Fig. 3 is the support column distribution schematic diagram that the array base palte side of another existing display panels is corresponding；
Fig. 4 is the actual distribution situation in wiring of the schematic diagram shown in Fig. 3；
Fig. 5 is the support column distribution schematic diagram that the array base palte side of another existing display panels is corresponding；
Fig. 6 is the distribution schematic diagram of the first passivation layer via hole of array base palte of the present invention；
Fig. 7 is the first detailed description of the invention of schematic diagram shown in Fig. 6 actual distribution situation in wiring；
Fig. 8 is the second detailed description of the invention of schematic diagram shown in Fig. 6 actual distribution situation in wiring；
Fig. 9 is the support column distribution schematic diagram that the array base palte side of display panels of the present invention is corresponding.
Detailed description of the invention
The array base palte below in conjunction with the accompanying drawings present invention provided and the tool of the display panels using this array base palte
Body embodiment elaborates.
See shown in Fig. 6 and Fig. 7, in the first detailed description of the invention of array base palte of the present invention, array base palte of the present invention
Including multiple sub-pixs 21, each sub-pix 21 includes a thin film transistor (TFT) (not indicating in accompanying drawing).At least one of sub-picture
Element 21 is grouped two-by-two as a repetitive 22, at least two repetitive 22 arranged adjacent.
Two described sub-pixs 21 in each repetitive 22 have the first common passivation layer via hole 23, i.e. two institutes
State sub-pix 21 and share first passivation layer via hole 23.Described first passivation layer via hole 23 allows pixel electrode (in accompanying drawing not
Indicate) it is connected with the drain electrode 24 of the thin film transistor (TFT) of these two sub-pixs 21.In each described repetitive 22, each sub-picture
Element 21 has an outer data line 211 and being positioned at repetitive 22 edge and is positioned at the inner data line within repetitive 22
212, in each repetitive 22, two sub-pixs 21 have common inner data line 212, if the source of a sub-pix 21
Pole is connected with its outer data line 211, then the source electrode of another sub-pix 21 is then connected with inner data line 212.
In array base palte of the present invention, distance L1 of described drain electrode 24 to described outer data line 211 is more than described drain electrode
24 to distance L2 of described inner data line 212, the most described drain electrode 24 to outer data 211 and inner data line 212 Unequal distance.
Described first passivation layer via hole 23 strides across described inner data 212, to form the common via of two described sub-pixs 21.
Owing to distance L1 of described drain electrode 24 to described outer data line 211 is more than described drain electrode 24 to described inner data
Distance L2 of line 212, two drain electrodes in same repetitive 22 are close to each other so that in each repetitive 22, Mei Yiya
The distance of pixel 21 to outer data line 211 is than the distance of sub-pix 11 (seeing Fig. 5) of the prior art to outer data line
Greatly, and then increase the distance between two the first passivation layer via hole 23 of two repetitives 22, thus be LCD
The support column of the color membrane substrates of plate provides enough spaces, it is ensured that described support column is unlikely to due to insufficient space when laminating
And fall in the first passivation layer via hole 23.Preferably, see Fig. 9, two the first passivation layers of two adjacent repetitives 22
Distance H between via 23 is more than the support column 20 end face width W on a color membrane substrates such that it is able to be liquid crystal display further
The support column 20 of the color membrane substrates of panel provides enough spaces.
Preferably due to two described sub-pixs 21 share first passivation layer via hole 23, if pixel electrode is protected
Stay original design, then may result in pixel electrode and data wire short circuit.In order to avoid the generation of the situation of short circuit, ginseng
Seeing Fig. 7, in this embodiment, two described sub-pixs 21 in each repetitive 22 have common pixel electrode
Via 25, i.e. two described sub-pixs 21 share a pixel electrode via 25, can avoid pixel electrode and data line contact and
Short circuit.
Array base palte of the present invention also provides for one second detailed description of the invention, it is possible to avoid pixel electrode and data wire short circuit.
Seeing Fig. 8, the present invention the second detailed description of the invention is with the difference of the first detailed description of the invention, each described sub-pix
Having a pixel electrode via 25, i.e. two described sub-pixs 21 do not share a pixel electrode via 25, but, at described picture
It is provided with a passivation layer (not indicating in accompanying drawing), such that it is able to avoid pixel electrode and data between element electrode layer and data line layer
Line short circuit.Seeing Fig. 8, form passivation layer between described pixel electrode layer and described data line layer, each sub-pix 21 has
One passivation layer via hole 26, pixel electrode may pass through described passivation layer via hole 26 and contacts with described drain electrode 24.
Seeing Fig. 9, the present invention also provides for a kind of display panels.Described display panels includes that color membrane substrates is (attached
Figure does not indicates) and array base palte (not indicating in accompanying drawing).Described color membrane substrates includes multiple extending towards described array base palte
For keeping the support column 20 of cell-gap.Described array base palte includes multiple sub-pix 21.
Seeing shown in Fig. 6 and Fig. 7, each sub-pix 21 includes a thin film transistor (TFT) (not indicating in accompanying drawing).At least one
The sub-pix 21 divided is grouped two-by-two as a repetitive 22, at least two repetitive 22 arranged adjacent.
Two described sub-pixs 21 in each repetitive 22 have the first common passivation layer via hole 23, i.e. two institutes
State sub-pix 21 and share first passivation layer via hole 23.Described first passivation layer via hole 23 allows pixel electrode (in accompanying drawing not
Indicate) it is connected with the drain electrode 24 of the thin film transistor (TFT) of these two sub-pixs 21.In each described repetitive 22, each sub-picture
Element 21 has an outer data line 211 and being positioned at repetitive 22 edge and is positioned at the inner data line within repetitive 22
212, in each repetitive 22, two sub-pixs 21 have common inner data line 212, if the source of a sub-pix 21
Pole is connected with its outer data line 211, then the source electrode of another sub-pix 21 is then connected with inner data line 212.
In array base palte of the present invention, the distance of described drain electrode 24 to described outer data line 211 is more than described drain electrode 24
To the distance of described inner data line 212, the most described drain electrode 24 to outer data 211 and inner data line 212 Unequal distance.Described
First passivation layer via hole 23 strides across described inner data 212, to form the common via of two described sub-pixs 21.
Owing to the distance of described drain electrode 24 to described outer data line 211 is more than described drain electrode 24 to described inner data line
The distance of 212, two drain electrodes in same repetitive 22 are close to each other so that in each repetitive 22, each sub-pix
The distance of 21 to outer data line 211 is bigger than the distance of sub-pix 11 (seeing Fig. 5) of the prior art to outer data line, enters
And increase the distance between two the first passivation layer via hole 23 of two repetitives 22, thus it is the coloured silk of display panels
The support column 20 of film substrate provides enough spaces, it is ensured that described support column 20 is unlikely to due to insufficient space when laminating
Fall in the first passivation layer via hole 23.Preferably, see Fig. 9, two the first passivation layer mistakes of two adjacent repetitives 22
Distance H between hole 23 is more than the support column 20 end face width W on a color membrane substrates such that it is able to be LCD further
The support column 20 of the color membrane substrates of plate provides enough spaces.
Preferably due to two described sub-pixs 21 share first passivation layer via hole 23, if pixel electrode is protected
Stay original design, then may result in pixel electrode and data wire short circuit.In order to avoid the generation of the situation of short circuit, ginseng
Seeing Fig. 7, in this embodiment, two described sub-pixs 21 in each repetitive 22 have common pixel electrode
Via 25, i.e. two described sub-pixs 21 share a pixel electrode via 25.
It addition, see Fig. 8, in another detailed description of the invention, each described sub-pix has a pixel electrode via 25,
I.e. two described sub-pixs 21 do not share a pixel electrode via 25, but, described pixel electrode layer and data line layer it
Between be provided with a passivation layer (not indicating in accompanying drawing), such that it is able to avoid the short circuit of pixel electrode and data wire.See Fig. 8, each
Sub-pix 21 has a passivation layer via hole 26, to form described passivation between described pixel electrode layer and described data line layer
Layer.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. an array base palte, including multiple sub-pixs, each sub-pix includes a thin film transistor (TFT), it is characterised in that at least
The sub-pix of a part is grouped two-by-two as a repetitive, at least two repetitive arranged adjacent, each repetitive
Two interior described sub-pixs have the first common passivation layer via hole, and pixel electrode is by described first passivation layer via hole and is somebody's turn to do
The drain electrode of the thin film transistor (TFT) of two sub-pixs connects, and in each described repetitive, each sub-pix has one and is positioned at weight
The outer data line and one of multiple cell edges is positioned at the inner data line within repetitive, described drain electrode to described outer data
The distance of line is more than the distance of described drain electrode to described inner data line.
Array base palte the most according to claim 1, it is characterised in that two described sub-pix tools in each repetitive
There is common pixel electrode via.
Array base palte the most according to claim 1, it is characterised in that each described sub-pix has a pixel electrode mistake
Hole, is provided with a passivation layer between described pixel electrode layer and data line layer.
Array base palte the most according to claim 3, it is characterised in that each sub-pix has one second passivation layer via hole,
To form described passivation layer between described pixel electrode layer and described data line layer.
Array base palte the most according to claim 1, it is characterised in that two first passivation of two adjacent repetitives
Distance between layer via is more than the support column end face width on a color membrane substrates.
6. a display panels, including color membrane substrates and array base palte, described color membrane substrates includes multiple towards described battle array
The support column for keeping cell-gap that row substrate extends, it is characterised in that described array base palte includes multiple sub-pix, often
One sub-pix includes that a thin film transistor (TFT), at least one of sub-pix are grouped two-by-two as a repetitive, at least two
Repetitive arranged adjacent, two described sub-pixs in each repetitive have the first common passivation layer via hole, described
First passivation layer via hole allows pixel electrode to be connected with the drain electrode of the thin film transistor (TFT) of these two sub-pixs, and described support column is corresponding
Position between two the first passivation layer via hole of two adjacent repetitives is arranged.
Display panels the most according to claim 6, it is characterised in that two described sub-pictures in each repetitive
Element has common pixel electrode via.
Display panels the most according to claim 6, it is characterised in that each described sub-pix has a pixel electrode
Via, is provided with a passivation layer between described pixel electrode layer and data line layer.
Display panels the most according to claim 8, it is characterised in that each sub-pix has one second passivation layer mistake
Hole, to form described passivation layer between described pixel electrode layer and described data line layer.
Display panels the most according to claim 6, it is characterised in that two of two adjacent repetitives
Distance between one passivation layer via hole is more than the end face width of the support column on described color membrane substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610692765.5A CN106054484A (en) | 2016-08-19 | 2016-08-19 | Array substrate and liquid crystal display panel using same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610692765.5A CN106054484A (en) | 2016-08-19 | 2016-08-19 | Array substrate and liquid crystal display panel using same |
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| CN106054484A true CN106054484A (en) | 2016-10-26 |
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| CN201610692765.5A Pending CN106054484A (en) | 2016-08-19 | 2016-08-19 | Array substrate and liquid crystal display panel using same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109637420A (en) * | 2019-01-09 | 2019-04-16 | 昆山国显光电有限公司 | Pixel arrangement structure, display panel and display device |
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| US20160131952A1 (en) * | 2014-11-07 | 2016-05-12 | Samsung Display Co., Ltd. | Display panel and method of manufacturing the same |
| CN105655290A (en) * | 2016-01-05 | 2016-06-08 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, array substrate and manufacturing method thereof |
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| CN104062821A (en) * | 2014-06-05 | 2014-09-24 | 厦门天马微电子有限公司 | Thin-film transistor array base plate, display panel and display device |
| US20160131952A1 (en) * | 2014-11-07 | 2016-05-12 | Samsung Display Co., Ltd. | Display panel and method of manufacturing the same |
| CN104698697A (en) * | 2015-02-11 | 2015-06-10 | 友达光电股份有限公司 | Pixel structure and display panel |
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Application publication date: 20161026 |