CN106033791B - A kind of memory component - Google Patents

Abstract

The invention discloses a kind of memory component, including the multi-layer laminate structure with multiple conductive layers.The multiple columns directly handed over base material, each column include multiple series winding storage units, on the crosspoint of this column and these conductive layers.A plurality of serial selection line is located above these conductive layers.Multiple bit lines are located above these serial selection lines, these columns are arranged on a rule grid with non-rectangle parallelogram element born of the same parents.The a plurality of parallel column flat cable of these column arrangement forms, every column flat cable is with these bit lines with θ>0 ° of scissors junction；Each column flat cable has n (n>1) column, all columns all intersect in these serial selection lines one specific common serial selection line.The arrangement mode allows the bit line density of bigger and higher data processing rate, and reduce the quantity of serial selection line because operation repetitive increases, and reduces interference, power consumption and unit born of the same parents' capacitance.

Description

A kind of memory component

Technical field

The invention relates to a kind of high-density storage element (high density memory devices), especially Relate to one kind include multilayered memory unit plane layer (multiple planes of memory cells) and arrange and Form the memory component of 3 D stereo (Three-Dimension, 3D) array, i.e. high velocity vertical channel solid nand memory Parallelogram storage unit design.

Present application is files an application in January 17 in 2014, number 14/157,550, entitled solid semiconductor element The continuous case in part of the US application case of (THREE-DIMENSIONAL SEMICONDUCTOR DEVICE) (Continuation-In-Part), herein and the mode of (incorporated by reference) is incorporated by reference into, it will This full patent texts is recorded among this specification.

The mode that the content of present application can be also incorporated by reference into, reference (makes reference) and this case are on the same day It files an application, number 14582963, the torsion Array Design of the three-dimensional nand memory of entitled high velocity vertical channel (TWISTED ARRAY DESIGN FOR HIGH SPEED VERTICAL CHANNEL 3D NAND MEMORY), inventor US application case for Chen Shihong.

Background technology

General memory cell technologies are contracted to the critical size (critical dimensions) of integrated circuit component The limit, designer is sought for more planar layers technologies (techniques for stacking of storage unit Multiple planes of memory cells), to obtain larger storage volume (storage capacity) and smaller position Cost (costs per bit).For example, Lai, et al., " A Multi-Layer Stackable Thin-Film Transistor(TFT)NAND-Type Flash Memory,”IEEE Int'l Electron Devices Meeting, 11-13Dec.2006；And Jung et al., " Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure For Beyond 30nm Node, " IEEE Int'l Electron Devices Meeting, 11-13Dec.2006, content Description uses thin-film transistor technologies (thin film transistor techniques) to charge trapping memory skill In art (charge trapping memory technologies).And the mode that above-mentioned periodical content will be incorporated by reference into, Full text is recorded among this specification.

In addition, Katsumata, et al., " Pipe-shaped BiCS Flash Memory with 16Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices, " 2009Symposium on VLSI Technology Digest of Technical Papers, 2009, it is interior Hold a kind of knot that vertical nand storage unit (vertical NAND cells) is provided in charge trapping memory of description Structure.The periodical content is recorded among this specification in full also through the mode being incorporated by.The described knots of Katsumata Structure includes vertical nand grid (vertical NAND gate), uses silicon-oxide-nitride-oxide-silicon (silicon-oxide-nitride-oxide-silicon, SONOS) charge-trapping technology, in each grid/vertical channel The position that (vertical channel) intersects forms bit of storage (storage site).Such storage organization is to be used for arranging The semiconductor column of material for arranging into the vertical channel of NAND gate and the lower section selection gate for being adjacent to base material and positioned at its top It is formed based on the top selection gate in portion.It is formed using the flat word line layer with semiconductor material pillar cross arrangement more The horizontal wordline of item (word lines) forms the so-called grid around storage unit in each stratum (layer).

Fig. 1 is tubulose (pipe-shaped) BiCS flash memory cells (BiCS being painted disclosed in a row Katsumata Flash cell) horizontal profile (horizontal cross-section) figure on word line layer.This structure, which includes, to be had The column (pillar) 15 of semi-conducting material core (center core) 110 passes perpendicularly through the laminated construction of word line layer (stack of word line layers).Core 110 has the seam (seam) by passing through center caused by deposition technique 111.Dielectric charge catch structure, such as the first silicon oxide layer 112,113 and second silicon oxide layer 114 of silicon nitride layer (can be described as ONO structure) or other multilayer dielectric charge trapping structures surround core 110.Grid surrounds wordline (gate all-around Word line) 115 intersect with column 15.Frustum (frustum) of the column 15 in each stratum is surrounded with grid Wordline 115 is in the combination of this layer, one storage unit of formation.

Fig. 2 is the perspective view for being painted a three-dimensional semiconductor element.It includes the multilayer laminated knots of multiple wordline conductive layers 11 Structure (multilevel stack), wherein each wordline conductive layer 11 is parallel base material 10；It is multiple directly to be handed over base material 10 The column 15 of (oriented orthogonally to), wherein each column 15 include multiple series winding (series- Connected storage unit), positioned at the column 15 and multiple crosspoint (cross- of these wordline conductive layers 11 Points between)；And a plurality of serial selection line (string select lines, SSLs) 12 is parallel to base material 10 and is located at These 11 tops of wordline conductive layer.Each serial selection line 12 intersects with corresponding a line column 15.In each column The infall of body 15 and serial selection line 12 defines the selection gate of the column 15.This structure also includes a plurality of Parallel bit line 20 is located in 12 top of serial selection line and the stratum of parallel base material 10.Each bit line 20 is stacked and placed on (superpose) on a corresponding column 15, and each column is located at 20 lower section of bit line.These columns 15 It may be constructed such the structure shown as depicted in FIG. 1.

Fig. 3 is part-structure top view depicted according to fig. 2.Thus two figures can be seen that wordline conductive layer 11 and A part of column 15 in overall structure intersects.Wordline conductive layer 11 defines a storage unit block (block of memory cells).Therefore, data (data) are read from particular memory location block, control circuit will be activated first (activates) a wordline conductive layer 11, to select the spy in a particular memory location block and multi-layer laminate structure Determine stratum, and further activate a serial selection line 12 and select a particular row.Lower section selection gate (not being painted) is activated simultaneously, Then a line storage unit is read by parallel (in parallel) to page buffer (pagebuffer) by bit line 20 (not being painted).(" activation " as used herein is meant, grants particular bias voltage to influence (to give effect to) quilt The storage unit or switch of link.This bias can be high or low, hold depending on the design of memory).Rule according to product Lattice and design, page buffer can preserve one or two row data, the operation that whole page is read in such a case, after may including Continuous two or the activation of a plurality of serial selection line 12.

When storage density (memory density) is significantly increased in three-dimensional stacked memory structure as expected while also spreads out Many technologic challenges are given birth to, since it is desired that etching very deep hole to pass through many layers.The width of these deep holes must add Width, and the lateral distance of each deep hole center to center must increase, to meet process specification (process windows).With The progress of production process, can not only be increased by increasing the wordline plane in laminated construction (word line planes) Storage volume more can increase storage volume by way of the space between reducing column 15.Fig. 4 is to be painted a diminution It is serial in the number of the top view of the structure of critical size, wherein memory cell areas bit line 20 in the block and storage unit block The number of selection line 12 both increases.This not only reduces cost, while also can reach and promote data read/write rate (read/ Write data rate) purpose.Because greater number of bit line 20 represents operation repetitive (parallel operation) Increase.But then, greater number of serial selection line 12 represent more multiple memory cell can be by selecting institute by wordline Caused Vpass interferes (Vpass disturb).Unit born of the same parents capacitance (unit cell capacitance) is also with serial choosing It selects the increase of 12 quantity of line and increases, thus power consumption is caused to increase and makes the service speed of element slack-off.

Promote bit line density (bit density) by increasing the quantity of the wordline conductive layer 11 in laminated construction, remove Layer number increase derives except expected process challenge, also its shortcoming.By Fig. 2 it can be seen that one has stepped knot Structure is connected to the Typical arrangements of wordline conductive layer 11.In order to form contact 22, use and be connected to wordline conductive layer 11 Online 24 in the metal of side, it is necessary to be made through the deep trenches (deep trench) of this structure.These contacts 22 are illustrated in simultaneously In the top view of Fig. 4.In a typical design, the line number of a storage unit block cylindrical body 15 at least can be with contact 22 And the quantity of accumulation layer (wordline conductive layer 11) is as many.For example, Komori, Y., et.al. are referred to, " Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device,"Electron Devices Meeting,2008,IEDM 2008,IEEE International,vol.,no.,pp.1-4,15-17(Dec.2008)at 2, the mode that above-mentioned periodical content will be incorporated by reference into is recorded among this specification in full.Due to the increase of accumulation layer Promoting the number of serial selection line 12 increases, thus also results in power consumption and increase and make the service speed of element slack-off.

Therefore, it is in need to create a kind of reliable solution, it is same in the bit line density for increasing three-dimensional storage structure When reduce its negative impact caused, with obtain preferable chip yield, circuit closer, efficiency is more powerful, element or System.

Invention content

Roughly, a kind of memory component, the multilayer of multiple conductive layers with parallel base material are provided according to technology Laminated construction.Multiple columns are directly handed over base material, each column include multiple series winding storage units, positioned at this column with On the crosspoint of these conductive layers.A plurality of serial selection line is located above these conductive layers, and in these columns and these strings Each crosspoint of row select line defines the selection gate of a column respectively.Multiple bit lines are located on serial selection line Square, multiple columns in multiple columns, which are arranged in one, has non-rectangle parallelogram (non-rectangular Parallelogram) on the rule grid (regular grid) of unit born of the same parents (unit cell).These columns can be arranged And define a plurality of parallel columnar body flat cable (parallel pillar lines).These parallel columnar body flat cables Acute angle (acute angle) θ (θ are pressed from both sides with these bit lines>0°).Each parallel columnar body flat cable has n (n>1) column Body.All columns all intersect with a specific common serial selection line in these serial selection lines.Such arrangement Mode may be allowed the bit line of higher density, therefore higher data read/write rate can be obtained because of the increase of operation repetitive.Together When can also use small number of serial selection line, by reducing unit born of the same parents' capacitance, to reduce interference and power consumption, and then Promote data read/write rate.

The invention content of the aforementioned present invention is only the various understandings that basis is provided towards (aspect) for the present invention.This Invention content is not to show key or necessary component nor the profile to describe scope of the invention as claimed.Its mesh Be only to show idea of the invention in a simplified manner, using the prelude as aftermentioned detailed embodiment.The spy of the present invention Determine embodiment to will be described in right, specification and schema.

Description of the drawings

In order to be clearer and more comprehensible to the above embodiment of the present invention and other objects, features and advantages, spy lift it is several compared with Good embodiment, and coordinate institute's accompanying drawings, it is described in detail below：

Fig. 1 is the horizontal sectional drawing for being painted tubing string shape BiCS flash memory cells；

Fig. 2 is the perspective view for being painted a three-dimensional semiconductor element；

Fig. 3 is part-structure top view depicted according to fig. 2；

Fig. 4 is part-structure top view depicted according to fig. 2；Accommodated due to critical dimension reduction more wordline and Serial selection line；

Fig. 5 be illustrate the column volume array that is located in conventional stereo memory component as depicted in Fig. 2 and Fig. 4 on regard Figure；

Fig. 6, Fig. 7, Fig. 9 and Figure 10 are depicted according to some embodiments of the present invention are located in three-dimensional storage element The top view of column volume array；And

Fig. 8 A to Fig. 8 D (being referred to as Fig. 8) are to be painted parallelogram element born of the same parents (unit parallelogram cell) A variety of variations.

【Symbol description】

10：Base material 11：Conductive layer

12：Serial selection line 15：Column

20：Bit line 22：Contact

24：Online 110 in metal：Core

111：Seam 112：First silicon oxide layer

113：Silicon nitride 114：Second silicon oxide layer

115：Grid surrounds wordline 512：Concatenate selection line

515：Column 520：Bit line

612：Serial selection line

612-1~612-5：Serial selection line

615：Column 620：Bit line

812-1~812-2：Serial selection line

813：Single serial selection line 820：Bit line

912：Serial selection line 920：Bit line

930-1~930-4：Column flat cable

1012：Serial selection line 1020：Bit line

1030-1~1030-4：Column flat cable

A：Column B：Column

C：Column D：Column

d：The distance between column p：The interval of bit line

ABCD：Unit born of the same parents S：Exceptional space

G：Edge gate criterion θ：Acute angle

Specific embodiment

Following description, which can be provided in any technical field, has usually intellectual's tool to use, make the present invention. The description is provided only for specific with requirement background.Having usually intellectual in technical field can be to the reality that is disclosed for It applies example to be retouched, and rule disclosed herein will be applicable to other embodiment and application, without departing from this hair Bright scope.Therefore, the proposition of embodiment is only the technical characteristic for illustrating the present invention, is not limited to this hair Bright right.

Fig. 5 is to illustrate to regard on the conventional stereo memory component cylindrical body array as depicted in Fig. 2 and Fig. 4 Figure.Each dot (dot) in Fig. 5 represents the lateral position (lateral position) of corresponding column 515.This " transverse direction " Spatial Dimension used in place (" lateral " dimensions) refers to the structure space dimension of parallel base material (also It is the Spatial Dimension that X-axis and Y-axis are indicated in Fig. 1, Fig. 2, Fig. 3 and Fig. 4).This structure include Fig. 2 depicted in it is all its His element, but for the sake of being clearly painted, most element is omitted in Figure 5.Particularly, the knot depicted in Fig. 5 Structure includes the multi-layer laminate structure of multiple wordline conductive layers 11, wherein all parallel base material of each stratum.A plurality of serial selection line 512 (wherein one is shown in Fig. 5) parallel base material, and positioned at 11 top of wordline conductive layer.These serial selection lines are rectangle, and A side with parallel Y direction, shows as shown graphically in fig 5.It is so-called herein to be located at other stratum " on (above) " or " it Under (below) " a specific stratum, in different embodiments, the middle layer (intervening of one layer or more can be passed through Layers it) is separated with other stratum.Identical solution shows that mode is also applied for being located at other stratum " top (superposing) " An or specific stratum of " lower section (underlying) ".

Each concatenates selection line 512 and a respective different column subset (a in multiple columns 515 Respective distinct subset of pillars) intersect.And in each concatenation selection line 512 and each column The infall of shape body 515 defines a selection gate of the column 515 respectively.A plurality of parallel digit lines 520 (wherein one It is shown in Fig. 5) extend along the X-direction of Fig. 5, it is arranged on parallel base material and positioned at one of 512 top of concatenation selection line In stratum.Each bit line 520 is located on a corresponding column 515.And each column 515 is located at a bit line 520 lower sections.Each column 515 directly hands over (vertical, along the Z-direction depicted in Fig. 2) with base material, and includes multiple series windings Storage unit, between these columns 515 and the crosspoint of these conductive layers 11.In one embodiment of this invention, The transverse cross-sectional view of this column 515 is depicted in Fig. 1.

In the arrangement mode of Fig. 5, it is possible to find the column 515 in column volume array is arranged in X-axis and Y-axis The rule grid of two horizontal space dimensions.Wherein, X-axis parallel digit lines 520, Y-axis are directly handed over bit line 520." rule so-called herein Rule grid " or " regular array (regular array) " refer to be distinguished into the grid (array) of adjacent cells born of the same parents.Its Middle entirety storage unit can fill up this grid, and all storage units have the same shape and dimensions.In Figure 5, unit Born of the same parents are a squares (square), such as scheme depicted square ABCD.Meanwhile in a particular embodiment, grid is in itself It can include multiple columns 515 and net boundary, " grid " word as used herein does not need to any rule.

" unit born of the same parents " word as used herein in the rule grid, is defined as a kind of parallelogram, and four A vertex position is on four columns 515 of grid.For example, the parallelogram of the unit born of the same parents in Fig. 5 is by A, B, C and D tetra- A column is defined.Definition mode as used herein, unit born of the same parents are defined since column A, then in vertical wordline Set direction grid near column A column B.Then it selects not conllinear with column A and B within a grid (non-collinear with), but within a grid near the column C of column A, and select positioned at parallelogram Column D on 4th vertex.Outer unless otherwise indicated, " distance (distance) " between column described herein refers to The distance (Euclidean center-to-center distance) of two column euclidean center to center.In addition, this Locate " in the distance (distance in a particular dimension) of specific direction " to refer between two column The coordinate of two columns and ignores the coordinate in other directions in the difference of the direction.For example, in Figure 5, two column A and B it Between distance for d, equal to the distance between two column A and C.Between two column B and C " distance " (that is, euclidean away from From) it is √ 2d, but be d " in the distance of Y direction " between two column B and C.In addition, " near " described herein one is given The column of column refers to the column that the column shortest distance is given from this.If have there are one above from this The column of the identical shortest distance of given column, then one column of any of which all meets gives column most short distance from this From condition.

In the grid depicted in Fig. 5, unit born of the same parents are square." square " word as used herein, is " rectangle (rectangular) " specific embodiments of a word.Because square is a kind of isometric rectangle in four side.It is likewise, " square A shape " word is the specific embodiments of " diamond shape (rhombus) " word.Because square is also that a kind of four interior angles are all right angle The diamond shape of (right angles).Furthermore " square ", " rectangle " and " diamond shape " is all " parallelogram (parallelogram) " specific embodiments of a word.Rectangle is the parallelogram that a kind of four interior angles are all right angle；Diamond shape It is a kind of isometric parallelogram in four side；And it is all right angle four at isometric parallel four that square, which is then a kind of four interior angles, Shape.Therefore the square ABCD depicted in Fig. 5 can be referred to as diamond shape, rectangle and parallelogram simultaneously.

Fig. 6 is the top view of the depicted column volume array in stereochemical structure of an embodiment according to the present invention.With Each the same dot of Fig. 5 represents the lateral position of corresponding column 615.Although Fig. 6 is omitted for the sake of clear mark Being painted for most element, but this structure is still comprising the every other element in Fig. 2.Wherein, Fig. 6 depicts five serially Selection line 612-1 to 612-5 (being referred to as serial selection line 612) and and eight bit lines 620.

Similar with Fig. 5, subset of each serial selection line 612 respectively from different columns 615 in Fig. 6 is intersected, and Multiple selection gates are defined by these intersections.Similarly, each bit line 620 is stacked and placed on respectively on a column 615, Each column 615 is located at 620 lower section of bit line.However, in figure 6, column 615 can be arranged in rows and and bit line 620 straight friendships.Column 615 and next bit line of interlacing in per a line intersect；And these staggered rows (alternating rows) translates (shift), so as to set (the alternating sets of with staggered bit line The bit lines) intersect.Fig. 7 is another pattern for the arrangement mode for being painted Fig. 6.Column 615 therein is in addition to quantity It is more outer compared with Fig. 1, it is according to depicted in Fig. 1.Column 615 depicted in Fig. 7, serial selection line 612 and bit line 620 simultaneously Quantity is less than Fig. 6.Two figures have all been painted one group of parallelogram ABCD unit born of the same parents simultaneously.

The translation of staggeredly rows of arrangement mode and the row of column 615 provides two benefits.First, if d It is distance of two columns 615 in 620 direction of vertical bit lines, then relatively narrow interval p=d/2 may be used to form bit line 620. The distance of adjacent two column 615 in grid is not needed to reduce, you can accommodate the bit line of higher density.Second, it is possible to reduce string The quantity of row select line 612.Because the width of serial selection line 612 (directions of parallel digit lines), is broadened to and is enough and two rows Column 615 intersect.In other words, the width of each serial selection line 612 is enough 4 columns 615 with unit born of the same parents Intersect.For example, in figure 6 and figure 7,4 columns 615 of a serial selection line 612 and unit born of the same parents ABCD intersect.In addition, Only pipe intersects with two row columns 615, these 612 one of which of serial selection line are each with these 620 one of which of bit line A intersection still uniquely (uniquely) can make single a 615 enable of column (enable) in grid.It is this is because living Change a wordline conductive layer 11 and a serial selection line 612 still can uniquely select single storage in bit line 620 Unit.Therefore the parallelogram mesh depicted in Fig. 6 and Fig. 7, can all achieve the purpose that with highdensity bit line 620, And then by increasing operation repetitive and obtaining higher data processing rate, and reduce using less serial selection line 612 Interference, power consumption；And further by reducing unit born of the same parents' capacitance, to promote data processing rate.

Fig. 8 A to Fig. 8 D (being referred to as Fig. 8) are a variety of benefits for being painted parallelogram element born of the same parents.Fig. 8 A are to be painted to be located at Unit born of the same parents in the conventional mesh shown as depicted in fig. 3.In this example, the distance of column A and B center to center, with column The distance of body C and D center to center is equal, and generally adds minimum grid thickness G by the diameter of column to be determined. But because design criteria (design rule) serial selection line 812-1 and 812-2 (being referred to as serial selection line 812) it Between required exceptional space S and because tightened up edge gate criterion (edge gate rule) G, column A and C Therebetween and column B and D therebetween, in the distance of bit line direction, it is necessary to more than between column A and B both, And the distance of column C and D therebetween.

In the fig. 8b, the column for being located above a line is shifted to the right a distance, this segment distance is two columns The half of distance between body.This unit born of the same parents become non-rectangle parallelogram now.Since bit line does not need to and goes here and there Row select line is equally wide, in this embodiment it is not even necessary to wide with as column.In the structure of Fig. 8 B, twice of bit line can be accommodated, because This can double data processing rate by the increase of operation repetitive.The interval of bit line can be reduced to p=d/2.Wherein d is column In the distance in vertical bit lines direction between shape body.But since column staggeredly is located at the lower section of bit line 820 staggeredly, Ke Yitong Cross by serial selection line 812-1 and 812-2 be merged into as the mode of the single serial selection line 813 depicted in Fig. 8 C come together into Row decoding.Can reduce the quantity of serial selection line by this method, so by reduce unit born of the same parents capacitance reduce interference, Power consumption simultaneously promotes data processing rate.Finally, the serial selection line of merging and design criteria are in the space of bit line direction Limitation can be relaxed.Due to, exceptional space S and edge gate criterion G are not being needed, as depicted in Fig. 8 D, two row columns Body can be reduced in the space of bit line direction (distance).Two serial selection lines 813 bit line direction distance, also can therefore and It reduces.

Unit born of the same parents are reduced, while the area of unit born of the same parents can be made to become smaller in the height (height) of bit line direction.In fig. 8 a, scheme The area of unit born of the same parents depicted in 8A becomesMore than d2, becauseLength be more than d.Depicted in Fig. 8 B and Fig. 8 C The area of unit born of the same parents remain unchanged.But since unit born of the same parents are shorter than in the height of bit line direction depicted in Fig. 8 B and Fig. 8 C in Fig. 8 D Unit born of the same parents bit line direction height, therefore the area of the unit born of the same parents depicted in Fig. 8 D be less than Fig. 8 B and Fig. 8 C depicted in list The area of cellular.

Among a preferred embodiment, unit born of the same parents can be lowered in the height of bit line direction, until being located at parallel four side Distance between the column on each side of shape is kept constant.That is, line segment WithLength all Equal to d, and this flat shape quadrangle dimension diamond shape.More preferably, the relatively narrow interior angle of this diamond shape is 60 °, therefore line segmentLength Degree is also equal to d.Herein among an embodiment, the minimum value of the area of unit born of the same parents only has (√ 3/2) × d2.

The above-mentioned technology for being arranged in capable column and being translated toward vertical bit lines direction, can extend in various degree (by different amounts) translates the column of more line numbers (a larger number of rows).Such as Fig. 9 It is painted the adjacent column of three rows.Per a line column relative to the column of adjacent rows (immediately adjacent row) Body is shifted the distance of d/3, as a result can accommodate 3 times of wordline 820, therefore significantly increases operation repetitive.Between wordline Every p=d/3 can be reduced to, and single merging serial selection line can be reduced the number of serial selection line in grid to original 2/3 come.So further interference and power consumption are reduced, and further promote number by reducing unit born of the same parents capacitance According to processing speed.Finally, required by the merging serial selection line of column volume mesh, design criteria be located at serial selection line it Between (inter-SSLs) space S and bigrid thickness (dual gate thicknesses) G can also reduce.

Similar situation, Figure 10 are painted 5 adjacent row columns, and d/ is shifted relative to the column of adjacent rows per a line 5 distance, as a result can accommodate 5 times of wordline 1020, therefore more significantly increase operation repetitive.The interval of wordline can drop Down to p=d/5, and single merging serial selection line can be reduced the number of serial selection line in grid to original 4/5. So further reducing interference and power consumption by reducing unit born of the same parents capacitance, and further promote data processing speed Rate.Finally, the space required by the merging serial selection line of column volume mesh, design criteria between serial selection line S and stringent gate design criteria (severity of the gate thicknesses design rule) G can also subtract It is more few.

In general, the above-mentioned technology for being arranged in capable column and being translated toward vertical bit lines direction, can extend to by Multirow column translates one section of distance relative to the column d/n of adjacent rows.As a result n times of wordline 1020 can be accommodated, because This significantly increases operation repetitive.The interval of wordline can be reduced to p=d/n, and single merging serial selection line can be with The number of serial selection line in grid is reduced and causes original (n-1)/n.Finally, it is serially selected across the merging of column volume mesh The required space S and G between serial selection line of line, design criteria can also be reduced.

Referring again to Fig. 9, it is observed that the column in grid is by landscape configuration, and at plan view (plan view) It is upper to form a plurality of column flat cable (lines of pillars), " the column flat cable as shown in the dotted line of figure (pillar lines) " 930-1,930-2,930-3 and 930-4 (being referred to as column flat cable 930) (wherein, column For flat cable 930 itself merely to being just illustrated on figure for the sake of clear visual, not representing has substance feature to be present in element Among).These column flat cables are parallel to each other, and with bit line 920 with θ>0 ° of scissors junction.Further, it is also possible to it observes All there are 3 columns in the region of each serial selection line 912 to each column flat cable.Each column 3 columns of body flat cable are overlapped jointly with single serial selection line 912.

Similar situation, please refers to Figure 10, it is observed that the column in grid is by landscape configuration, and in plan view It is upper to form a plurality of column flat cable, " column flat cable " 1030-1,1030-2,1030-3 as shown in the dotted line of figure With 1030-4 (being referred to as column flat cable 1030).These column flat cables are parallel to each other, and with bit line 1020 with θ >0 ° of scissors junction.Further, it is also possible to observe each column flat cable in the area of each serial selection line 1012 All there are 5 columns in domain.5 columns of each column flat cable are jointly and single serial selection line 1012 Overlapping.

Similarly, under normal circumstances, the value of each n be grid cylindrical body by landscape configuration, and on plan view Form the number of a plurality of column flat cable.These column flat cables are parallel to each other, and with bit line with θ>0 ° of acute angle Intersect.In addition, each column flat cable all has n column in the region of each serial selection line.It is each N column of bar column flat cable is overlapped jointly with single serial selection line.

Therefore, it is arranged in the interval that capable column translates the bit line that can narrow toward vertical bit lines direction, simultaneously widening Serial selection line.However, ideal translation distance is that should to avoid result in the degree that bit line spacing narrows be more than original 1/10.This It is because meeting the design criteria for minimizing column-column distance, it may not be possible to which the spacing for meeting regulation bit line need to have The design criteria of minimum range.In addition if the spacing of bit line narrows more than original 1/10, required technique may be unable to reach Specification, so that the expected bit line needed to be stacked and placed on column is directed at column or expection is made to need the column that is staggered Bit line is staggered column.When the value of n is more than 10 (n>10) when, above-mentioned risk significant will improve.Due to influencing bit line spacer ruler The diminution factor of very little d/n is that the diminution factor of the distance between column d is identical, therefore limitation and the process of n values It reduces (process shrinking) and has no connection.The value of n is preferably less than or equal to 10 (n≤10).And the value of n must be whole Number.

Set-point (given value) used herein is " response (responsive) " preceding value (predecessor value), if this preceding value affects set-point.If there is middle process element, step or period, give Definite value " can still respond " preceding value.If this middle process element or step is combined with more than one value, middle process element Or the output signal of step is considered as " response " each input value.If set-point is equal to preceding value, this is only one Degenerate case (degenerate case), the wherein set-point are still considered as being " response " preceding value.Set-point is to another " degree of dependence (dependency) " of value can also make similar definition.

" the identification of a certain information project (an item of information) used herein (identification) " the direct explanation (direct specification) of the information project, is not needed to.Information can be with By indirect one or multilayer (one or more layers of indirection) briefly referring to an entity information (actual information) and then the quilt " identification (identified) " or one or more by identifying in some field A different information project and be identified.Wherein, these different information projects integrally add up the reality for being enough to determine information Body project (actual item of information).In addition, the meaning of " determining (determine) " used herein word " confirming (identify) " is identical.

The combination of indivedual independent technical characteristic or two or more these independent technique features is disclosed herein.At some In degree, the technical field tool usually intellectual can the overall description based on this specification, implement according to general knowledge The combination of these indivedual independent technical characteristics and technical characteristic.No matter these indivedual independent technical characteristics and technical characteristic It is described herein whether combination solves the problems, such as, and without limitation on scope of the presently claimed invention.Implementation disclosed by this case Example can include the combination of these indivedual independent technical characteristics and technical characteristic.Based on aforementioned reason, technology belonging to the present invention Has usually intellectual in field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.

Although the present invention is disclosed above with preferred embodiment, however, it is not to limit the invention.Skill belonging to the present invention Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Example Such as, although in the embodiments herein being described using the charge storage memory cells of vertical channel.Column and its The storage unit of his type can still utilize the various technical characteristics of the present invention, without realizing all advantages as described herein. Especially, it but is not limited to, various change class shape, suggestion or any in the paragraph in relation to technical background herein and all pass through reference The mode of being incorporated to is included into the content of this specification, is all included among the embodiment of description of the invention.In addition, various change class Any and all mode that is incorporated by reference into is included into the interior of this specification in shape, the paragraph of suggestion or this paper in relation to technical background Hold, be also considered to be taught by the other embodiment of this case.Embodiment described herein is only selected to this hair Bright principle and its practical application make best explanation, and then make to have usually intellectual in this field it will be appreciated that the present invention Various embodiments and the various modifications and retouching for being suitable for reaching expected special-purpose.Therefore, protection scope of the present invention is worked as and is regarded Subject to appended claims range is defined.

Claims (16)

1. a kind of memory component being located on a base material, including：

One multi-layer laminate structure has multiple conductive layers, the parallel base material of each these conductive layers；

Multiple columns are directly handed over the base material, these each columns include the storage unit of multiple series windings, positioned at these columns On the crosspoint of body and these conductive layers；

A plurality of serial selection line, the parallel base material, and above these conductive layers, these each serial selection lines and these columns A respective different column subset is intersected in shape body, and in each crosspoint of these columns and these serial selection lines point A column selection gate is not defined；And

A plurality of parallel bit line positioned at the parallel base material and is higher than in a stratum of these serial selection lines, these each bit lines This is stacked and placed on respectively in different column subset, and these each columns are located at the lower section of the one of these bit lines；

Wherein, multiple columns in these multiple columns are arranged in a rule grid of the tool there are two horizontal space dimension, The rule grid have a unit born of the same parents, unit born of the same parents include positioned at a parallelogram four vertex four column A, B, C and D,

Column B is located in the rule grid near column A person,

Column C is not conllinear with column A and column B, but near column A in the rule grid Person,

The parallelogram is a non-rectangle parallelogram, and with a line segmentThese vertical bit lines.

2. memory component according to claim 1, wherein these each storage units have a vertical channel structure, one Electric charge storage layer and an insulating layer.

3. memory component according to claim 1, wherein in the rule grid, it is each in these multiple columns It is not aligned with each other on a direction of these parallel bit lines to column, but be separated from each other, and be orthogonal to these bit lines There is the distance at least more than d/10, wherein d is the line segment in one transverse dimensionsLength.

4. four sides of memory component according to claim 1, the wherein parallelogram are isometric.

A 5. line segment of memory component according to claim 4, the wherein parallelogramLength be equal to the line SectionLength.

6. memory component according to claim 1, wherein in the rule grid, it is each in these multiple columns It is not aligned with each other on a direction of these parallel bit lines to column, but be separated from each other, and be orthogonal to these bit lines There is the distance for d/n, wherein d is the line segment in one transverse dimensionsLength, n is comprising the integer between 2 to 10.

7. memory component according to claim 1, wherein these serial selection lines include multiple rectangles, these each squares Shape has the one side for being orthogonal to these bit lines；

One wherein in these serial selection lines intersects with each of one in these bit lines, can uniquely identify these Single a column in multiple columns；

Wherein specific one of these serial selection lines, is broadened in a direction of the parallel bit line and is enough to make the particular serial Selection line is at least intersected with the column A in the particular one of these units born of the same parents and C.

8. memory component according to claim 7, wherein the particular serial selection line is in a direction of the parallel bit line Width, it is sufficient to the particular serial selection line is made to intersect with 4 columns in the particular one of these units born of the same parents.

9. four sides of memory component according to claim 8, the wherein parallelogram are isometric.

10. four sides of memory component according to claim 7, the wherein parallelogram are isometric.

11. memory component according to claim 7, wherein the particular serial selection line is in a direction of the parallel bit line Width, it is sufficient to make the particular serial selection line with respectively be located at non-conterminous two these units born of the same parents at least two column Intersect, wherein non-conterminous two these units born of the same parents are separated from each other on a direction of the not vertical bit line.

12. a kind of memory component being located on a base material, including：

One multi-layer laminate structure has multiple conductive layers, the parallel base material of each these conductive layers；

Multiple columns are directly handed over the base material, these each columns include the storage unit of multiple series windings, positioned at these columns On the crosspoint of body and these conductive layers；

A plurality of serial selection line, parallel base material, and above these conductive layers, and shape is multiple rectangles, it is each these Rectangle has the one side for being orthogonal to these bit lines, these each serial selection lines and in these columns one respective different column Body subset is intersected, and defines a column selection grid respectively in each crosspoint of these columns and these serial selection lines Pole；And

A plurality of parallel bit line positioned at the parallel base material and is higher than in a stratum of these serial selection lines, these each bit lines This is stacked and placed on respectively in different column subset, and these each columns are located at the lower section of the one of these bit lines；

Wherein, multiple columns in these multiple columns are by landscape configuration, and a plurality of column is formed on a plan view Flat cable, these column flat cables and these bit lines are to be more than 0 ° of a scissors junction；These each columns are flat Cable have n column, all these columns all with the specific common serial selection line in these serial selection lines Intersect, wherein n is the integer more than 1；

In a direction of these vertical bit lines, a length is in 2n times that the direction of these vertical bit lines is more than these bit lines, often A column in these bit lines of one nth bar person different from the one of these column flat cables intersects intersecting.

13. the value of memory component according to claim 12, wherein n is less than or equal to 10.

14. memory component according to claim 12, wherein n are comprising the integer between 2 to 10.

15. memory component according to claim 12, wherein these each bit lines it is parallel with these column it is flat Cable is intersected at just on the column in one of these column flat cables.

16. memory component according to claim 15, wherein with the specific common serial selection line intersect it is all this A little bit lines also intersect with the column in one of these column flat cables.