TWI594246B - Memory device and method for fabricating the same - Google Patents

Description

Memory element and manufacturing method thereof

The present invention relates to a high density memory component, and more particularly to a memory component incorporating a plurality of memory cell stacks and arranged in a three dimensional array.

This application is related to the following US application and has the same patentee and the same inventor.

US Patent No. US Patent No. 9,219,074; Announcement on December 22, 2015; Application No. 14/157,550, application date is January 17, 2014; patent is known as Three-Dimensional Semiconductor Device; The entire disclosure of this patent is incorporated herein by reference in its entirety in its entirety in its entirety in its entirety in

US Patent No. US Patent No. 9,219,073; announced on December 22, 2015; application No. 14/582,848, application date is December 24, 2014; patent is called Parallelogram Cell Design For High Speed Vertical Channel 3D NAND The entire disclosure of this patent is hereby incorporated by reference herein in its entirety in its entirety in its entirety in the the the the the the the the

US patent application, publication number US 2015/0206899; published on July 23, 2015; application number No. 14/582,963, application date is December 24, 2014; patent is known as Twisted Array Design For High Speed Vertical Channel 3D NAND Memory; incorporated herein by reference in its entirety.

U.S. Patent Application Serial No. 14/640,869, filed on March 6, 2015, the disclosure of which is hereby assigned to The full text of the patent is contained in this specification.

U.S. Patent Application Serial No. 14/857,651, filed on Sep. 17, 2015, the disclosure of which is hereby incorporated by reference in its entirety in its entirety in In this manual.

As the critical dimensions of integrated circuit components shrink to the limits of common memory cell technologies, designers are continually looking for ways to stack multiple memory cell planes to achieve greater storage capacity and less. Cost per bit. For example, thin film transistor technology is used in charge trapping memory technology, in Lai, et al., "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, and Jung et al., "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node," IEEE Int'l Electron Devices Meeting , 11-13 Dec. 2006. This document is hereby incorporated by reference in its entirety in its entirety herein in its entirety in its entirety.

Another structure for providing vertical NAND devices in charge trap memory technology is described in Katsumata, et al., Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices," 2009 Symposium The VLSI Technology Digest of Technical Papers, 2009. This document is hereby incorporated by reference in its entirety herein in its entirety in its entirety in its entirety in its entirety in the the the the the the the the the The capture technique creates a memory point on each of the gate/vertical channel interfaces. The memory structure is a column of semiconductor material arranged as a vertical channel of the NAND device, a lower layer select gate adjacent to the substrate, and located The upper top select gate is based; a planar word line layer intersecting the column of semiconductor material is used to form a plurality of horizontal word lines; and a so-called gate all around the cell is formed in each layer.

1 and 2 are a top view and a side view, respectively, showing a tubular column of flash memory cells. Referring to the top view of FIG. 1, a bit line (dashed line 8) is connected to the via conductor 9 and is in contact with the contact pad 10 at the top of the vertical channel column 15. In the drawings, the contact pad 10 shields the core portion of the vertical channel column 15. In the cross-sectional view, a dielectric charge trapping structure including a first tantalum oxide layer 16, a tantalum nitride layer 17 and a second tantalum oxide layer 18 (referred to as an ONO structure), or other cylindrical shell surrounding the semiconductor material is illustrated. The multilayer dielectric charge trapping structure of body 14. The diameter of the vertical channel columnar body 15, that is, the outer diameter of the second tantalum oxide layer 18 of the vertical channel columnar body 15, is indicated by the letter "a". In the upper view of FIG. 1, a series of select line 24 conductive strips in contact with the second tantalum oxide layer 18 of the dielectric charge trapping structure are illustrated to form a series select gate of the vertical channel column 15.

Referring to the side view of FIG. 2, the contact pad 10 covers the core portion of the vertical channel column 15 including the columnar housing 14 of semiconductor material. The semiconductor material columnar housing 14 extends vertically through the plurality of conductive strips. These multilayer conductive strips comprise conductive strips as tandem select lines 24, multilayer strips constructed as conductive strips of word lines (WLs) 20-23, and ground select lines 25 conductive strips on the bottom layer. In the present embodiment, the electrically conductive semiconductor material columnar housing 14 has an insulating core 11 therein. In another embodiment, the inner core of the cylindrical housing has a metallic material. In another embodiment, the electrically conductive semiconductor material is a solid cylindrical semiconductor material. A dielectric charge trapping structure or other multilayer dielectric charge trapping structure including, for example, a first tantalum oxide layer 16, a tantalum nitride layer 17, and a second tantalum oxide layer 18 (referred to as an ONO structure) surrounds the semiconductor material columnar housing 14. The diameter of the columnar body 15, that is, the outer diameter of the dielectric layer on the outer edge of the columnar body 15, is indicated by the letter "a". The second tantalum oxide layer 18 on the outer edge of the dielectric charge trapping structure is in contact with a conductive strip (layer) constructed to serve as the word line 20-23, thereby forming a memory cell at the intersection of the two. In this embodiment, the conductive strips on the bottom layer are constructed to serve as ground select lines 25 while also being in contact with the second tantalum oxide layer 18 of the dielectric charge trapping structure. In some embodiments, the dielectric material between one or both of the tandem select line 24 and the ground select line 25 is different from the dielectric material of the dielectric charge trapping structure.

As shown in the upper view of FIG. 1, the tandem selection line conductive strips 24 and the columnar bodies 15 are intersected. Thus the tandem select line conductive strip 24 is a wraparound gate. Each of the conductive strips located below the tandem select line conductive strips 24 as word lines 20-23 also intersects the columnar body 15, each of which is also a wraparound gate. The combination of the frustum of the columnar body 15 and the conductive strips 20-23 forms a memory cell at each level of the conductive strips of the word lines 20-23. The ground select line conductive strip 25 located below the word line 20-23 conductive strip also intersects the columnar body 15.

Thus, a NAND string is formed on the current path through the column of semiconductor material between the bit line (BL) 8 and the land. Wherein, the connection region (GND, not shown) is located below the columnar body of the semiconductor material.

Figure 3 is a diagram showing a three-dimensional semiconductor component. It comprises a multi-layered word line 20-23 conductive strip stack over a substrate (not shown), a plurality of columnar bodies 15 extending through the stack. Each of the columns 15 includes a plurality of channels of a plurality of series memory cells and a plurality of string selection lines 24. These channels are located at the intersection of the word line 20-23 conductive strip and the columnar body 15. The tandem select line 24 conductive strips are then located in the tandem select line layer above the traces of the word lines 20-23. Each of the tandem selection line conductive strips 24 respectively intersects the columnar bodies 15. The intersection of each of the columnar bodies 15 and the conductive strips of the string selection line 24 defines a series of 15 column select gates (SSGs). The structure also includes a level of ground select line conductive strips 25A and 25B that are parallel substrates and formed under conductive strips 20-23. A common source line (CSL) 27 is formed at a level below the ground select line conductive strips 25A and 25B. The intersection of each of the columns 15 and the ground selection line conductive strips 25A and 25B defines a grounded selection gate (GSG) of the columnar body 15. The plurality of columnar bodies 15 of the ground selection line conductive strips 25A are shared by the columnar bodies 15 and can be coupled to the common source line 27, and can be selectively operated by the ground selection line conductive strips 25A. Similarly, the plurality of columnar bodies 15 of the ground selection line conductive strips 25B are shared by the columnar bodies 15 and can be coupled to the common source line 27, and can be selected and operated by the ground selection line conductive strips 25B. This structure also includes word lines 8 that are parallel to the substrate and formed in a hierarchy above the series select line conductive strips 24. Each of the word lines 8 is located above a columnar body 15; and each of the columnar bodies 15 is located below one of the word lines 8. The columnar body 15 can be constructed in the manner described in Figs. 1 and 2. In this configuration, a plurality of columnar bodies 15 coupled to a single tandem select line conductive strip 24 are arranged in a straight line along the direction of the vertical bit line 8; and each bit line includes a columnar body 15. Each of the bit lines is coupled to one of the columnar bodies 15 of the group of columns.

As shown in FIG. 3, the three-dimensional semiconductor device is typically arranged to have a stepped contact structure connected to the word line conductive layer. Deep etching is performed on this structure to form a plurality of contact structures for connecting the conductive layer to the upper metal interconnect. In a typical design, the number of rows of columns in a block is at least as many as the number of contact structures; the memory layer is also. See, for example, Komori, Y., et al. , "Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device," IEEE Int'l Electron Devices Meeting, pp. 1-4, 15-17 Dec 2008. This document is hereby incorporated by reference in its entirety in its entirety herein in its entirety in its entirety.

Here, the layout of the memory structure can be extended to have an overhead connector connected to the conductive stack, and a vertical channel column having a relatively large diameter. Among them, the top conductive structure is a limitation condition of the three-dimensional memory bit density.

Therefore, there is a need to create a robust solution that reduces the negative impact of increasing bit density while increasing the bit density of the three-dimensional memory structure. Provide better wafer yield, higher density, more efficient circuits, components and systems.

A memory component is described that includes a vertical NAND string array positioned below a set of bit lines. This bit line extends along one bit line. The tandem select lines and word lines of the vertical NAND string include a plurality of conductive strips built into the stacked plurality of conductive layers. The NAND strings located in the array extend through the plurality of conductive strips. A NAND string located in a given subset of the array page is coupled to a conductive strip of a corresponding single string select line. A subset as used herein refers to a page that contains a plurality of NAND strings. A plurality of NAND strings in each page are placed in a grid. The grid is offset from the direction of the bit line by an off-angle. The conductive strips of the tandem selection line have sides that are curved sides. The conductive strips of the plurality of word lines and the conductive strips of the ground select lines may have curved sides. The curved sides can increase the layout density of the NAND string blocks. Wherein, the NAND serial block includes a plurality of pages arranged in an offset from the grid.

Multiple NAND strings in each page are placed in a regular grid. This regular grid is obliquely offset with respect to the direction of the bit line. The regular grid located in each of the pages has a regular pitch. Wherein, the regular spacing points away from the direction of the bit line. A regular grid in adjacent first and second pages can off-set this regular spacing. This offset can occur in either or both of the bit line direction and the vertical bit line direction.

The above summary is intended to provide a basic description of the various aspects of the invention, and is not intended to limit the scope of the invention. It merely presents some concepts in a simplified manner as a prelude to the disclosure, and a more detailed description will be presented later. The specific aspects of the invention will be described in the following claims, description and drawings.

One of the solutions for increasing the bit density of a three-dimensional memory structure while reducing the negative impact of increasing the bit density has been described in the present specification and describes the "twisted array" structure. U.S. Patent Application Serial No. US 2015/0206899, which is incorporated herein by reference. As described in more detail herein, in a memory device having a conductive layer stack structure of a plurality of parallel substrates, each vertical substrate column has a plurality of serially connected memory cells between the column and the conductive layer. At the intersection. A plurality of serial select lines (SSL) are located above the conductive layer. Each column and a series of select lines define a series select gate. A plurality of bit lines are located above the tandem selection line. A plurality of columns in the plurality of columns are arranged in a regular grid. Where this grid is rotated relative to the bit line. This grid may have square, rectangular or diamond shaped unit cells and may be offset from the bit line by an offset angle θ. Where tan(θ)=±X/Y, X and Y are mutually prime integers. The tandem selection line has a sufficient width to intersect with two columns located on one side of a unit cell; or with all columns in the unit cell; or has a sufficient width and adjacent cells Two or more columns intersect. This ratio allows for the setting of higher density bit lines, which in turn achieve higher data rates due to the increase in parallel operations. This can also reduce the number of serial selection lines, reduce the read distance, reduce power consumption, and further increase the data rate by reducing the cell package capacitance.

Another solution to the above problem is described in the present specification, which is incorporated herein by reference in its entirety by reference to the "parallelogram cell" structure, also referred to herein as a twisted array, U.S. Patent Application Serial No. Discussed in 9,219,073. As described in more detail herein, a plurality of columns in a plurality of columns are not arranged in a rotating grid, but are arranged in a regular grid having a non-rectangular parallelogram. Among them. These columns can be arranged and define a certain number of parallel column lines. These columnar lines intersect the bit lines and have an acute angle θ > 0 °. Each columnar line has n columns, n>1. Each of the columns intersects a common string selection line. With this twisted array design, this parallelogram array design also allows for the placement of higher density bit lines, with higher data rates achieved by the addition of parallel operations. This also reduces the number of serial select lines, thereby reducing interference, reducing power consumption, and further increasing the data rate by reducing the cell package capacitance.

Among the above two solutions, the reason why this technique benefits is in part because the tandem selection line has a significantly wider width relative to the bit line in the conventional array structure. However, this approach has its limits. Because a string selection line and a bit line must define a unique column. If the width of the string selection line is too wide in the direction of the strip line, more than one column below the single bit line will also be located below one of the string selection lines, resulting in address conflict (addressing) Conflict). If the width of the tandem selection line in the direction of the strip line is too narrow, the portion where some of the bit lines intersect with the tandem selection line does not have a columnar body intersecting therewith.

The layout of the tandem select line conductive strips is generally perpendicular to the bit line, and the conductive layer stack structure disposed below the tandem select line and disposed in a twisted array layout in an off-grid grid must be considered close to the tandem select line side The process and efficiency limits of the columnar sides. Therefore, an overhead structure coupled to a single tandem select line conductive strip in a columnar block layout is introduced to account for the aforementioned process and performance limits.

4A and 4B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. The upper view shows the conductive strips 24A and 24B as adjacent string select lines disposed in the respective column blocks of the twisted array. Fig. 4B is a cross-sectional side view showing the zigzag lines taken along the line A-A' and B-B', i.e., the upper view shown in Fig. 4A. The cross-sectional structure of the line A-A' shown in Fig. 4B is adjacent to the cross-sectional structure of the line B-B'. The memory component includes a conductive layer stack structure overlying the integrated circuit substrate and interleaved with a plurality of insulating layers. The conductive layer stack structure includes at least one bottom conductive layer having a ground select line 25, a plurality of intermediate conductive layers for the word lines 20-23, and a top conductive layer having a string select line 24. The columnar body 15 intersects with the conductive layer stack structure.

Although only four conductive layers are shown as the word lines 20-23. However, in other embodiments, the number of layers of word lines can be any number. For example, 8 layers, 16 layers or 32 layers. Likewise, the number of columns, string select lines, ground select lines, and/or ground lines in different embodiments may vary.

The columnar body 15 in the vertical channel structure is perpendicular to and intersects with the plurality of conductive layers in the conductive layer stack structure. A plurality of memory cells are respectively disposed on the interface region between the plurality of conductive layers of the conductive layer stack structure and the side intersections of the plurality of layer pillars 15.

Referring to the layout diagram shown in FIG. 4A, the columnar block that intersects the tandem selection line conductive strip 24A and the columnar block that intersects the tandem select line conductive strip 24B form a twisted array. . In this embodiment, each block of the warped array contains a regular grid. Each regular grid has two lateral dimensions R1 and R2, respectively rotated by an acute angle offset angle θ and an obtuse angle offset angle φ with respect to the bit line direction 34; and in two lateral dimensions R1 and R2 With lateral spacing. Therefore, the bit line pitch described below is smaller than the lateral pitch of the columnar body at the obtuse angle deviating from the transverse dimension R2 of the angle φ; and is also smaller than the lateral spacing of the columnar body at the obtuse angle deviating from the transverse dimension R1 of the angle θ. In a preferred embodiment, the blocks along the same bit line of the plurality of bit lines in the plurality of blocks have a central acute angle deviation angle θ and an obtuse angle deviation angle φ. In other embodiments, the implementation of the acute angle offset angle θ and the obtuse angle offset angle φ may vary from block to block. In other embodiments, there are different numbers of cylinders, regular grids used to define the position of the cylinders, and/or different numbers of bit lines.

As shown, the first paged columnar body intersecting the tandem selection line conductive strips 24A, including the first outer edge subset of the columnar body, is disposed on the first wavy line 35A. The first wavy line 35A intersects the bit line direction due to the off angle. The tandem select line conductive strip 24A has a first side 33A between the tandem select line conductive strips 24A and 24B and a wave profile along the first wavy line 35A.

The second paged columnar body, including the columnar body of the first outer edge subset, is disposed on the second wavy line 35B. The second wavy line 35B intersects the bit line direction due to the deviation angle of the approximately orthogonal direction. The tandem select line conductive strip 24B has a second side 33B between the tandem select line conductive strips 24A and 24B and a wave profile along the second wavy line 35B. The first wavy line 35A and the second wavy line 35B are formed by straight line segments between adjacent columns in the outer edge subset of the individual blocks. The first side edge 33A and the second side edge 33B extend equidistantly from the straight line segment along the wavy line. In other embodiments, the wave shape of the conductive strip is not formed by a straight line segment, but may be formed by a curved line segment or a combination of a straight line segment and a curved line segment, along the outer cylindrical body. The defined wavy lines extend in a less rigid form. The appearance of the opposite sides of the series select line conductive strips 24A and 24B extends along the wavy lines 36A and 36B. For example, the first wavy line 35A has a plurality of crests (e.g., positions at the columnar body 35Ac) and troughs (e.g., at the position of the columnar body 35At) with respect to a line perpendicular to the bit line. In this figure, the peak is the rightmost vertex of the line. In this figure, the trough is the leftmost lowest point (nadirs) of the first wavy line 35A. Similarly, the second wavy line 35B has a plurality of wave fronts (e.g., positions at the columnar body 35Bc) and troughs (e.g., at the position of the columnar body 35Bt). In the figure, the peak is the vertex of the rightmost side of the second wavy line 35B. In the figure, the trough is the lowest leftmost point of the second wavy line 35B. The two-wave columnar bodies 35At and 35Bt located on the adjacent sides of the two conductive strips are arranged along the bit line direction and may overlap the same bit line. The crest columns 35Ac and 35Bc located on the adjacent sides of the two conductive strips are arranged along the bit line direction and may overlap the same bit line. In other embodiments, the peaks and troughs may not be arranged in the manner described above.

The sides of the conductive strips (including the tandem select line conductive strips 24A and 24B) follow the sides of the columnar wavy line. In the present description, the sides may be curved or generated at peaks or troughs. Intermittent or uninterrupted, as shown in jagged shape. Each column on the wavy line has a minimum distance from the side of the conductive strip in the direction of the bit line, thereby at least sufficient to meet manufacturing and performance tolerances so that the conductive strip reliably surrounds the column on the wavy line And the distance range above this minimum must be less than the distance between the valley and the peak in the direction of the bit line. When the shape of a line segment or side is not a straight line, the line segment or the side edge is said to be "wavy". In an embodiment, the shape of the wavy lines or sides may be curved. In another embodiment, the shape of the wavy line or side is a concatenation of a plurality of lines. Therefore, although the individual segments are straight lines, their unions are still not straight.

Such a wave shape consisting of one or more curved lines and/or string segments, the angle formed by any two line segments from the side will not be 180°.

In the embodiment illustrated in FIG. 4A, the outer edge columnar body along a given positioning element line in one block is smaller than the other columnar body located on the bit line to the side of the string selection line. Also close to this bit line. In this embodiment, the wave shape extends along a wavy line in an equidistant manner. Small process parameters up to a few nanometers are expected.

The tandem select line conductive strips 24A and 24B have wavy shaped sides 33A and 33B extending along the wavy lines 35A and 35B of the columnar body.

The wavy lines 35A and 35B and the bit line direction 34 intersect at a non-perpendicular angle. Figures 6 through 11 illustrate bit lines extending along the bit line direction 34.

Referring to FIG. 4B, an insulating dielectric layer 32 separates each layer of conductive strips from each other. For example, the conductive strips as word lines 20-23 are separated from one another.

The conductive strips of the conductive layer stack structure and the sides of the tandem select line conductive strips 24A and 24B may have a wavy shape. The portion of the three-dimensional memory element having the side of the wavy shape has a word line, a string selection line, a ground selection line, and a grounded common source line or ground line.

The vertical channel structure of the columnar body 15 includes a semiconductor material suitable as a channel for the memory member, such as germanium (Si), germanium (Ge), germanium (SiGE), gallium arsenide (GaAs), tantalum carbide (SiC), and / or graphene (Graphene). The memory component in the memory component includes a charge storage structure, such as a dielectric charge trapping structure as is known in flash memory technology, such as oxide-nitride-oxide (ONO). Structure, oxide-nitride-oxide-nitride-oxide (ONONO) structure, 矽-矽 oxide-tantalum nitride-矽 oxidation Silicon-oxide-nitride-oxide-silicon (SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon) BE-SONOS) structure, tantalum nitride-aluminum oxide, silicon nitride, silicon oxide, silicon (TANOS) structure and a metal high dielectric constant energy gap Metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS).

The word line stack structure, such as the stacked structure including the word line conductive strips 20-23, intersects with the columnar blocks in the overall structure to define a memory block. Therefore, in order to read data from a particular block of memory, the control circuitry must activate a word line, such as conductive strip 20, to select a memory block and a particular level in the block. And further activate a serial selection line 24 to select a particular columnar page. At the same time, the ground selection gate of the ground selection line 25 is activated, and at least the block selected by the word line is selected. A memory pack page is read in parallel to a page buffer (not shown) via a bit line coupled to the top of the selected column header. (The term "activation" as used herein refers to the application of a specific bias to the connected memory cell or switch. This bias can be high or low, depending on the memory design and implementation. Operation content). Depending on the manufacturing specifications and design, the page buffers can be coupled to multiple memory cells via different sets of bit lines, and can store more data than one page from a single block.

5A and 5B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. The upper view shows the word line conductive strips 20 having wavy shaped sides. The structures illustrated in FIGS. 5A and 5B are substantially the same as those illustrated in FIGS. 4A and 4B. However, FIG. 4A is a top view of the tandem select line conductive strips 24A and 24B separated by an insulating dielectric layer 32, and FIG. 5A is a top view of the conductive strips of the word line 20. Fig. 5A is a side view showing the cross-sectional structure taken along line 39 of Fig. 5B.

The side edges of the word line conductive strips, such as the side edges 37A and 37B, have a wavy shape extending along the columnar body wavy lines 35A and 35B. The opposite sides of the word line conductive strips extend along the columnar wavy lines 36A and 36B.

Figure 6 is a top view (rotating 90° with respect to Figures 4A and 5A) showing a set of parallel bit lines 8 electrically coupled to the top of the column. Among them, the columnar body intersects the tandem selection lines 115 and 215 having the linear side edges 163, 164, 263, and 264, respectively. Among the series selection line levels having the bit line level below the bit line 8, the series selection lines 115 and 215 intersect the column. Each of the columnar bodies 15 has two corresponding distances, which are the distance from the columnar body to the top side of the tandem selection line, and the other is the distance from the columnar body to the bottom side of the tandem selection line. The top side 163 of the tandem select line 115 and the bottom side 264 of the tandem select line 215 are separated from one another by a distance S260.

In the embodiment illustrated in the figures, the following four shorter distances, which are equal to or within a range of a few nanometers of process parameters, represent a narrower process window: (i) columnar body The distance from 141 to the top side edge 163 of the tandem selection line 115, (ii) the distance from the columnar body 143 to the top side edge 163 of the tandem selection line 115, and (iii) the columnar body 242 to the tandem selection line 215 The distance from the bottom side 264 and (iv) the distance from the columnar body 244 to the bottom side 264 of the tandem selection line 215. The columnar body here is shown by a short dashed circle.

In the embodiment illustrated in the figures, the following four longer distances, which are equal to or within a range of a few nanometers of process parameters, represent a wider process margin: (i) columnar 142 to tandem The distance from the top side 163 of the selection line 115, (ii) the distance from the columnar body 144 to the top side edge 163 of the tandem selection line 115, and (iii) the bottom side 264 of the columnar body 241 to the tandem selection line 215. The distance and (iv) the distance from the columnar body 243 to the bottom side edge 264 of the tandem selection line 215. The columnar body here is shown by a long dashed circle.

Different lengths and distances mean different process margins. Different process margins are due to the rotating columnar grid. Therein, the columnar system is located on tandem select lines 115 and 215 having straight side edges and including top and bottom sides. The string selection line 115 and the string selection line 215 are separated from each other by a distance S260. When the rotation axis of the rotating mesh is not parallel to a string selection line, different process margins are created.

7 and 6 are similar, and the same component symbols are used to represent the same components. However, compared to the linear side edges 163, 164, 263, and 264 of the tandem select line 115 and the tandem select line 215 illustrated in FIG. 6, the tandem select line 315 and the tandem row illustrated in FIG. Selection line 415 has sides 363, 364, 463, and 464 that are wavy.

The sides of the string selection line 315 and the string selection line 415 are parallel to the wavy lines on the regular grid. The grid is used to locate the position of the columnar body in each of the tandem selection lines. The outer edge columnar body in the tandem selection line is the columnar body closest to the side of the corresponding tandem selection line among the tandem selection lines with respect to the other columnar body in the tandem selection line. The wavy lines 361, 362, 461, and 462 of the columnar body 15 are defined by the connected partial grid lines. The side lines of the string selection line 315 and the string selection line 415 having a wave shape extend along the wavy lines 361, 362, 461, and 462. The partial grid lines 361, 362, 461, and 462 intersect the bit line direction of the bit line 8 at a non-perpendicular angle. For example, the top side of the tandem select line 315 is parallel to a set of grid lines 361 that are used to connect the top of the tandem select line 315. In another embodiment, the top side of the tandem select line 415 is parallel to a set of gridlines 462 that are used to connect the bottom pillars in the tandem select line 415. In this embodiment, one line segment extends along the other line segment in an equidistant manner. Small process parameters up to a few nanometers are expected.

The tandem select lines 315 and 415 are generally relatively narrow, as shown in FIG. 7 with tandem select lines 315 and 415 having wavy shaped sides 363, 364, 463, and 464, which are straighter than those depicted in FIG. The tandem selection lines 115 and 215 of the sides 163, 164, 263, and 264 (as depicted by the dashed lines in Figure 7) are also narrower. The string selection line 115 and the string selection line 215 are separated from each other by a distance S260. The tandem selection line 315 and the tandem selection line 415 are separated from one another by a distance S'360 that is different from the distance S260. In the present embodiment, the distance S'360 is greater than the distance S260. The reason for the wider S'360 is that the additional tandem selection line material is removed, leaving the outer rim column 15 with a larger process margin. After removing the additional tandem selection line material, the outer edge cylinders 15 that are closer to the sides of the tandem selection line than the other columns generally have the same and narrower process margin.

In the illustrated embodiment, the trough columnar body on the wavy line 461 and the trough columnar body on the wavy line 361 can overlap with and be connected to the same bit line (eg, , in the figure, the number of the 56 bit lines is the 22nd bit line). A crest column on the wavy line 361 and a crest column on the wavy line 461 can overlap with the same bit line and be connected to the bit line (eg, the number in the 56 bit lines in the figure) Article 18 bit line). The structure of the columnar mesh here is different from that shown in Fig. 4.

Figure 8 is a top view, similar to Figure 7, showing a set of parallel bit lines 8 electrically coupled to the top of the column. Therein, the columnar body intersects the tandem selection line having the wavy side, and the tandem selection lines 315 and 415 and the mesh of the columnar body are moved so as to be closer to each other along the bit line direction. As a result, the grid pitch of the string selection line 315 is shifted from the grid pitch of the string selection line 415 along the bit line direction.

In Fig. 8, after moving the string selection lines 315 and 415 closer together, the string selection lines 315 and 415 are separated from each other by a narrower distance S" 460 than the distance S'360 depicted in Fig. 7. The direction of movement corresponds to moving the string selection lines closer to each other along the direction of the bit line of the bit line 8. Since the moving direction has only a pure vertical movement, the series selection lines 315 and 415 are relatively opposite before and after the vertical movement. The columnar distribution of the bit lines is the same. The characteristics of each column distribution are each string selection line corresponding to each bit line, and the number of columns is equal. The relative positions of the columns in the line selection lines 315 and 415 are also the same. Among the embodiments illustrated in the drawings, as shown in Fig. 7, the troughs on the wavy line 461 and A trough columnar body on the wavy line 361 can overlap the same bit line and be connected to the bit line (for example, the number 22 bit line in the 56 bit lines in the drawing). The crest column on the 361 and the crest column on the wavy line 461 can be The same bit line overlaps and is connected to the bit line (eg, the numbered 18th bit line in the 56 bit lines in the drawing).

However, uneven regions and process margins are still displayed in the vicinity of the peaks and troughs. In region 470, tandem select lines 315 and 415 are separated from one another by distance S" 460.

Figure 9 is a top view, similar to Figure 8, showing a set of parallel bit lines 8 electrically coupled to the top of the column. Wherein the columnar body intersects the tandem selection line having wavy sides, and the tandem selection lines 315 and 415 and the grid of the columnar body are vertically shifted (in the direction of the bit line) and horizontal (vertical position) The direction of the line moves) to bring them closer together. The direction of horizontal movement corresponds to moving the string selection lines in the direction of the bit line along the vertical bit line 8 to bring them close to each other. An embodiment of horizontally moving the size includes moving the entire series of select lines along the direction of increasing the bit line number or decreasing the bit line number, moving the displacement amplitude of 1, 2 or 3 bit lines. In other words, if the overall serial selection line is moved along the direction of increasing the bit line number or decreasing the bit line number, the displacement amplitude of the 1, 2 or 3 bit lines is moved, and the columnar distribution of the different series selection lines can be Match each other.

Among the layouts depicted in FIG. 9, the trough columns on the adjacent side edges 563 and 664 of the two conductive strips are arranged along the bit line direction and are aligned by the same bit line (for example, In the formula, the number of the 56 bit lines is covered by the 25th bit line). The crest columns 35Ac and 35Bc located on adjacent side edges 563 and 664 of the two conductive strips are arranged along the bit line direction and are aligned by the same bit line (for example, in the 56 bit lines in the drawing) No. 21 bit line). In other embodiments, the troughs and crests may not be arranged in this manner.

As a result, the separation distance of the series-selective line conductive strips and the area where the process margin is uneven are substantially reduced or even eliminated. Since the moving direction is the horizontal direction, the overall columnar body distributions of the tandem selection lines 315 and 415 before the horizontal movement are different from the overall columnar body distribution of the tandem selection lines 315 and 415 after the horizontal movement. In the columnar distribution of the different tandem select lines, the columns of the different tandem select lines 515 and 615 have sides 563, 564 with respect to the tandem select lines 515 and 615 along different bit lines. , 663 and 664 different relative positions. In various embodiments, the distance S"' 660 used to separate the tandem selection lines 515 and 615 after horizontal movement may be equal to, less than, or greater than the distance S used to separate the tandem selection lines 315 and 415 prior to the horizontal movement. "460.

SSL _x T _y represents the distance between the column body coupled to the bit line y and the top side of the string selection line x; SSL _x B _y represents the column and string coupled to the bit line y The column selects the distance between the bottom sides of the line x. For example, SSL ₁ B ₂₄ 642 represents the distance between the columnar body coupled to bit line 24 and the bottom side of tandem select line 1. Embodiments of different columnar distributions in different series of select lines are represented as follows: (i) SSL _a T _n ≠ SSL _a+1 T _n For example, SSL ₁ T ₃₉ 643 ≠ SSL ₂ T ₃₉ 542 (ii SSL _a B _m = SSL _a+1 T _m For example, SSL ₁ B ₂₁ 641 = SSL ₂ T ₂₁ 541

A method of fabricating a memory device includes the steps of forming a vertical NAND string array below a set of bit lines such that the bit lines extend along a one-bit line direction. And forming a string select line and a word line of the NAND string such that the string select line and the word line comprise conductive strips. The method includes constructing a vertical NAND string in the array to extend through the multi-conductive layer of the conductive strip, into the NAND string column, and coupling the NAND string in a given page to a given page. Serial selection line. The NAND strings in each page are placed in a grid. The grid is offset from the direction of the bit line by an offset angle. This method includes forming curved sides on the conductive strips of the tandem selection lines to make the pages more closely packed. The method includes forming curved sides on the conductive strips of the plurality of word lines. The NAND string in the array can also include a ground select switch located in the conductive strip layer. The method includes forming curved sides on the conductive strips of the plurality of ground selection lines.

As shown in Figures 8 and 9, the method includes placing each paged NAND string in a regular grid such that the regular grid is obliquely offset from the bit line direction and is located at each The regular grid in the page has a regular spacing, where the regular spacing points away from the bit line direction. And offsetting the regular spacing of the regular grids in the adjacent first and second pages. This offset can occur in either or both of the bit line direction (as shown in Figure 8) and the vertical bit line direction (as shown in Figure 9).

Figure 10 is similar to Figure 7 and shows the area saved using a tandem selection line with wavy sides.

For example, a cross-hatched region 780 represents the area saved by the tandem select lines 315 and 415 having wavy sides compared to the tandem select lines 115 and 215 having the original straight sides. The area that is saved is the portion saved by the pitch 769 of the tandem selection lines, that is, (i) the distance S760 used to separate the tandem selection lines 115 and 215 having the straight sides and (i) The distance difference h764 between the distances S' 762 of the tandem selection lines 315 and 415 having the wavy sides is separated.

The distance difference h764 is approximately the distance difference along the direction of the bit line, that is, the direction of the side of the 3-4-5 right triangle 782. In the present embodiment, the length of the side of the 5th of the 3-4-5 right triangle 782 is equal to the diameter of the memory cell. The phase is located at the side length of the 3-4-5 right triangle 782, h 764 = (3/5) × a. Therefore, the area that is saved by changing the straight side of the tandem selection line to the wavy side corresponds to the distance from the series selection line in the direction of 769, or h 764 = (3/5 ) × a. This approximate result is from the slight difference between the directions q 766 and q' 768. The direction q 766 parallel bit line 8 is used to measure the distance between the string selection lines 315 and 415. The direction q' 768 is the outer edge side of the vertical tandem selection lines 315 and 415 offset for measuring the distance between the sides of the outer edge.

Figure 11 is similar to Figure 6, showing the area saved using a tandem selection line with wavy sides. The table below shows the savings in area calculated using the relevant dimension examples.         <TABLE border="1" borderColor="#000000" width="_0004"><TBODY><tr><td> diameter of the column </td><td> a </td><td> 160 nm </td></tr><tr><td> Distance from the outer edge of the column to the side of the tandem selection line</td><td> b </td><td> 25 nm </td> </tr><tr><td> Separating the distance of the string selection line</td><td> c </td><td> 180 nm </td></tr><tr><td> Select the spacing of the lines</td><td> g </td><td> 1158 nm </td></tr><tr><td> the spacing saved </td><td> h </td> <td> 96 nm </td></tr><tr><td> area saved </td><td> h/g </td><td> 8.3% </td></tr>< /TBODY></TABLE>

The diameter "a" of the columnar body is shown in Figs. 1 and 2.

The distance "b" from the outer edge column to the side of the tandem selection line is shown on both sides of the tandem selection line 115 of Fig. 11.

The distance "c" separating the string selection lines is shown in Fig. 11 to separate the string selection lines 115 and 215.

The distance "d" approximates the distance along the bit line direction, corresponding to the length of the side 4 of the 3-4-5 right triangle 890. The length of the side of the 3-4-5 right triangle 890 is equal to 6 units of the memory cell diameter a or 6 × a. According to the relative length of the 3-4-5 right triangle 890, the distance d = (4/5) × 6 × a.

The distance "e" is the sum of the memory cell diameter a of the distance d and an extra unit, or the sum of the distance d and the memory cell diameter a" of the half unit located on both sides of the distance d, e = d + a.

The distance "f" is the sum of the distance e and the distance "b" on both sides, f = e + 2b.

The distance "g" is the sum of the distance e and the distance f.

In one embodiment, the use of wavy shaped sides saves 8.3% of the area. In other embodiments, at least one or more of the values of a, b, c, d, e, f, g, and h are different from the present embodiment.

12A and 12B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. Fig. 12A is a top view of Fig. 12B. Figure 12B is a cross-sectional side view showing the ground selection line 26A and the ground selection line 26B passing through the lower-level conductive strips through the section line 40. The structures illustrated in FIGS. 12A and 12B are substantially the same as those illustrated in FIGS. 4A and 4B. However, FIGS. 12A and 12B divide the ground selection line 25 illustrated in FIGS. 4A and 4B into a plurality of ground selection lines 26A and 26B that can be respectively turned on. As depicted in Figure 12A, both ground selection lines 26A and 26B have the appearance of a wave shape.

In Fig. 12A, the sides of the ground selection line, such as the sides 38A and 38B of the ground selection lines 26A and 26B, have a wave-like appearance that extends along the columnar wavy line 35.

13A and 13B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. Fig. 13A is a top view of Fig. 13B. Fig. 13B is a side view showing the cross-sectional structure taken along the line 41. The structures illustrated in FIGS. 13A and 13B are substantially the same as those illustrated in FIGS. 4A and 4B. However, FIGS. 13A and 13B also illustrate a plurality of ground lines (or common source lines) 41/42 located below the ground selection line 25. The upper layer 41 of the ground line is an n-type or p-type heavily doped polysilicon layer having a doping concentration of about 10 ²⁰ /cm ³ . The underlying layer 42 of the ground line is a metal, such as tungsten (W), a layer. As depicted in Figure 13A, each of the ground lines 41/42 has a wavy appearance.

The sides of the ground line, such as the sides 43A and 43B of the ground line 41/42, have a wave-like appearance that extends along the outer edge columnar wavy lines 36A and 36B.

Figure 14 is a simplified block diagram of an integrated circuit memory of a three-dimensional vertical gate memory array having wavy sides as described herein.

Integrated circuit 975 includes a memory array 960 on a semiconductor substrate. The memory array 960 herein is implemented in a block structure having sides of a non-linear or wavy shape. For example, any one of the string selection line, the word line, the ground selection line, and the ground line has a side of a wavy shape. A row detector 961 comprising a high voltage driver is coupled to the plurality of word lines 962 and is arranged along a row in the memory array 960. A column decoder 963 is coupled to the plurality of bit lines 964 (or the string select lines as previously described) and is configured along the columns in the memory array 960 for use from the memory. The memory cells in array 960 read data or write data to memory cells. A plane decoder 958 is coupled to a plurality of planar layers in the memory array 960 via a plurality of string select lines 959 (or bit lines as previously described). The address is provided by a bus to a column decoder 963, a plane decoder 958, and a row decoder 961. The perceptual expander/data input structure 966, in the present embodiment, is coupled to the column decoder 963 via the data bus 967. Data may be provided to the perceptual amplifier/data input structure 966 via data input line 971 from input/output ports on integrated circuit 975 or other sources internal or external to integrated circuit 975. In the embodiment illustrated in the drawings, the integrated circuit 975 can include other circuits 974, such as general purpose processors or special purpose processors, or supported by a NAND flash memory cell array to provide system integrated chip functions. (system-on-a-chip functionality) combination module. Data may be provided from the perceptual amplifier/data input structure 966 to the input/output ports on the integrated circuit 975, or other data destinations internal or external to the integrated circuit 975 via the data input line 972.

The controller, in this embodiment, is implemented with a biasing arrangement state machine 969 that controls the application of bias arrangement supply voltages provided by the voltage supply line or supply 968, such as reading and writing. , erase, read verify, and write verify voltage. Such a controller can be implemented using special purpose logic circuitry as is known in the art. In another embodiment, the controller includes a general purpose processor for executing a computer program to control the operation of the components in the same integrated circuit. In yet another embodiment, the controller can be implemented using a combination of special purpose logic circuitry and general purpose processors.

The biasing arrangement state machine 969 is configured to perform a memory operation including reading, writing, and erasing, such as by applying a read bias to a selected one of the plurality of word lines and using The signal of the serial selection line selects a page for reading.

The memory array 960 can include charge trapping memory cells to store a plurality of bits for each memory cell by establishing multiple levels of writing corresponding to different amounts of charge storage. Among them, different charge storages can establish different threshold voltages of memory cells.

It can be seen that the top conductive structure of the adjacent blocks of the three-dimensional vertical gate memory element is small. In a "twisted" columnar array, the vertical column intersects the horizontal tandem selection line and the word line and is arranged at the intersection of the rotated regular grid. The outer edge cylinders in the columnar array are placed on the wavy line. The sides of the three-dimensional NAND array structure have a wavy appearance that extends along the wavy lines of the columnar array. For example, the tandem select line, the word line, the ground select line, and the ground line have sides of a wavy shape that extend along the wavy line of the columnar array. The wavy lines of the columnar array and the wavy sides of the string select lines, word lines, ground select lines, and ground lines eliminate excess material on the sides of the three-dimensional NAND array structure and reduce the top conductive structure.

Different embodiments of the invention are applicable to memory elements formed on a substrate. This memory element includes a three-dimensional memory element having a vertical channel structure.

A three-dimensional memory element having a vertical channel structure comprising a stacked structure of a plurality of conductive layers of a plurality of word lines, a plurality of columns, a plurality of series of column selection lines on the plurality of conductive layers, and a plurality of lines along the bit line direction Extends and is located on the bit line above the tandem selection line.

Each of the columns includes a plurality of memory cells connected in series with each other at an intersection of the columnar body and the plurality of conductive layers. In some embodiments, the plurality of columns in the plurality of columns are arranged on a regular grid. This regular grid has a plurality of horizontal dimensions.

In some embodiments, the tandem selection lines respectively intersect a subset of the columns, and the subsets described herein represent one page. The intersection of one of the plurality of columns and one of the plurality of string selection lines defines a tandem selection gate of the column.

A plurality of outer edge columns in the plurality of columns are adjacent to sides of the plurality of string selection lines. A plurality of outer edge columns in the plurality of columns are arranged to form a wavy line.

In an embodiment of the present technology, each of the series selection lines has a side of a wave shape extending along a wavy line in which a plurality of columnar bodies are arranged.

In an embodiment of the present technology, each of the word lines has a side of a wavy shape extending along a wavy line in which a plurality of columns are arranged.

In an embodiment of the present technology, the ground selection line is located below the layer of the multilayer conductor layer stack used as the word line. The ground selection line has a wavy side and extends along a wavy line of a plurality of columns.

In an embodiment of the present technology, the grounding wire is located above the substrate and underneath the stacked structure of the multilayer conductor layer used as the word line. The grounding wire has a wavy side and extends along a wavy line of a plurality of columnar bodies.

In an embodiment of the present technology, a subset of word lines intersecting a plurality of columns in a plurality of word lines, the columns further intersecting the first series selection line, each of the subsets A word line has a distance between (i) the columnar body closest to the second side of the first string selection line and (ii) the second side of the first string selection line. This first distance is equal to the minimum of the distance.

In an embodiment of the present technology, the first bit line of the plurality of bit lines extends from the end of the first bit line to the end of the second bit line. The first string selection line and the second string selection line of the first bit line and the plurality of string selection lines overlap. The first series of select lines and the second series of select lines each include a first side and a second side that are opposite in position. The first bit line end point is closer to the first side than the second bit line end point.

The first bit line intersects the first subset of the plurality of columns, wherein the columns intersect the first string select line. The first bit line intersects the second subset of the plurality of columns, wherein the columns intersect the second string select line. The first subset of the columns includes a first column that is closest to the first side of the first string selection line. The second subset of the columns includes a second column that is closest to the first side of the second series of select lines.

The first distance is between the first column and the first side of the first string selection line; the second distance is between the second column and the first side of the second string selection line. And the first distance and the second distance are different.

In an embodiment of the present technology, the second bit line of the plurality of bit lines extends from the third bit line end point to the fourth bit line end point. The first bit select line and the second string select line of the second bit line and the plurality of string select lines overlap. The first series of select lines and the second series of select lines each include a first side and a second side that are opposite in position. The third bit line end point is closer to the first side than the fourth bit line end point.

The second bit line intersects a third subset of the plurality of columns, wherein the columns intersect the second series select line. The third subset of the columns includes a third column that is closest to the first side of the second string selection line.

The third distance is between the third column and the second side of the first series selection line. And the first distance and the third distance are the same.

In an embodiment of the present technology, the first bit line and the second bit line are adjacent.

The "lateral" dimension generally refers to the dimension of the structure parallel to the substrate. The "vertical" direction generally refers to the dimension of the structure and is generally perpendicular to the substrate. In addition, if a layer is "above" or "below" in another layer, in some embodiments, such description may include one or more intermediate layers that separate the layer from the other layers. If there is no intermediate layer, it will be described using "immediately above" or "immediately below" in these embodiments. The same interpretation is also used to describe that one layer "superposing" to other layers, one layer "underlying" to another layer, or one layer "over" to other layers.

The two objects "adjacent" to each other means that the two are not separated by the same type of object. For example, two "serial" selection lines "adjacent" to each other means that no intermediate serial selection line is located between the two, even if the two serial selection lines are in contact with each other. Unless explicitly emphasized, the term "contiguous" does not require immediate adjacency.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

8‧‧‧ bit line

9‧‧‧Interlayer conductor

10‧‧‧Contact pads

11‧‧‧Insulation core

14‧‧‧Semiconductor material columnar shell

15‧‧‧ columnar body

16‧‧‧First oxide layer

17‧‧‧矽 nitride layer

18‧‧‧Second tantalum oxide layer

20-23‧‧‧ character line

24, 115, 215, 315, 415, 515, 615‧‧‧ tandem selection line

24A, 24B‧‧‧ tandem selection line conductive strip

25, 26A, 26B‧‧‧ Grounding selection line

25A, 25B‧‧‧ Grounding selection wire conductive strip

27‧‧‧Common source line

32‧‧‧Insulated dielectric layer

33A‧‧‧First side

33B‧‧‧Second side

34‧‧‧ bit line direction

35A‧‧‧First wave line

35B‧‧‧second wave line

35Ac, 35Bc‧‧‧ crest column

35At, 35Bt‧‧‧ trough columnar

36A, 36B‧‧‧ columnar wavy line

Side of the 37A, 37B‧‧‧ character line conductive strip

38A, 38B‧‧‧ side of the grounding selection line

41‧‧‧Upper layer of grounding wire

42‧‧‧Under the grounding wire

43A, 43B‧‧‧ side of the grounding wire

141, 143, 241, 242, 243, 244 ‧ ‧ columnar body

163, 164, 263, 264, 363, 364, 463, 464, 563, 564, 663, 664 ‧ ‧ sided side of the selection line

163‧‧‧The top side of the tandem selection line

264‧‧‧Bottom side of the tandem selection line

361, 362, 461, 462‧‧‧ wavy lines (grid lines)

470‧‧‧Area

563, 664‧‧‧ conductive strips adjacent sides

769‧‧‧separation of tandem selection lines

782, 890‧‧‧ right triangle

3-4-5‧‧‧The sides of a right triangle

958‧‧‧ Planar Decoder

960‧‧‧Memory array

961‧‧ ‧ row decoder

962‧‧‧ character line

963‧‧‧ column decoder

966‧‧‧Perceptual Amplifier/Data Entry Structure

967‧‧‧ data bus

968‧‧‧Voltage supply line or supply

969‧‧‧ state machine

971‧‧‧ data input line

974‧‧‧Other circuits

975‧‧‧ integrated circuit

A-A’ ‧‧‧ Thread

A‧‧‧ outer diameter of the second tantalum oxide layer (diameter of the columnar body)

b‧‧‧Distance from the outer cylindrical body to the side of the tandem selection line

B-B’ ‧‧‧ Thread

BL‧‧‧ bit line

c‧‧‧Distance of the distance between the series selection lines

CSL‧‧‧Common source line

g‧‧‧Split selection line spacing

GND‧‧‧Connected area

GSG‧‧‧Ground selection gate

H‧‧‧saving spacing

H764‧‧‧distance difference

q 766, q’ 768‧‧‧ directions

R1, R2‧‧‧ horizontal dimension

SSL‧‧‧ tandem selection line

SSG‧‧‧Serial selection gate

S260, S'360, S" 460, S"' 660, S760, S' 762, d, e, f‧‧‧ distance

WLs‧‧‧ character line

Θ‧‧‧ Deviation angle

Φ‧‧‧ Deviation angle

SSL _x T _y , SSL ₂ T ₂₁ 541, SSL ₁ T ₃₉ 643, SSL ₂ T ₃₉ 542‧‧‧ Distance between the columnar body coupled to the bit line y and the top side of the tandem selection line x

SSL _x B _y , SSL ₁ B ₂₁ 641, SSL ₁ B ₂₄ 642‧‧‧ Distance between the columnar body coupled to the bit line y and the bottom side of the tandem selection line x

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below in conjunction with the accompanying drawings, which are described in detail below: Figure 1 and Figure 2 show the flash memory cells, respectively. Upper and side views of the tubular column. Figure 3 is a diagram showing a three-dimensional semiconductor component. 4A and 4B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. The upper view shows the serial selection line. 5A and 5B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. Among them, the upper view shows the word line. Figure 6 is a top view showing a set of parallel bit lines electrically coupled to the top of the columnar body. Figure 7 is a top view showing a set of parallel bit lines electrically coupled to the top of the columnar body. The columnar body intersects the tandem selection line having wavy sides. Figure 8 is a top view showing a set of parallel bit lines electrically coupled to the top of the columnar body. Wherein the columnar body intersects the tandem selection line having wavy sides, and the tandem selection lines are moved to bring them closer together. Figure 9 is a top view showing a set of parallel bit lines electrically coupled to the top of the columnar body. Wherein the columnar body intersects the tandem selection line having the wavy side edges, and the tandem selection lines are moved to bring them closer together. Figure 10 is similar to Figure 7 and shows the area saved using a tandem selection line with wavy sides. Figure 11 is similar to Figure 6, showing the area saved using a tandem selection line with wavy sides. 12A and 12B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. The upper view shows the ground selection line. 13A and 13B are top and side views, respectively, showing an embodiment of a three-dimensional memory element using a vertical channel structure. The upper view shows the grounding wire. Figure 14 is a simplified block diagram of an integrated circuit memory of a three-dimensional vertical gate memory array having wavy sides as described herein.

15‧‧‧ columnar body

24A, 24B‧‧‧ tandem selection line conductive strip

33A‧‧‧First side

33B‧‧‧Second side

34‧‧‧ bit line direction

35A‧‧‧First wave line

35B‧‧‧second wave line

35Ac, 35Bc‧‧‧ crest column

35At, 35Bt‧‧‧ trough columnar

36A, 36B‧‧‧ columnar wavy line

A-A’‧‧‧ cut line

B-B’‧‧‧ cut line

BL‧‧‧ bit line

R1, R2‧‧‧ horizontal dimension

Θ‧‧‧ Deviation angle

Φ‧‧‧ Deviation angle

Claims (20)

A memory component, comprising: a NAND string array, located below a plurality of bit lines, the bit lines extending along a bit line direction; a plurality of string selection lines and a plurality of word lines, including construction a plurality of conductive strips in the plurality of conductive layers; a first page comprising a plurality of NAND strings in the array of NAND strings extending through the conductive layers and coupled to the series of select lines a first series of select lines; the NAND strings in the first page are disposed in a first grid, the first grid being offset from the bit line by an off angle (off-angle); and the conductive strips of the series of selection lines each have at least one curved side. The memory device of claim 1, wherein the conductive strips of the word lines each have at least one curved side. The memory device of claim 1, wherein the NAND strings in the NAND string array have a plurality of ground selection switches, the ground selection switches including a plurality of conductive strips located on the conductive layers And the conductive strips of the ground selection switches each have at least one curved side. The memory component of claim 1, further comprising a second page coupled to a second string selection line of the series of selection lines, the second series selection line and the second a series of column selection lines abutting, and comprising a plurality of conductive strips each having at least one curved side; the bit lines are superposed on the first page and the second page, and have one bit between each other a bit line pitch, each of the bit lines being connected only to a corresponding one of the first page and the second page; wherein the second page includes a second a grid, and the first grid and the second grid are both a regular grid; each of the regular grids has a first lateral dimension and a second lateral dimension, respectively Rotating an acute angle deviation angle and an obtuse angle deviation angle in the direction of the bit line; and having a first lateral spacing and a second lateral spacing in the first lateral dimension and the second lateral dimension, respectively, and the bit line The pitch is smaller than the second lateral pitch; wherein the first page includes a first The edge NAND string subset is disposed on a first wave line, the first wave line intersecting the bit line direction due to the off angle; the bending of the conductive strips of the first string selection line The set of sides is a first side, located between the first string selection line and the second string selection line, and extends along the first wave line; and wherein the second page includes a Second outer edge NAND string subset, Arranging on a second wave line, the second wave line intersecting the bit line direction due to the off angle; the set of the curved sides of the conductive strips of the second string selection line is a first The two sides are located between the first string selection line and the second string selection line and extend along the second wave line. The memory component of claim 1, further comprising a second page comprising a plurality of NAND strings in the NAND string array, disposed in a second grid, the second grid Adjacent to the first mesh; wherein the first mesh includes a first outer edge NAND string subset disposed on a first wavy line, the first wavy line having at least one crest and a trough a first straight line with respect to a direction perpendicular to the bit line; and a second outer edge NAND string subset disposed on a second wavy line having at least one peak and at least one trough relative to a second line perpendicular to the direction of the bit line; the second grid includes a third outer edge NAND string subset disposed on a third wavy line, the third wavy line is located in the second grid a third line having at least one peak and at least one valley relative to a direction perpendicular to the bit line; and a fourth outer edge NAND string subset disposed on a fourth wavy line, the fourth The wavy line has at least one peak and at least one trough relative to the vertical a fourth line in the direction of the bit line; and wherein the first page is located on the peak of the first wave line a NAND string connected to a specific bit line of the bit lines; and a NAND string of the second page located on the peak of the third wave line is connected to the specific bit line. The memory component of claim 1, further comprising a second page comprising a plurality of NAND strings in the NAND string array, disposed in a second grid, the second grid Adjacent to the first mesh; wherein the first mesh includes a first outer edge NAND string subset disposed on a first wavy line, the first wavy line having at least one crest and a trough a first straight line with respect to a direction perpendicular to the bit line; and a second outer edge NAND string subset disposed on a second wavy line having at least one peak and at least one trough relative to a second line perpendicular to the direction of the bit line; the second grid includes a third outer edge NAND string subset disposed on a third wavy line, the third wavy line is located in the second grid a third line having at least one peak and at least one valley relative to a direction perpendicular to the bit line; and a fourth outer edge NAND string subset disposed on a fourth wavy line, the fourth The wavy line has at least one peak and at least one trough relative to the vertical a fourth line in the direction of the bit line; and wherein a NAND string on the peak of the first page in the first page is connected to a specific bit line of the bit lines; And a NAND string on the peak of the second page in the second page is connected to the specific bit line. The memory component of claim 1, further comprising a second page comprising a plurality of NAND strings in the NAND string array, disposed in a second grid, the second grid Adjacent to the first mesh; wherein the first mesh includes a first outer edge NAND string subset disposed on a first wavy line, the first wavy line having at least one crest and a trough a first straight line with respect to a direction perpendicular to the bit line; and a second outer edge NAND string subset disposed on a second wavy line having at least one peak and at least one trough relative to a second line perpendicular to the direction of the bit line; the second grid includes a third outer edge NAND string subset disposed on a third wavy line, the third wavy line is located in the second grid a third line having at least one peak and at least one valley relative to a direction perpendicular to the bit line; and a fourth outer edge NAND string subset disposed on a fourth wavy line, the fourth The wavy line has at least one peak and at least one trough relative to the vertical a fourth line in the direction of the bit line; and wherein a NAND string on the peak of the first page in the first page is connected to a particular bit line of the bit lines; One of the second pages in the trough on the third wavy line A NAND string connected to the particular bit line. The memory component of claim 1, further comprising a second page comprising a plurality of NAND strings in the NAND string array, disposed in a second grid, the second grid Adjacent to the first mesh; wherein the first mesh and the second mesh are respectively configured as a regular mesh, and the off-angle is offset from the bit line direction, and each of the regular meshes has a regular spacing. Having a pointing from the off-angle of the bit line direction; and the regular spacings of the first mesh and the second mesh cancel each other in a direction perpendicular to the bit line. The memory component of claim 1, further comprising a second page comprising a plurality of NAND strings in the NAND string array, disposed in a second grid, the second grid Adjacent to the first mesh; wherein the first mesh and the second mesh are respectively configured as a regular mesh, and the off-angle is offset from the bit line direction, and each of the regular meshes has a regular spacing. a pointing having an off angle from the direction of the bit line; and the regular spacing of the first grid and the second grid at the bit The lines cancel each other out. The memory component of claim 1, further comprising a second page comprising a plurality of NAND strings in the NAND string array, disposed in a second grid, the second grid Adjacent to the first mesh; wherein the first mesh and the second mesh are respectively configured as a regular mesh, and the off-angle is offset from the bit line direction, and each of the regular meshes has a regular spacing. Having a direction that deviates from the direction of the bit line; and the regular spacing of the first and second grids cancel each other in the direction of the bit line and in the direction of the bit line. A memory component, located on a substrate, comprising: a multilayer stack structure comprising a plurality of conductive strips; a plurality of columnar bodies extending through the multilayer stack structure; a plurality of memory cells located in the plurality of columns a plurality of intersections between the body and the plurality of conductive strips; a first tandem select line and a second tandem select line are all located in the multi-layer stack structure; wherein the plurality of columns extend through the The plurality of columns of the first string selection line are a first page; the plurality of columns extending through the second series selection line of the columns are a second page; a plurality of serial selection gates at a plurality of intersections between the plurality of columns and the first string selection line and the second string selection line; a plurality of bit lines located in the first string Above the column select line and the second string select line, having a one-line spacing, wherein each of the bit lines is respectively connected to a corresponding one of the first page and the second page; The first column and the second column of the columns are respectively arranged in a first grid and a second grid, and the first grid and the second grid are both a regular network. Each of the regular grids has a first lateral dimension and a second lateral dimension, respectively rotating an acute angle deviation angle and an obtuse angle deviation angle with respect to the bit line direction; and respectively in the first lateral dimension and The second lateral dimension has a first lateral spacing and a second lateral spacing, and the bit line spacing is less than the second lateral spacing; the first lateral spacing of the first grid and the second grid And the second lateral directions cancel each other in a direction perpendicular to the bit line; the first point Having a first outer edge columnar body subset disposed on a first wave line, the first wave line intersecting the bit line direction due to the off angle; the first string selection line includes a plurality of the plurality of lines a conductive strip having a first curved side between the first series selection line and the second series selection line and extending along the first wavy line; and the second page has a a second outer edge columnar body disposed on a second wave line, the second wave line intersecting the bit line direction due to the off angle; the second string selection line includes a plurality of the plurality of conductive strips Belt, and There is a second curved side located between the first series selection line and the second series selection line and extending along the second wave line. The memory device of claim 11, wherein the first wavy line comprises at least one peak column disposed on at least one peak relative to a first straight line in a direction perpendicular to the bit line, and at least one The trough columnar body is disposed on at least one trough relative to the first line; the second wave line has at least one crest columnar body disposed on at least one peak relative to a second line perpendicular to the direction of the bit line, And at least one trough columnar body is disposed on at least one trough relative to the second line; wherein a crest column on the first wave line of the first page is connected to the bit lines a specific bit line; and a crest column on the second wave line of the second page is connected to the specific bit line. The memory component of claim 11, wherein the second page has a third outer edge column subset disposed on a third wavy line, and the third wavy line is due to the off angle. Intersecting with the bit line direction; the second string selection line has a third curved side opposite to the second curved side and extending along the third wave line; the first wave line includes at least one peak The columnar body is disposed on at least one peak relative to a first straight line perpendicular to the direction of the bit line, and at least a trough columnar body disposed on at least one trough relative to the first line; the third wave line having at least one crest columnar body disposed on at least one peak relative to a third line perpendicular to the direction of the bit line And at least one trough columnar body is disposed on at least one trough relative to the third line; wherein a crest column on the first wave line of the first page is connected to the bit lines a specific bit line; and a crest column on the third wave line of the second page is connected to the specific bit line. The memory device of claim 11, wherein the conductive strips have at least one curved side located on one side of the multilayer stack. The memory component of claim 11, further comprising a ground selection conductive strip under the multi-layer stack structure; the pillars in the first page and the second page extend through The ground selects a conductive strip; and the ground select conductive strip has at least one curved side. The memory component of claim 11, further comprising: a source line located below the multi-layer stack structure, at least connected to the a first page; and a contact structure abutting the first page and extending to the source line, and the contact structure has at least one curved side. A method of fabricating a memory device, comprising: forming a NAND string array, located under a plurality of bit lines, such that the bit lines extend along a bit line direction; forming a plurality of string selection lines and a plurality of lines a word line, wherein the string selection lines and the word lines comprise a plurality of conductive strips constructed in the plurality of conductive layers; forming a first page, the first page being included in the NAND string array a plurality of NAND strings extending through the conductive layers and coupled to a first one of the series of select lines; the NAND strings in the first page are set in a In a grid, the first grid is offset from the direction of the bit line by an off angle; and the conductive strips of the series of select lines each have at least one curved side. The method of fabricating the memory device of claim 17, wherein the conductive strips of the word lines each have at least one curved side. The system for memory components as described in claim 17 The method, wherein the NAND strings in the NAND string array have a plurality of ground selection switches, the ground selection switches including a plurality of conductive strips in the conductive layers, and the ground selection switches The conductive strips have a plurality of curved sides. The method of fabricating the memory device of claim 17, further comprising: forming a second page in the NAND string array, wherein the second page comprises a plurality of the NAND string array The NAND string is disposed in a second grid; wherein the first grid and the second grid are respectively configured as a regular grid, and the off-angle is offset from the bit line direction, and each of the rules The grid has a regular spacing with a pointing offset from the direction of the bit line; and the regular spacing of the first grid and the second grid cancels each other in a direction perpendicular to the bit line.