CN105990361B - High velocity vertical channel three-dimensional NAND gate memory device - Google Patents
High velocity vertical channel three-dimensional NAND gate memory device Download PDFInfo
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- CN105990361B CN105990361B CN201510063076.3A CN201510063076A CN105990361B CN 105990361 B CN105990361 B CN 105990361B CN 201510063076 A CN201510063076 A CN 201510063076A CN 105990361 B CN105990361 B CN 105990361B
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Abstract
The present invention provides a kind of memory devices.The memory device has the multiple-level stack of conductive layer.Each vertical arrangement position to column include the memory cell being connected in series, memory cell is located at the crosspoint of column and conductive layer.String selection line (SSLs) passes through on conductive layer, and each crosspoint of column and string selection line defines a selection gate (select gate) for column respectively.Bit line passes through on string route selection.Column is set on a regular grid, and wherein regular grid is rotated relative to bit line.Grid can have the storage unit of square, rectangle or diamond shape, and can rotate an angle, θ by tan (θ)=± X/Y relative to bit line, and wherein X and Y is relatively prime integer.String selection line can be made into sufficiently wide all columns or the sufficiently wide column to intersect two or more non-adjacent storage units to intersect two columns or storage unit of storage unit side.
Description
Technical field
The invention relates to one kind to have highdensity memory device, and in particular to a kind of more planes of configuration
Storage unit is to provide the memory device of three-dimensional (3D) array.
Background technique
As the critical dimension of the device in integrated circuit is contracted to the limit of general memory cell technologies, designer exists
Seek to stack the technology of more planar storage cells, to reach bigger storage capacitance and reduce every cost.For example,
Lai et al. is published in " A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type
Flash Memory, " IEEE Int ' l Electron Devices Meeting, 11-13Dec.2006 and Jung et al.
It is published in " Three Dimensionally Stacked NAND Flash Memory Technology Using
Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm
Node, " technology contents of IEEE Int ' l Electron Devices Meeting, 11-13Dec.2006 disclose film crystal
Manifold technology is applied to charge capturing memory technology.
Another structure is described in Katsumata et al. and is published in " Pipe-shaped BiCS Flash Memory with
16Stacked Layers and Multi-Level-Cell Operation for Ultra High Density
Storage Devices, " 2009Symposium on VLSI Technology Digest of Technical Papers,
2009 technology contents, wherein providing vertical NAND gate (NAND) unit in charge capturing memory technology.In Katsumata etc.
Structure described in the delivering of people includes a vertical NAND gate grid, utilizes silicon-oxygen-nitrogen-oxygen-silicon (SONOS) charge-trapping
Technology, to generate a storage location (storage site) in each grid/vertical channel interface.This memory construction is to be based on
A line (column) semiconductor material arranges the vertical channel as NAND gate grid, has and selects in selection gate and one
Grid, lower selection gate are located at top close to substrate, upper selection gate.Multiple horizontal wordline utilize plane word line layer and multirow
Semiconductor material intersects and is formed, and forms so-called grid circulating type storage unit (gate all-around in each layer
cell)。
Fig. 1 is painted a line tubulose BiCS flash cells horizontal sectional drawing, in the horizontal profile of a wordline level (level)
Figure, storage unit is, for example, storage unit described in Katsumata et al..Its structure includes one with semiconductor material centronucleus
The column 15 of the heart (center core) 110, column 15 extend vertically through the stacking of word line layer.Prostheses 110 can be with
With the seam (seam) 111 by center, seam 111 is generated by deposition technique.One dielectric charge catch structure surrounds center
Core 110, dielectric charge catch structure is for example including one first silicon oxide layer 112, a silicon nitride layer 113 and one second oxidation
Silicon layer 114 (referred to as ONO layer), or another multilayer dielectric charge trapping structure.One grid circulating type wordline 115 and column 15
Intersection.The frustum (frustum) of column 15 in each layer combines in this layer with grid circulating type wordline, to be formed
One storage unit.
Fig. 2 is painted the perspective view of a 3 D semiconductor element.It includes the multiple-level stack of wordline conductive layer 11, each conduction
Layer is parallel to substrate 10；Multiple columns 15, arranging position to substrate, each column is orthogonal to includes depositing for multiple series connections
Storage unit, storage unit are located at the crosspoint of column and conductive layer；And multiple string selection lines 12, arrangement position is to being parallel to base
Plate is simultaneously located on conductive layer 11, the column of a difference of each string selection line intersection column.Column and selection line of going here and there
Each crosspoint defines a selection gate of column respectively.Its structure also includes multiple parallel bit line conductors 20, is matched
It is set to one layer and is parallel to substrate and is located on string selection line.The overlapped difference in column of each bit line conductors
Row and each column are located at a bit line conductors lower section.Column 15 can be constructed as the structure shown as depicted in FIG. 1.
Fig. 3 is the top view of part-structure depicted according to fig. 2.Thus two figures can see in total, word
Line conductive layer 11 only intersects some columns；Wordline conductive layer 11 defines a storage unit block (block of memory
cells).Therefore, data (data) is read from certain memory blocks of cells, control circuit wants first enable (activates)
One wordline conductive layer 11 is gone forward side by side with selecting the specific stratum in a particular memory location block and multilayer lamination structure
One a string of selection lines of step enable 12 select a particular column.One lower selection gate (not being painted) of enable simultaneously.Then a column are deposited
Storage unit is read to page buffer (page buffer) by parallel (in parallel) by bit line 20 and (is not painted) (this
" enable (Activate) " in place refers to one particular bias voltage of application, and to influence, (to give effect to) is connected to be deposited
The effect of storage unit or switch.Bias can be high or low, depending on the design of memory.) according to product specification and design, page
Face buffer area can save the data of two or more columns, and a complete page read operation may include in this case
The enable of two or more subsequent string selection lines 12.
When storage density (memory density) is significantly increased in three-dimensional stacked memory construction as expected while also spreading out
Many technologic challenges are given birth to, since it is desired that etching very deep hole to pass through many layers.The width of these deep holes must add
Width, and the lateral distance of each deep hole center to center must increase, to meet process specification (process windows).When
Manufacturing process improves, and capacitor can increase, not only by increasing the quantity of wordline plane in stacking, also by between reduction column
Distance.Fig. 4 is painted the top view of the structure of scaled down, wherein the quantity of block neutrality line conductor 20 and string selection line 12
Increase.This not only reduces cost, while also can reach and increasing data read/write rate (read/write data rate)
Purpose.Because greater number of bit line conductors 20 represent the increase of operation repetitive (parallel operation).But another party
Face, the increase of 12 quantity of serial selection line represents more multiple memory cell can be by the Vpass interference caused by wordline selection
(Vpass disturb).Memory cell capacitor (unit cell capacitance) increases also with the quantity of string selection line 12
And increase, thus cause power consumption to increase and slow down element operation.
Quantity by increasing the wordline conductive layer 11 in stacked structure is removed with increasing bit line density (bit density)
Layer number increase derives except expected process challenge, and there are also its disadvantage.It can be seen that one has ladder in Fig. 2
Shape structure (stepped contact structure) is connected to the Typical arrangements of wordline conductive layer 11.In order to form touching
Point (contacts) 22 uses the metal interconnecting piece (metal interconnects) 24 that conductive layer 11 is connected to top, must
The deep trench (deep trench) of this structure must be made through.Also it is symbolically drawn by the top view of Fig. 4 these contacts 22
Show.In modular design, the quantity of the column of a block cylindrical body 15 at least can be with contact 22 and memory layer (wordline conductive layer
11) quantity is as many.For example, referring to Komori, Y., et.al. are published in " Disturbless flash memory
due to high boost efficiency on BiCS structure and optimal memory film stack
for ultra high density storage device,"Electron Devices Meeting,2008,IEDM
2008, IEEE International, vol., no., pp.1-4, the technology contents of 15-17 (Dec.2008) at 2, above-mentioned phase
Periodical content is incorporated by reference in the content of this specification.Since the increase of accumulation layer also promotes string selection line 12
Number increases, thus also results in power consumption and increase and slow down element operation.
Therefore, in need to create a kind of reliable solution, it is same in the bit line density for increasing three-dimensional memory structure
When reduce its negative impact caused, to obtain preferable chip yield, circuit closer, efficiency is more powerful, element
Or system.
Summary of the invention
It generally describes, technology of the invention provides a kind of memory device, has arrangement position to being parallel to a substrate
The multiple-level stack that multiple conductive layers are constituted.It is each arrangement position to the column for being orthogonal to substrate include be connected in series memory cell,
Memory cell is located at the crosspoint of column and conductive layer.String selection line is configured on conductive layer, column and selection line of going here and there
Each crosspoint defines a selection gate of column respectively.Bit line configuration is on string selection line.Column is set to
On one regular grid, wherein regular grid is rotated relative to bit line conductors.Grid can have square, rectangle or diamond shape
Storage unit, and one angle, θ can be rotated by tan (θ)=± X/Y relative to bit line, wherein X and Y is relatively prime integer.String
Selection line can be made into sufficiently wide to intersect two columns of storage unit side or all columns of storage unit,
Or the sufficiently wide column to intersect two or more non-adjacent storage units.This rotates the bit line for allowing higher density,
Therefore can because of operation repetitive increase and obtain higher data rate.Small number of string selection also can be used simultaneously
Line reads interference and power consumption by reducing memory cell capacitor to reduce, and then improve data rate.
Above-mentioned abstract of the invention is provided to provide the basic comprehension to some aspects of the present invention.Above-mentioned abstract not to
Mark key or necessary component, nor to describe profile of the invention.Its purpose is only to show the present invention in a simplified manner
Concept, using the prelude as aftermentioned detailed embodiment.The particular embodiment of the present invention will be described in claim, explanation
Book and attached drawing.
Detailed description of the invention
The present invention will be described specific embodiment referring to appended attached drawing, in which:
Fig. 1 is painted the horizontal sectional drawing of a line tubulose BiCS flash cells.
Fig. 2 is painted the perspective view of a 3 D semiconductor element.
Fig. 3 is the top view of part-structure depicted according to fig. 2.
Fig. 4 is the top view of part-structure depicted according to fig. 2, and size scaled down is to allow more bit lines and string
Selection line.
Fig. 5 is to illustrate the top view for the column volume array being located in the conventional three-dimensional structure as depicted in Fig. 2 and Fig. 4.
Fig. 6 is the top view of the column volume array in depicted three-dimensional structure according to an aspect of the present invention.
Fig. 7 is painted the structure of Fig. 5, has several different rotation angles relative to bit line conductors.
Fig. 8 is painted a structure, and wherein grid is rotated a special angle.
Fig. 9 is painted another view of the structure of Fig. 8, shows bit line conductors and a SSL.
Figure 10 is painted a regular grid of column, and wherein storage unit is rectangle.
Figure 11 is painted by the grid of Figure 10 of one angle, θ of rotation.
Figure 12 is painted a regular grid of column, and wherein storage unit is diamond shape.
Figure 13 is painted by the grid of Figure 12 of one angle, θ of rotation.
[symbol description]
10: substrate
11: conductive layer
12,512,612 (612-1,612-2), 912,1012: string selection line
15,515,615,715,915,1015: column
20、520、620(620-1、620-2)、722、724、726、728、730、732、920、
1020, BL: bit line conductors
22: contact
24: metal interconnecting piece
110: prostheses
111: seam
112: the first silicon oxide layers
113: silicon nitride layer
114: the second silicon oxide layers
115: grid circulating type wordline
A, B, C, D: column
D: the distance between column
D1: the short side length of storage unit
D2: the long side length of storage unit
P: the spacing of bit line conductors
X, Y: horizontal space dimension
Z: vertical space dimension
ABCD: storage unit
θ: acute angle
Specific embodiment
Following description, which can provide those of ordinary skill in any technical field, to be had to use, make the present invention.It should
Description is provided only for specific with requirement background.Those of ordinary skill can be to the embodiment being disclosed in technical field
It is modified, and rule disclosed herein will be applicable to other embodiments and application, without departing from of the invention
Scope.Therefore, the proposition of embodiment, only to illustrate technical characteristic of the invention, the power being not intended to limit the invention
Benefit requires.
Fig. 5 is to illustrate the top view for the column volume array being located in the conventional three-dimensional structure as depicted in Fig. 2 and Fig. 4.Fig. 5
In each dot (dot) represent the lateral position of corresponding column 515." laterally (lateral) " used herein
Spatial Dimension, which refers to, to be parallel to the structure space dimension of substrate (such as X-axis and Y-axis is indicated in Fig. 1, Fig. 2, Fig. 3 and Fig. 4
Spatial Dimension).Its structure includes other all elements depicted in Fig. 2, but in order to clearly demonstrate, most member in Fig. 5
Part has been ignored.In particular, structure depicted in Fig. 5 includes the multiple-level stack of conductive layer 11, each layer of arrangement position Xiang Pinghang
In substrate.Multiple string selection lines 512 (wherein one is shown in Fig. 5) arrange positions to be parallel to substrate and be located at conductive layer it
On, string selection line is rectangle and there is its long spacing dimension to arrange position in the Y Spatial Dimension shown as shown graphically in fig 5.It is used herein
Layer its be referred to as in other layers " on (above) " or " under (below) ", can be in different embodiments by one or more
More middle layers (interventing layers) and separated with other layers.Identical explanation is also applied for layer and is described positioned at another
One layer " overlapped (superposing) ", " lower section (underlying) " or " covering (over) ".
A respectively different subset (a respective distinct in each string selection line intersection column 515
Subset), and each crosspoint of column and string selection line defines a selection gate of column 515 respectively.In Fig. 5
In be configured to one layer in multiple parallel digit lines conductors 520 (wherein one is shown in Fig. 5) that X Spatial Dimension extends and be parallel to
Substrate is simultaneously located on string selection line, the row of the overlapped difference in column 515 of each bit line conductors.In addition, each column
Shape body 515 is located under a bit line conductors.Each column 515 arranges position to being orthogonal to substrate (vertically, as Fig. 2 is drawn
The Z-space dimension shown), and the memory cell including multiple series connections, memory cell are located at the crosspoint of column and conductive layer.?
In one embodiment, the horizontal section of a line column shows as depicted in FIG. 1.
In the setting of Fig. 5, it can be seen that the column 515 in column volume array is arranged in X-axis and Y-axis two
The regular grid of a horizontal space dimension.X Spatial Dimension is parallel to bit line conductors and Y Spatial Dimension is orthogonal to bit line conductors.This
" regular grid (regular grid) " used in text, " regular array (regular array) " refers to can be distinguished into phase
The grid (array) of adjacent storage unit, wherein all storage units can fill up this grid, and its all shape all having the same
Shape and size.Storage unit is square and is painted an example square ABCD in Fig. 5.Meanwhile in a particular embodiment, net
Lattice itself may include multiple columns and net boundary, and term used herein " grid " does not need any rule.
It is used herein to be defined as parallelogram in " storage unit (the unit cell) " of regular grid, it puts down
Four vertex of row quadrangle are located on four columns of grid.For example, the parallelogram of the storage unit in Fig. 5 by
Tetra- columns of column A, B, C and D are defined.Definition mode used herein, storage unit are since column A
Definition then select in grid near the column of column A as column B, then in selection grid with column A and
Column B non-colinear and to be used as column C near the column of column A, and select the 4th in the parallelogram
The column on a vertex is as column D.Unless otherwise indicated, " distance (distance) " between column used herein
Refer to the distance (Euclidean center-to-center distance) of euclidean center to center between column.This
Outside, " in distance (the distance in a particular of a particular space dimension between two column used herein
Dimension) ", refer in this particular space dimension coordinate difference of two columns and ignore the coordinate of other Spatial Dimensions.
For example, the distance between column A and column B are d, and d is also the distance between column C and column D in Fig. 5.Column
" distance (distance) " between shape body B and column C is d √ 2, but column B and column C are between Y Spatial Dimension
" distance (distance) " be d.In addition, the column of " near (nearest) " one used herein given column, is
Referring to has the column that the column shortest distance is given from this.If there is more than one identical most short with column is given from this
The column of distance, then any one of its all meets the condition that column " near (nearest) " is given from this.
In grid depicted in Fig. 5, storage unit is square.The term as used herein " square (square) " is
One special circumstances of term " rectangle (rectangle) ", square is the rectangle that four sides all have equal length herein.Equally
Ground, " square (square) " are also a special circumstances of " diamond shape (rhombus) ", and it is all straight that square, which is four angles, herein
The diamond shape at angle.In addition, square, rectangle and diamond shape are all the special feelings of term " flat shape quadrangle (parallelogram) "
Condition.Rectangle is the flat shape quadrangle that four angles are all right angle；Diamond shape is the flat shape quadrangle that four sides all have equal length,
And it is all the flat shape quadrangle that right angle and four sides all have equal length that square, which is four angles,.Therefore, in Fig. 5 just
Rectangular ABDC can be referred to as diamond shape, square and flat shape quadrangle simultaneously.
Fig. 6 is the top view of the column volume array in depicted three-dimensional structure according to an aspect of the present invention.Such as figure
Each dot (dot) in 5, Fig. 5 represents the lateral position of corresponding column 615.Its structure include in Fig. 2 it is all its
His element, but in order to clearly demonstrate, most element has been ignored in Fig. 6.Two string selection lines 612-1 and 612-2
(being referred to as 612) and two bit line conductors 620-1 and 620-2 (being referred to as 620) are shown.Although the Partial Mesh that Fig. 6 is painted
Boundary meet the boundary of Partial Mesh occurred in Fig. 5 of rotation version, reason is it should be understood that the two grids may include
More columns as illustrated.In Fig. 6, continue to make attached drawing complete for example, grid generally includes additional column, square
Shape region has alignment and is orthogonal to the boundary of bit line.
Such as the structure of Fig. 5, each string selection line 612 intersects a respectively different subset of column 615 in Fig. 6, and
Multiple selection gates are defined by these crosspoints.Similarly, overlapped one in column 615 of each bit line conductors 620
Row respectively, and each column 615 is located under bit line conductors 620 1.In the structure of Fig. 6, however, the net of column
Lattice rotate clockwise angle, θ=45 ° relative to bit line conductors 620.Its provide two advantages, firstly, bit line conductors 620 one compared with
In small spacing, p=dsin (45 °).This allows the bit line of higher density without reducing any adjacent column in grid
Distance d between body.Furthermore, it is possible to reduce the quantity of string selection line 612, because the width of each string selection line 612 is made
Sufficiently wide (Spatial Dimension of parallel digit lines conductor 620) to intersect two column columns.In other words, in the identical of storage unit
On side, sufficiently wide at least two columns to intersect storage unit of width of each string selection line 612.For example, in Fig. 6
In, (string selection line 612-1 also intersects column by the column A and column C of string selection line 612-1 intersection storage unit A BDC
D).And although intersecting two column columns, each crosspoint of a string selection line 612 and a bit line conductors 620 is in grid
It still can individually distinguish single a column.That is, one wordline conductive layer 11 of enable and a serial selection line 612 still may be used
Uniquely to select single a storage unit in bit line 620.Therefore, the rotation grid of Fig. 6 realizes the bit line of higher density
Conductor 620, therefore higher data rate is caused with the quantity of lower string selection line since operation repetitive increases, to reduce
Interference is read, power consumption is reduced and further improves data rate by reducing memory cell capacitor.
Grid in Fig. 6 structure rotates angle, θ=45 ° relative to bit line conductors 620.Other rotation angles can make
For in different embodiments；However, and not all angle all operational excellences.For convenience, Fig. 7 is painted the structure of Fig. 5, has
Several different rotation angles relative to bit line conductors.On the grid that the bit line conductors that Fig. 7 is painted rotation do not rotate in one, generation
For being painted the bit line conductors that do not rotate on the grid of a rotation.Reason should be understood that the identical knot of type specification of the two performances
Structure, because of as a result the rotation angle of the grid relative to bit line conductors.
Five rotation angles are illustrated in Fig. 7.For bit line conductors 722, rotation angle is θ=45 °, and depicted in Fig. 6
It is identical.For bit line conductors 724, it is about 33.7 ° that rotation angle, which is θ=arctan (2/3),.For bit line conductors 726,
Rotation angle is θ=arctan (1/2), is about 26.6 °.For bit line conductors 728, rotation angle is θ=arctan (2/
It 5), is about 21.8 °.For bit line conductors 730, it is about 18.4 ° that rotation angle, which is θ=arctan (1/3),.It can be with
See, for the square shaped cells grid of Fig. 7, the arctan function of the ratio between feasible rotation at least two small integer of angle
(arctangents).The angle for not meeting these standards may be unable to run well.For example, for bit line conductors 732, rotation
Angle is θ=arctan (27/48) relative to grid, is about 29.4 °.Bit line may miss Process Planning in this angle
Lattice, because it is by place too close to the column for being not intended to intersect with it.
When actually manufacturing, the rotation angle of grid closely passes through selected by the method for Fig. 7 relative to bit line conductors
Angle be important.This is because bit line conductors are very long in typical element, word line conductor is extended across all the way.If system
The angle for the angular deviation design made is too many, then bit line conductors may be staggered the process specification of corresponding pillar, this pillar is answered
It is overlapped in the long-range of bit line conductors.If used herein its meets angle in acceptable manufacturing tolerance, the rotation of grid
Gyration is known as the arctan function that " substantial (substantially) " meets the ratio between two small integers.
Fig. 8 is painted a structure, and wherein grid is about 36.9 ° by rotation one angle, θ=arctan (3/4).Column
Shape body is orthogonal to bit line in this grid and the distance between horizontal space dimension can be calculated by geometry and be equal to 0.2d.Therefore
Bit line can be separated by a spacing p=0.2d, and the number of data bits that can be read in parallel is caused to increase by five times.Fig. 9 be painted as
A part of the same mesh of Fig. 8 shows the bit line conductors 920 of close interval.In addition, the single string display of selection line 912 is covered
Lid multiple row column 915.It the use of single string selection line 912 is possible, because due to rotating angle, previously along list
Multiple columns of one bit line conductors arrangement are embodied in corresponding to multiple and different bit line conductors.As a result, a string selection
The crosspoint of line 912 and a bit line conductors 920 still can individually distinguish single a column 915.Use the grid of Fig. 9, bandwidth
(bandwidth) increase by five times, and power consumption and each five times of the reduction of stress.In addition, the string choosing that each region needs to separate
Decoder (decoders) much less for also illustrating that needs is greatly decreased in the quantity for selecting line, thus reduces cost.
Fig. 9 is also painted several storage units in regular grid.It can be seen that string selection line 912 has such as the grid of Fig. 6
The short Spatial Dimension of sufficiently large one (being parallel to bit line conductors 920) is with two column A of one 932 side of storage unit of intersection
And B.In fact, sufficiently large all four columns to intersect storage unit 932 of short Spatial Dimension of string selection line 912.
Further, the sufficiently large column to intersect different and non-adjacent storage units 932 of the short Spatial Dimension of string selection line 912
Shape body, such as in a column of storage unit 932 and a column of storage unit 934.
In the embodiment of Fig. 6, Fig. 7, Fig. 8 and Fig. 9, the regular grid of column is all to have square shape
Storage unit.That is, all storage units are parallelogram, wherein parallelogram a angle is right angle, and institute
All there is equal length d there are four side.Grid with other rectangular shapes (non-square) also can use of the invention excellent
Point.Figure 10 is painted a regular grid of column 1015, wherein storage unit be short side and long side be respectively provided with length be d1 and
The rectangle of d2.Single a bit line conductors 1020 and single string selection line 1012 are illustrated in figure.Figure 11 is painted column and is revolved
The identical grid for turning an angle, θ, causes the spacing p ratio d1 and d2 of bit line conductors narrow, and a wider string selection line (is not drawn
Show) intersect more columns than string selection line 1012.
Similarly, a regular grid of Figure 12 column 1215, wherein storage unit is diamond shape 1210.Diamond shape is one flat
Shape quadrangle, wherein four while all have equal length but without it is a pair of adjacent while form right angle.It can also be referred to as non-
The diamond shape of square.Figure 12 be painted with " normal (normal) " arrangement position to grid, wherein a line is drawn across opposite column
Storage unit between shape body be not be in parallel exactly to be orthogonal to bit line conductors.There is a spacing p in figure neutrality line conductor.Figure 13 is painted
Column causes narrower bit line conductors spacing p, and a wider string selection line by the identical grid of one angle, θ of rotation
1312 intersect more columns than string selection line 1012.Storage unit 1310 is illustrated in Figure 13 with apex marker ABDC, as above
It states and is defined.It can be seen that owning due to the rotation angle of displayAndAll it is not parallel also not just
Meet at bit line conductors.In addition, it is particularly interesting that the grid with diamond shape storage unit, the adjacent side shape of one pair of them
60 ° at an angle, as depicted in Figure 12 and Figure 13.This storage unit has between each pair of column on the side of storage unit
Identical distance d, and the distance d having the same between the opposite column of a pair of storage unit.For example, in storage unit
In 1310, ownAndAll there is equal length d.The area of this storage unit is (√
3/2)×d2, minimum value can be shown as a specific range d.
Under normal circumstances, the embodiment of the present invention includes that the grid of column rotates an angle, θ relative to bit line conductors,
So that the horizontal space dimension of grid is both not parallel or is non-orthogonal with bit line conductors.Preferably, in the storage unit of grid
In ABDC, as defined above, ownAndIt is all not parallel to be also non-orthogonal with bit line conductors.
The spacing of bit line conductors as described above, the rotation of regular grid has narrowed, it is also wide to have changed string selection line.However, reason
What is thought is the degree that rotation angle causes spacing to narrow should be avoided and be more than original 1/10.Column is minimized this is because meeting
To the design criteria of column distance, it may not be possible to meet between regulation bit line away from the design criteria that need to have minimum range.This
Outside, if the spacing of bit line narrows more than original 1/10, it may be unable to reach required process specification, so that expected needs are overlapped
It is directed at column in the bit line on column, or the bit line of the expected column that needs to be staggered is made to be staggered column.For such as
(all sides of storage unit all have equal length and storage unit a pair of phase to grid in Fig. 7 with square shaped storage cells
Adjacent side forms a right angle), indicate that rotating angle, θ relative to bit line conductors should be tan (θ)=± X/Y, wherein X and Y are
Relatively prime integer.In other words, for storage unit A BDC as defined above, no matterOrAny one all with position
Line conductor has an angle, θ, wherein tan (θ)=X/Y, and X and Y is the integer of units mutual prime rwmber.
The integer that table 1 lists all units mutual prime rwmbers leads (X, Y), corresponding rotation angle and its resulting bit line
Body spacing:
Table 1
It is preferred that rotation angle, θ should relative to bit line conductors for the grid with square shaped storage cells
It is tan (θ)=± X/Y, wherein (X, Y) is to being included in table 1.
A given value (given value) used herein is " response (responsive) " preceding value
(predecessor value), if this preceding value influences given value.If there is middle process element (intervening
Processing element), step or period, given value " can still respond " preceding value.If middle process element or step
Suddenly in conjunction with more than one value, then the output signal of middle process element or step is considered as " response " each input value.
If the case where given value is equal to preceding value, this is only a degeneration (degenerate case), wherein given value is still recognized
For " response " preceding value.Given value can also make similar definition to " degree of dependence (dependency) " of another value.
A certain information project (an item of information) used herein " distinguishes
(identification) " it is not absolutely required to the direct explanations (direct specification) of this information project.Information
It can be by indirect one layer or more (one or more layers of indirection) briefly referring to an entity information
(actual information) and then the quilt " discrimination " in some field, or by distinguishing one or more different information
Project and it is identified.Wherein these different information projects integrally add up the information project for being enough to determine entity.In addition, this
Term used in text " pointing out (indicate) ", which is meant, is equal to " distinguishing (identify) ".
The combination of independent technical characteristic or two or more those independent technique features is disclosed herein.To some extent
On, technical field those of ordinary skill can implement those according to general knowledge solely based on the overall description of this specification
The combination of vertical technical characteristic and technical characteristic.No matter whether the combination of those independent technical characteristics and technical characteristic solves
Problem described herein, and without limitation on claim of the invention.Embodiment disclosed by this case may include those independences
Technical characteristic and technical characteristic combination.Based on aforementioned reason, persons of ordinary skill in the technical field of the present invention, not
It is detached from the spirit and scope of the present invention, when various change and modification can be made.
Present invention preferred embodiment above-mentioned is provided for the purpose explained and described.It is not meant as exhausted
Or it limits the present invention and discloses to accurate form.It is apparent that being it will be apparent that when many can be made for this field practitioner
Modification and change.For example, although being carried out using the storage unit of the charge storage of vertical channel in the embodiments herein
The storage unit of description, column and other kenels still can use each aspect of the present invention technical characteristic, without realizing this
All advantages described in text.In particular, but be not limited to, in various change type, the paragraph of suggestion or this paper in relation to technical background
Any and all contents for being incorporated by reference into mode and being included into this specification, be all included into description of the invention embodiment it
In.In addition, any and all in various change class shape, the paragraph of suggestion or this paper in relation to technical background be incorporated by reference into mode
It is included into the content of this specification, is also considered to be taught by the other embodiments of this case.Embodiment described herein
It is only selected to make best explanation to the principle of the present invention and its practical application, and then makes those skilled in the art
It will be appreciated that various embodiments of the present invention and the various modifications and modification for being suitable for reaching expected special-purpose.Therefore, this hair
Bright protection scope is subject to view as defined in claim.
Claims (25)
1. a kind of memory device, which is characterized in that be located on a substrate, comprising:
One multiple-level stack has multiple conductive layers, and respectively the conductive layer arranges position to being parallel to the substrate；
Multiple columns arrange position to the substrate is orthogonal to, and respectively the column includes the memory cell of multiple series connections, those are deposited
Storage born of the same parents are located at multiple crosspoints of those columns Yu those conductive layers；
Multiple string selection lines, arrangement position is to being parallel to the substrate and being located on those conductive layers, and respectively the string selection line intersects at
The respectively different subset of the one of those columns, those columns and those string selection lines have multiple crosspoints, respectively the column
Respectively crosspoint of body and the respectively string selection line defines a selection gate of the respectively column respectively；And
Multiple bit line conductors parallel to each other are configured to one layer and are parallel to the substrate and are located on those string selection lines, respectively
The overlapped another respectively different subset in those columns of the bit line conductors, respectively the column is located at one of those bit line conductors
Under；
Wherein those columns are configured on a regular grid, which has the space dimension of mutually perpendicular two transverse directions
Degree, and the two spaces dimension is not parallel to and is also non-orthogonal with those bit line conductors；
Wherein the regular grid have a storage unit, the storage unit by be located at a parallelogram four vertex those
Four column A, column B, column C and the column D of column are constituted,
Column B in the regular grid near one of column A, and
Column C is in the regular grid with column A and column B non-colinear and near column A's
Another；
The regular grid is the grid that can be distinguished into consecutive storage unit.
2. memory device according to claim 1, wherein respectively the memory cell is deposited including a vertical channel structure, a charge
Reservoir and an insulating layer.
3. memory device according to claim 1, wherein every a pair in those columns should in the regular grid
Column is not aligned with each other on a Spatial Dimension of those parallel bit line conductors, and is being orthogonal to the one of those bit line conductors
It is separated from each other in horizontal space dimension and there is the distance at least more than d/10, wherein minimum Ou Ji of the d between those columns
Reed distance.
4. memory device according to claim 1,
Wherein
The regular grid is rotated relative to those bit line conductors, so that allAndBoth not parallel
In being also non-orthogonal with those bit line conductors, whereinAndFor four sides of the storage unit,Even
Connect column A and column B,Connect column A and column C,Connect column B and the column
Body C andConnect column A and column D.
5. memory device according to claim 1, wherein the regular grid is the grid that multiple squares are constituted.
6. memory device according to claim 5, wherein the regular grid passes through tan relative to those bit line conductors
(θ)=± X/Y rotates an angle, θ, and wherein X and Y is relatively prime integer.
7. memory device according to claim 6, wherein (X, Y) be selected from by (1,2), (1,3), (1,5), (1,6),
(1,7)、(1,8)、(1,9)、(2,3)、(2,5)、(2,7)、(2,9)、(3,4)、(3,5)、(3,7)、(3,8)、(4,5)、(4,
7), group composed by (4,9), (5,6), (5,7), (5,8) and (6,7).
8. memory device according to claim 1, wherein the storage unit is pushed up by four that are located at a parallelogram
Four column A, column B, column C and the column D of those columns of point are constituted,
Column B in the regular grid near one of column A, and
Column C is in the regular grid with column A and column B non-colinear and near column A's
Another, and wherein all four sides length all having the same of the storage unit.
9. memory device according to claim 8, in which:
WithIt is two of four sides of the storage unit,Connect column A and column B,Connection
Column A and column C,OrThere is an angle, θ with those bit line conductors, and wherein
Tan (θ)=X/Y, wherein X and Y is the relatively prime integer of units.
10. memory device according to claim 1, wherein the storage unit is pushed up by four that are located at a parallelogram
Four column A, column B, column C and the column D of those columns of point are constituted,
Column B in the regular grid near one of column A, and
Column C is in the regular grid with column A and column B non-colinear and near column A's
Another, wherein
Those string selection lines include multiple rectangles, and there is those rectangles long spacing dimension arrangement position to lead to those bit lines are orthogonal to
Body, wherein
Those string selection lines and those bit line conductors have multiple crosspoints, and respectively the string selection line and each bit line conductors respectively should
Crosspoint individually distinguishes single of those columns, and wherein
Those strings specific one of selection lines are with a short Spatial Dimension and intersect in specific one of those storage units
At least column A and column B.
11. memory device according to claim 10, wherein this specific one of those string selection lines intersects at those
All four those columns in this specific one of storage unit.
12. memory device according to claim 10, wherein this specific one of those string selection lines intersects at those
Different and non-adjacent two of at least those columns in this specific one of storage unit.
13. a kind of in the memory device on a substrate characterized by comprising
One multiple-level stack has multiple conductive layers, and respectively the conductive layer arranges position to being parallel to the substrate；
Multiple columns arrange position to the substrate is orthogonal to, and respectively the column includes the memory cell of multiple series connections, those are deposited
Storage born of the same parents are located at multiple crosspoints of those columns Yu those conductive layers；
Multiple string selection lines, arrangement position is to being parallel to the substrate and being located on those conductive layers, and respectively the string selection line intersects at
The respectively different subset of the one of those columns, those columns and those string selection lines have multiple crosspoints, respectively the column
Respectively crosspoint of body and the respectively string selection line defines a selection gate of the respectively column respectively；And
Multiple bit line conductors parallel to each other are configured to one layer and are parallel to the substrate and are located on those string selection lines, respectively
The overlapped another respectively different subset in those columns of the bit line conductors, respectively the column is located at one of those bit line conductors
Under, and those string selection lines and those bit line conductors have multiple crosspoints, respectively the string selection line and each bit line conductors
Respectively the crosspoint individually distinguishes single of those columns,
Wherein those columns are configured on a regular grid, and there are two lateral Spatial Dimensions and a storage for regular grid tool
Unit, the storage unit by be located at four column A of those columns on four vertex of a parallelogram, column B,
Column C and column D is constituted,
Column B in the regular grid near one of column A, column C in the regular grid with the column
Shape body A and column B non-colinear and near column A another,Length be not equal toLength,
And wherein
Those strings specific one of selection lines are with a short Spatial Dimension and intersect in specific one of those storage units
At least column A and column B；
The regular grid is the grid that can be distinguished into consecutive storage unit.
14. memory device according to claim 13, wherein respectively the memory cell includes a vertical channel structure, a charge
Accumulation layer and an insulating layer.
15. memory device according to claim 13, wherein those Spatial Dimensions of the regular grid are not parallel to
It is non-orthogonal with those bit line conductors.
16. memory device according to claim 13, wherein every a pair in the regular grid, in those columns
The column is not aligned with each other on a Spatial Dimension of those parallel bit line conductors, and is being orthogonal to those bit line conductors
It is separated from each other in one horizontal space dimension and there is the distance at least more than d/10, wherein minimum Europe of the d between those columns
Ji Li obtains distance.
17. memory device according to claim 13, wherein the two spaces dimension of the regular grid is orthogonal.
18. memory device according to claim 17, wherein the regular grid is the grid that multiple squares are constituted,
And wherein
The regular grid rotates an angle, θ by tan (θ)=± X/Y relative to those bit line conductors, and wherein X and Y is relatively prime
Integer.
19. memory device according to claim 13, wherein all four sides of the storage unit are all having the same
Length.
20. memory device according to claim 19, the wherein storage unit it is any adjacent side is formed it is non-straight
Angle.
21. memory device according to claim 20, wherein the adjacent side shape of a pair of the storage unit is at an angle
60°。
22. memory device according to claim 21, wherein the regular grid is rotated relative to those bit line conductors, with
So that allAndBoth those bit line conductors are not parallel to or are non-orthogonal with, whereinAndFor four sides of the storage unit,Connect column A and column B,
Connect column A and column C,Connect column B and column C andConnect column A and
Column D.
23. memory device according to claim 19, in which:
The adjacent side of a pair of the storage unit forms right angle, and
OrThere is an angle, θ with those bit line conductors,WithIt is two of four sides of the storage unit,
Connect column A and column B,Column A and column C are connected, wherein
Tan (θ)=X/Y, wherein X and Y is relatively prime integer.
24. memory device according to claim 13, wherein this specific one of those string selection lines intersects at those
All four those columns in this specific one of storage unit.
25. memory device according to claim 13, wherein this specific one of those string selection lines intersects at those
Different and non-adjacent two of at least those columns in this specific one of storage unit.
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