CN106033756B - High-voltage ESD protective circuit - Google Patents
High-voltage ESD protective circuit Download PDFInfo
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- CN106033756B CN106033756B CN201510104607.9A CN201510104607A CN106033756B CN 106033756 B CN106033756 B CN 106033756B CN 201510104607 A CN201510104607 A CN 201510104607A CN 106033756 B CN106033756 B CN 106033756B
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Abstract
The present invention provides a kind of high-voltage ESD protective circuit, for the ESD electric current flowed by IO PAD of releasing, includes at least: the GDPMOS vent unit between supply voltage and the IO PAD；The auxiliary vent unit being connect with the GDPMOS vent unit between the IO PAD and ground, and the GGNMOS vent unit being connect with the auxiliary vent unit；Wherein, the auxiliary vent unit is released path to provide the auxiliary of the GGNMOS vent unit.The auxiliary that auxiliary vent unit of the invention is capable of providing the GGNMOS vent unit is released path, and ESD ability is improved；Using the stacked structure for being directed to high-pressure process, the ESD ability of circuit on the one hand can be improved, the trigger voltage and noise resisting ability of entire high-voltage ESD protective circuit on the other hand can be improved, the malfunction of entire high-voltage ESD protective circuit is caused so as to avoid noise.
Description
Technical field
The present invention relates to ESD technical fields, more particularly to a kind of high-voltage ESD protective circuit.
Background technique
ESD (Electro-Static discharge, static discharge) phenomenon causes the reliability of integrated circuit huge
Big to threaten, forming protection circuit using semiconductor devices in piece is the important means for improving ESD protection.Existing ESD protects electricity
Road be generally arranged in integrated circuit at the IO PAD (input/output pads) and voltage input port of main circuit.
In high-pressure process, common esd protection circuit is as shown in Figure 1, wherein due to the first high pressure NMOS pipe
The limitation of HVNMOS1 defect itself, ESD ability are lower than the first high voltage PMOS pipe HVPMOS1, are one in esd protection circuit
Block short slab causes the ESD ability of entire esd protection circuit poor, and such case in high-pressure process than more prominent.
In addition, the situation that this ESD ability for leading to entire esd protection circuit is poor, will cause the touching of esd protection circuit
Power generation pressure Vtrig (voltage at namely IO PAD) is relatively low.For high-tension circuit, if trigger voltage is lower, it would be possible to
Circuit leaky is caused, great security risk is brought.
In addition, many applications have certain requirement to the noise resisting ability of esd protection circuit in high-pressure process.If touching
Power generation pressure is lower, when noise reaches a certain size, it would be possible to cause the malfunction of esd protection circuit.
Therefore, how to improve the ESD ability of esd protection circuit, and improve trigger voltage and noise resisting ability, be the present invention
Urgent problem to be solved.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of high-voltage ESD protective circuits, use
Poor in the ESD ability for solving esd protection circuit in the prior art, the trigger voltage at IO PAD is lower and ESD protection is electric
The problem of noise resisting ability on road is poor, may cause malfunction.
In order to achieve the above objects and other related objects, the present invention provides a kind of high-voltage ESD protective circuit, for release by
The ESD electric current that IO PAD is flowed into, wherein the high-voltage ESD protective circuit includes at least:
GDPMOS vent unit between supply voltage and the IO PAD；
The auxiliary vent unit being connect with the GDPMOS vent unit between the IO PAD and ground, Yi Jiyu
The GGNMOS vent unit of the auxiliary vent unit connection；
Wherein, the auxiliary vent unit is released path to provide the auxiliary of the GGNMOS vent unit.
Preferably, the GGNMOS vent unit includes at least the first High voltage NMOS transistor, the auxiliary vent unit
Including at least the second High voltage NMOS transistor, first High voltage NMOS transistor is connected with second High voltage NMOS transistor
Form stacked structure.
Preferably, the auxiliary vent unit further includes parasitic gate-source capacitance；Wherein, the upper pole of the parasitic gate-source capacitance
Plate is connect with the grid of second High voltage NMOS transistor, the bottom crown of the parasitism gate-source capacitance and second high pressure
The source electrode of NMOS transistor is connected with the drain electrode of first High voltage NMOS transistor.
Preferably, second High voltage NMOS transistor is suitable for forming automatic biasing by the parasitic gate-source capacitance and lead
It is logical, as equivalent resistance increase, the trigger voltage at the IO PAD in the stacked structure.
Preferably, the auxiliary vent unit further includes the first parasitic triode, the first dead resistance, the second parasitic three poles
Pipe and the second dead resistance；Wherein, the drain electrode of second High voltage NMOS transistor and first parasitic triode and described
The collector of second parasitic triode connects, the emitter of first parasitic triode and second High voltage NMOS transistor
Source electrode connection, the base stage of first parasitic triode connect with one end of first dead resistance, first parasitism
The other end of resistance is connect with the source electrode of second High voltage NMOS transistor, and the emitter of second parasitic triode connects
Ground, the base stage of second parasitic triode are connect with one end of second dead resistance, second dead resistance it is another
One end ground connection.
Preferably, the GGNMOS vent unit further includes third parasitic triode and third dead resistance；Wherein, described
The drain electrode of first High voltage NMOS transistor is connect with the collector of the third parasitic triode, the third parasitic triode
Emitter is connect with the source electrode of first High voltage NMOS transistor, and base stage and the third of the third parasitic triode are posted
One end connection of raw resistance, the other end ground connection of the third dead resistance.
Preferably, the GGNMOS vent unit further includes GGNMOS bleeder resistance；Wherein, first high pressure NMOS is brilliant
The grid of body pipe is connect with one end of the GGNMOS bleeder resistance, the other end of the GGNMOS bleeder resistance and described first
The source electrode of High voltage NMOS transistor is grounded jointly.
Preferably, the GDPMOS vent unit includes at least the first high voltage PMOS transistor and GDPMOS bleeder resistance；
Wherein, the grid of first high voltage PMOS transistor is connect with one end of the GDPMOS bleeder resistance, and the GDPMOS is let out
The other end of electric discharge resistance and the source electrode of first high voltage PMOS transistor are connect with the supply voltage respectively, and described first is high
The drain electrode of pressure PMOS transistor is connect with the drain electrode of second High voltage NMOS transistor.
As described above, high-voltage ESD protective circuit of the invention, have the advantages that auxiliary of the invention is released list
The auxiliary that member is capable of providing the GGNMOS vent unit is released path, and ESD ability is improved；Utilize the heap for being directed to high-pressure process
On the one hand stack structure can be improved the ESD ability of circuit, the triggering of entire high-voltage ESD protective circuit on the other hand can be improved
Voltage and noise resisting ability cause the malfunction of entire high-voltage ESD protective circuit so as to avoid noise.
Detailed description of the invention
Fig. 1 is shown as present invention esd protection circuit schematic diagram in the prior art.
Fig. 2 is shown as the high-voltage ESD protective circuit schematic diagram of one embodiment of the invention.
Fig. 3 is shown as the equivalent schematic of the high-voltage ESD protective circuit of one embodiment of the invention.
Fig. 4 is shown as ghost effect schematic diagram in the high-voltage ESD protective circuit of one embodiment of the invention.
Component label instructions
10 GDPMOS vent units
20 auxiliary vent units
30 GGNMOS vent units
VDD supply voltage
IO IOPAD (input/output pads)
GND
Vtrig trigger voltage
The first high voltage PMOS transistor of HVPMOS1
The first High voltage NMOS transistor of HVNMOS1
The second High voltage NMOS transistor of HVNMOS2
RP1 GDPMOS bleeder resistance
RN1 GGNMOS bleeder resistance
Cgs parasitism gate-source capacitance Cgs
The first parasitic triode of NPN1
The second parasitic triode of NPN2
NPN3 third parasitic triode
The first dead resistance of RES1
The second dead resistance of RES2
RES3 third dead resistance
Req_HVNMOS2 equivalent resistance
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
As an embodiment of the present invention, the present embodiment is related to a kind of high-voltage ESD protective circuit, for releasing by IO
The ESD electric current that PAD is flowed into, please refers to Fig. 2~Fig. 4.It should be noted that diagram provided in the present embodiment is only with signal side
Formula illustrates basic conception of the invention, only shows with related component in the present invention rather than when according to actual implementation in schema then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
As shown in Fig. 2, the high-voltage ESD protective circuit of the present embodiment includes at least: be located at supply voltage VDD and IO PAD it
Between GDPMOS vent unit 10；The auxiliary connecting with GDPMOS vent unit 10 between IO PAD and ground GND is released
Unit 20, and the GGNMOS vent unit 30 being connect with auxiliary vent unit 20；Wherein, auxiliary vent unit 20 is to provide
The auxiliary of GGNMOS vent unit 30 is released path.
The present embodiment increases an auxiliary vent unit 20, can make up for it the first high pressure in the technology of the prior art
ESD ability NMOS transistor HVNMOS1 poor as caused by defect itself, provides for entire high-voltage ESD protective circuit
Other ESD electric current is released path, to enhance the ESD ability of entire high-voltage ESD protective circuit.
Please continue to refer to Fig. 2, in the present embodiment, GGNMOS vent unit 30 refers to the NMOS with grounded-grid GND
Vent unit, can release part ESD electric current.The GGNMOS vent unit 30 of the present embodiment includes at least the first high pressure NMOS
Transistor HVNMOS1, auxiliary vent unit 20 include at least the second High voltage NMOS transistor HVNMOS2, and the first high pressure NMOS is brilliant
Body pipe HVNMOS1 connects to form stacked structure with the second High voltage NMOS transistor HVNMOS2.
Also, referring to Fig. 4, auxiliary vent unit 20 further includes parasitic gate-source capacitance Cgs.Wherein, parasitic gate-source capacitance
The top crown of Cgs is connect with the grid of the second High voltage NMOS transistor HVNMOS2, the bottom crown of parasitic gate-source capacitance Cgs and
The drain electrode of the source electrode HVNMOS2 of two High voltage NMOS transistors and the first High voltage NMOS transistor HVNMOS1 connect.
Also, referring to Fig. 3, the second High voltage NMOS transistor HVNMOS2 is suitable for being formed certainly by parasitism gate-source capacitance Cgs
Biasing (self-bias) is simultaneously connected, as equivalent resistance Req_HVNMOS2, to make the triggering at IO PAD in stacked structure
Voltage Vtrig increases.
That is, parasitism gate-source capacitance Cgs is actually the grid of the second High voltage NMOS transistor HVNMOS2 itself
Source capacitor, the second High voltage NMOS transistor HVNMOS2 in the present embodiment form self-bias by the gate-source capacitance of its own.Second
After the conducting of high pressure NMOS crystal, the equivalent resistance Req_ that connected is equivalent at the drain electrode of the first high pressure NMOS crystal
HVNMOS2's (as shown in Figure 3), equivalent resistance Req_HVNMOS2 increases the trigger voltage so that at IO PAD
VtrigVtrig increases delta_V, and delta_V calculation formula is as follows:
Delta_V=Itrig*Req_HVNMOS2；
Wherein, Itrig is the trigger current of entire high-voltage ESD protective circuit.
Therefore, because equivalent resistance Req_HVNMOS2 is increased in stacked structure, correspondingly, at original IO PAD
Trigger voltage Vtrig is also improved, so that the noise resisting ability of entire high-voltage ESD protective circuit is also mentioned
Height avoids the malfunction that noise causes entire high-voltage ESD protective circuit.
Certainly, in other examples, auxiliary vent unit 20 can also be capable of forming equivalent resistance using other
Component, it is not limited to the second above-mentioned High voltage NMOS transistor HVNMOS2, as long as identical technical effect can be played i.e.
It can.
Please continue to refer to Fig. 4, assisting vent unit 20 further includes the first parasitic triode NPN1, the first dead resistance
RES1, the second parasitic triode NPN2 and the second dead resistance RES2.Wherein, the leakage of the second High voltage NMOS transistor HVNMOS2
Pole is connect with the collector of the first parasitic triode NPN1 and the second parasitic triode NPN2, the hair of the first parasitic triode NPN1
Emitter-base bandgap grading is connect with the source electrode of the second High voltage NMOS transistor HVNMOS2, and the base stage of the first parasitic triode NPN1 is parasitic with first
One end of resistance RES1 connects, the source electrode of the other end of the first dead resistance RES1 and the second High voltage NMOS transistor HVNMOS2
Connection, the emitter of the second parasitic triode NPN2 are grounded GND, the base stage and the second dead resistance of the second parasitic triode NPN2
One end of RES2 connects, and the other end of the second dead resistance RES2 is grounded GND.
Please continue to refer to Fig. 4, GGNMOS vent unit 30 further includes third parasitic triode NPN3 and third dead resistance
RES3.Wherein, the drain electrode of the first High voltage NMOS transistor HVNMOS1 is connect with the collector of third parasitic triode NPN3, the
The emitter of trixenie triode NPN3 is connect with the source electrode of the first High voltage NMOS transistor HVNMOS1, third parasitic triode
The base stage of NPN3 is connect with one end of third dead resistance RES3, and the other end of third dead resistance RES3 is grounded GND.
The ghost effect of stacked structure in through this embodiment can be seen that the second parasitic triode NPN2 and provide separately
Outer ESD electric current is released path, will be from the ESD electric current that the collector of the second parasitic triode NPN2 flows into from the second parasitic three poles
The emitter-trailing of pipe NPN2 enables stacked structure to effectively improve the ESD energy of entire high-voltage ESD protective circuit to ground GND
Power.Meanwhile second parasitic triode NPN2 also contribute to so that current distribution is more in the first High voltage NMOS transistor HVNMOS1
Uniformly, the defect for improving first High voltage NMOS transistor HVNMOS1 itself, improves the first High voltage NMOS transistor
The ESD ability of HVNMOS1 further improves the ESD ability of entire high-voltage ESD protective circuit.
Please continue to refer to Fig. 2~Fig. 4, the GGNMOS vent unit 30 in the present embodiment further includes GGNMOS bleeder resistance
RN1.Wherein, the grid of the first High voltage NMOS transistor HVNMOS1 is connect with one end of GGNMOS bleeder resistance RN1, GGNMOS
The source electrode of the other end of bleeder resistance RN1 and the first High voltage NMOS transistor HVNMOS1 are grounded GND jointly.
In the present embodiment, GDPMOS vent unit 10 refers to the list of releasing that the PMOS of supply voltage VDD is met with grid
Member, can release another part ESD electric current.Please continue to refer to Fig. 2~Fig. 4, GDPMOS vent unit 10 in the present embodiment to
It less include the first high voltage PMOS transistor HVPMOS1 and GDPMOS bleeder resistance RP1.Wherein, the first high voltage PMOS transistor
The grid of HVPMOS1 is connect with one end of GDPMOS bleeder resistance RP1, the other end of GDPMOS bleeder resistance RP1 and first high
The source electrode of pressure PMOS transistor HVPMOS1 is connect with supply voltage VDD respectively, the leakage of the first high voltage PMOS transistor HVPMOS1
Pole is connect with the drain electrode of the second High voltage NMOS transistor HVNMOS2.
The present embodiment is based on 0.5 μm of 5V/15V technique, and the raising of ESD ability is realized by the design and improvement of circuit,
It is changed without technique, therefore cost is relatively low, feasibility is higher.
In conclusion high-voltage ESD protective circuit of the invention, have the advantages that auxiliary of the invention is released list
The auxiliary that member is capable of providing the GGNMOS vent unit is released path, and ESD ability is improved；Utilize the heap for being directed to high-pressure process
On the one hand stack structure can be improved the ESD ability of circuit, the triggering of entire high-voltage ESD protective circuit on the other hand can be improved
Voltage and noise resisting ability cause the malfunction of entire high-voltage ESD protective circuit so as to avoid noise.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (6)
1. a kind of high-voltage ESD protective circuit, for the ESD electric current flowed by IO PAD of releasing, which is characterized in that the high pressure
Esd protection circuit includes at least:
GDPMOS vent unit between supply voltage and the IO PAD；
The auxiliary vent unit being connect with the GDPMOS vent unit between the IO PAD and ground, and
The GGNMOS vent unit being connected between the auxiliary vent unit and ground；
Wherein, the auxiliary vent unit is released path to provide the auxiliary of the GGNMOS vent unit；
The GGNMOS vent unit includes at least the first High voltage NMOS transistor, and the auxiliary vent unit includes at least second
High voltage NMOS transistor, first High voltage NMOS transistor connect to form stacking knot with second High voltage NMOS transistor
Structure；The auxiliary vent unit further includes the first parasitic triode, the first dead resistance, the second parasitic triode and the second parasitism
Resistance；Wherein, the drain electrode of second High voltage NMOS transistor and first parasitic triode and second parasitic three poles
The collector of pipe connects, and the emitter of first parasitic triode is connect with the source electrode of second High voltage NMOS transistor,
The base stage of first parasitic triode is connect with one end of first dead resistance, the other end of first dead resistance
It is connect with the source electrode of second High voltage NMOS transistor, the emitter ground connection of second parasitic triode, described second posts
The base stage of raw triode is connect with one end of second dead resistance, the other end ground connection of second dead resistance.
2. high-voltage ESD protective circuit according to claim 1, which is characterized in that the auxiliary vent unit further includes posting
Raw gate-source capacitance；Wherein, the top crown of the parasitic gate-source capacitance is connect with the grid of second High voltage NMOS transistor, institute
State the bottom crown of parasitic gate-source capacitance and the source electrode of second High voltage NMOS transistor and first High voltage NMOS transistor
Drain electrode connection.
3. high-voltage ESD protective circuit according to claim 2, which is characterized in that second High voltage NMOS transistor is suitable
In forming automatic biasing by the parasitic gate-source capacitance and be connected, described in, as equivalent resistance, making in the stacked structure
Trigger voltage at IO PAD increases.
4. high-voltage ESD protective circuit according to claim 1, which is characterized in that the GGNMOS vent unit further includes
Third parasitic triode and third dead resistance；Wherein, the drain electrode of first High voltage NMOS transistor and the third are parasitic
The collector of triode connects, and the source electrode of the emitter of the third parasitic triode and first High voltage NMOS transistor connects
Connect, the base stage of the third parasitic triode is connect with one end of the third dead resistance, the third dead resistance it is another
One end ground connection.
5. high-voltage ESD protective circuit according to any one of claims 1 to 4, which is characterized in that the GGNMOS releases list
Member further includes GGNMOS bleeder resistance；Wherein, the grid of first High voltage NMOS transistor and the GGNMOS bleeder resistance
One end connection, the other end of the GGNMOS bleeder resistance and the source electrode of first High voltage NMOS transistor are grounded jointly.
6. high-voltage ESD protective circuit according to any one of claims 1 to 4, which is characterized in that the GDPMOS releases list
Member includes at least the first high voltage PMOS transistor and GDPMOS bleeder resistance；Wherein, the grid of first high voltage PMOS transistor
Pole is connect with one end of the GDPMOS bleeder resistance, the other end of the GDPMOS bleeder resistance and first high voltage PMOS
The source electrode of transistor is connect with the supply voltage respectively, the drain electrode of first high voltage PMOS transistor and second high pressure
The drain electrode of NMOS transistor connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510104607.9A CN106033756B (en) | 2015-03-10 | 2015-03-10 | High-voltage ESD protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510104607.9A CN106033756B (en) | 2015-03-10 | 2015-03-10 | High-voltage ESD protective circuit |
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| CN106033756A CN106033756A (en) | 2016-10-19 |
| CN106033756B true CN106033756B (en) | 2019-03-19 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449637A (en) * | 2016-11-08 | 2017-02-22 | 中国电子科技集团公司第四十七研究所 | Electrostatic protection of input circuit Based on large-scale CMOS integrated circuit and method thereof |
| CN107039422A (en) * | 2016-12-06 | 2017-08-11 | 湘潭大学 | A kind of ESD full-chip protection circuit of integrated circuit |
| CN106992511A (en) * | 2017-05-30 | 2017-07-28 | 长沙方星腾电子科技有限公司 | A kind of ESD protection circuit |
| CN107786195B (en) * | 2017-12-01 | 2021-04-13 | 珠海亿智电子科技有限公司 | High-voltage-resistant high-speed IO circuit realized by using low-voltage device |
| CN109742070B (en) * | 2018-12-21 | 2021-07-30 | 中国电子科技集团公司第四十八研究所 | FDSOI silicon controlled rectifier electrostatic protection device |
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|---|---|---|---|---|
| CN1169799A (en) * | 1994-01-13 | 1998-01-07 | 爱特梅尔股份有限公司 | Electrostatic discharge circuit for high speed, high voltage cricuit |
| CN101882616A (en) * | 2008-12-31 | 2010-11-10 | 海力士半导体有限公司 | Integrated circuit |
| CN101944530A (en) * | 2010-08-27 | 2011-01-12 | 电子科技大学 | ESD protective circuit with control circuit for integrated circuit |
| CN103236431A (en) * | 2013-04-19 | 2013-08-07 | 陶野 | Secondary electrostatic protection circuit formed by memristor and having feature size being lower than 130nm |
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2015
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1169799A (en) * | 1994-01-13 | 1998-01-07 | 爱特梅尔股份有限公司 | Electrostatic discharge circuit for high speed, high voltage cricuit |
| CN101882616A (en) * | 2008-12-31 | 2010-11-10 | 海力士半导体有限公司 | Integrated circuit |
| CN101944530A (en) * | 2010-08-27 | 2011-01-12 | 电子科技大学 | ESD protective circuit with control circuit for integrated circuit |
| CN103236431A (en) * | 2013-04-19 | 2013-08-07 | 陶野 | Secondary electrostatic protection circuit formed by memristor and having feature size being lower than 130nm |
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Address after: 401331 No. 25 Xiyong Avenue, Shapingba District, Chongqing Applicant after: Huarun Microelectronics (Chongqing) Co., Ltd. Address before: 401331 No. 25 Xiyong Avenue, Xiyong Town, Shapingba District, Chongqing Applicant before: China Aviation (Chongqing) Microelectronics Co., Ltd. |
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