CN106033108A - Testing device - Google Patents
Testing device Download PDFInfo
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- CN106033108A CN106033108A CN201510103645.2A CN201510103645A CN106033108A CN 106033108 A CN106033108 A CN 106033108A CN 201510103645 A CN201510103645 A CN 201510103645A CN 106033108 A CN106033108 A CN 106033108A
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Abstract
A testing device comprises a testing interface, a converting chip and two nixie tubes. The testing interface can be connected with a mainboard through a low-pin-number bus for receiving testing data. The converting chip is electrically connected with the testing interface for receiving the testing data and converting the testing data to decimal data. The two nixie tubes are electrically connected with the converting chip for receiving the decimal data and displaying corresponding codes. The testing interface of the testing device is connected with the mainboard through the low-pin-number bus or a parallel bus for performing data transmission with the mainboard and transmitting tested data to the two nixie tubes, thereby quickly, conveniently and accurately acquiring error information of the mainboard.
Description
Technical field
The present invention relates to a kind of test device.
Background technology
Computer has become electronic product closely bound up in our daily life, and computer main board, in the R & D design stage, needs to test mainboard comprehensively, and to investigate fault, but existing test mode is cumbersome and fault detect is the most accurate.
Summary of the invention
In view of this, it is necessary to provide a kind of simplicity and fault detect to test device accurately.
A kind of test device, including a test interface, a conversion chip and two charactrons, described test interface can be connected with a mainboard by low pin count bus, to receive test data, described conversion chip electrically connects with described test interface, in order to receive described test data, and be decimal data by described test data conversion, described two charactrons electrically connect with described conversion chip, in order to receive described decimal data, and show respective code.
A kind of test device, including a test interface and two charactrons, described test interface is connected by parallel busses and a mainboard controller, to receive test data, this controller includes that Binary Conversion is metric compiler, described two charactrons electrically connect with described test interface, in order to receive described decimal data, and show respective code.
Compare prior art, the test interface of described test device is carried out data transmission with mainboard by low pin count bus or parallel bus with mainboard, and the data detected be delivered on two charactrons, thus get final product quick, convenient, to learn mainboard accurately error message.
Accompanying drawing explanation
Fig. 1 is the block diagram that the present invention tests the better embodiment of device.
Fig. 2 is the schematic diagram that the present invention tests the better embodiment of device.
Main element symbol description
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
Refer to Fig. 1, the present invention tests the conversion chip 20 that the better embodiment of device 100 includes a test interface 10, is connected with test interface 10, two charactrons 30 and 40 being connected with conversion chip 20.Described test device 100 is connected with a computer main board by described test interface 10, to detect the fault of computer main board.
Refer to Fig. 2, in the present embodiment, this test interface 10 is a trust platform module (Trusted Platform Modul, it is called for short TPM) adapter 120, this trust platform module connector 120 is connected by low pin count (Low Pin Count is called for short LPC) bus with mainboard south bridge, decreases number of pins, save sheet material space, convenient design and use.This trust platform module connector has 20 pins.These pins are defined as follows:
Certainly, in other embodiments, test interface 10 can also use MINI-PCIE interface 110 or a parallel port 130.Described MINI-PCIE interface 110 and parallel port 130 are respectively positioned on the different ends of described test device 100, and described MINI-PCIE interface 110 is used the communication modes of LPC, carried out data transmission with computer main board by lpc bus.This parallel port 130 is connected with printing terminal (Line Print Terminal the is called for short LPT) interface of the Super I/O control on mainboard, and there are 10 pins this parallel port 130.
Two charactrons 30,40 are seven-segment decoder, and this seven-segment decoder includes seven LED, represents with abcdefg respectively.
Conversion chip 20 is a BCD(Binary-Coded Decimal) conversion chip, the binary code that main frame transmits is converted to decimal scale, and is shown as metric two codes by two charactrons 30,40.
Two charactrons 30,40 can represent the state from 00-FF, and wherein verification form is as follows:
When mainboard is tested, when using trust platform module connector 120 to carry out data transmission with mainboard, it is the information in 0080H that conversion chip 20 reads I/O port address by LPC interface during switching on and shutting down, TPM adapter 120 is connected with mainboard by lpc bus, to receive the test data on mainboard, and these test data are converted to decimal digit by conversion chip 20, by controlling charactron 30, the low and high level of the seven-segment decoder abcdefg of 40 shows different states, user is by verification form, mainboard the opposite way round can be immediately arrived at, conveniently carry out error checking.Such as: when charactron 30,40 shows " 8 " and " A " respectively, then the level state of the seven-segment decoder a ~ g of charactron 30 is " 1111111 ", and the level state of the seven-segment decoder of charactron 40 correspondence is " 1110111 "；When charactron 30,40 shows " B " and " D " respectively, the level state of the seven-segment decoder a ~ g of charactron 30 is " 0011111 ", and the seven-segment decoder level state of charactron 40 correspondence is " 0111101 ".
When using MINI-PCIE interface 110 to carry out data transmission with mainboard, it is the information in 0080H that conversion chip 20 reads I/O port address by LPC interface during switching on and shutting down, MINI-PCIE interface 110 is connected with mainboard by lpc bus, to receive the test data on mainboard, and these test data are converted to decimal digit by conversion chip 20, different states is shown by controlling seven-segment decoder to charactron 30,40 output low and high level, user is by verification form, mainboard the opposite way round can be immediately arrived at, conveniently carry out error checking.
When using parallel port 130 to carry out data transmission with mainboard, it is metric compiler owing to including Binary Conversion inside the Super I/O control of mainboard, parallel port 130 directly with export low and high level to charactron 30,40 and control seven-segment decoder and show different states, go out corresponding error code, verify for user.
The present invention is tested the test interface 10 of device 100 and can be carried out data transmission with mainboard by lpc bus or parallel bus, and the data detected is delivered on two charactrons 30 and 40, thus gets final product quick, convenient, to learn mainboard accurately error message.
Claims (6)
1. a test device, including:
One test interface, can be connected with a mainboard by low pin count bus, to receive test data；
One conversion chip, electrically connects with test interface, in order to receive described test data, and is decimal data by this test data conversion, and
Two charactrons, electrically connect with described conversion chip, in order to receive described decimal data, and show respective code.
Test device the most as claimed in claim 1, it is characterised in that: this test interface is a MINI-PCIE interface.
Test device the most as claimed in claim 1, it is characterised in that: this test interface is a trust platform module connector.
Test device the most as claimed in claim 1, it is characterised in that: this two charactron is seven-segment decoder.
5. a test device, including:
One test interface, is connected by parallel busses and a mainboard controller, and to receive test data, this controller includes that Binary Conversion is metric compiler；
Two charactrons, electrically connect with described test interface, in order to receive described decimal data, and show respective code.
Test device the most as claimed in claim 5, it is characterised in that: this two charactron is seven-segment decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510103645.2A CN106033108A (en) | 2015-03-10 | 2015-03-10 | Testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510103645.2A CN106033108A (en) | 2015-03-10 | 2015-03-10 | Testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106033108A true CN106033108A (en) | 2016-10-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510103645.2A Pending CN106033108A (en) | 2015-03-10 | 2015-03-10 | Testing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106033108A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107423175A (en) * | 2017-06-29 | 2017-12-01 | 郑州云海信息技术有限公司 | Server test mounting seat and the measurement jig that server CPU module can be replaced |
-
2015
- 2015-03-10 CN CN201510103645.2A patent/CN106033108A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107423175A (en) * | 2017-06-29 | 2017-12-01 | 郑州云海信息技术有限公司 | Server test mounting seat and the measurement jig that server CPU module can be replaced |
| CN107423175B (en) * | 2017-06-29 | 2021-02-02 | 苏州浪潮智能科技有限公司 | Mounting base for server test and test fixture capable of replacing server GPU module |
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Legal Events
| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161019 |
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| WD01 | Invention patent application deemed withdrawn after publication |