CN106024904A - Self-aligned GaAs-PMOS device structure - Google Patents

Self-aligned GaAs-PMOS device structure Download PDF

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CN106024904A
CN106024904A CN201610613952.XA CN201610613952A CN106024904A CN 106024904 A CN106024904 A CN 106024904A CN 201610613952 A CN201610613952 A CN 201610613952A CN 106024904 A CN106024904 A CN 106024904A
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layer
type
gaas
ohmic contact
pmos device
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CN106024904B (en
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王勇
王瑛
丁超
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Guangdong University of Technology
Dongguan South China Design and Innovation Institute
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Guangdong University of Technology
Dongguan South China Design and Innovation Institute
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a self-aligned GaAs channel PMOS device structure which comprises an N type GaAs channel layer, an InGaP etching stop layer on the source end of the N type GaAs channel layer, a P type GaAs ohmic contact layer on the InGaP etching stop layer, a source end metal electrode formed on the P type GaAs ohmic contact layer, an alumina oxide dielectric layer on the N type GaAs channel layer and the source end material layer, a gate metal electrode formed on the alumina oxide dielectric layer, a P type ohmic contact region formed on the N type GaAs channel layer, and a drain end metal electrode formed on the P type ohmic contact region.

Description

A kind of autoregistration GaAs-PMOS device architecture
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, be specifically related to a kind of autoregistration arsenic Change gallium PMOS device structure, be applied to high-performance III V race semiconductor CMOS technology.
Background technology
For III V compound semiconductor materials are relative to silicon materials, there is high carrier mobility, big The advantage such as energy gap, and have excellent characteristics at aspects such as calorifics, optics and electromagnetism. Lack and the PMOS device that matches of nmos device is always III V race quasiconductor on a large scale One of major obstacle of application in CMOS integrated circuit.Current research report shows: source and drain is parasitic Resistance is greatly the key factor affecting III V PMOS device performance boost.Accordingly, it would be desirable to it is a kind of New approach realizes self aligned PMOS device on III V race semiconductor device structure, reduces The source and drain dead resistance of PMOS device, improves device performance, to meet high-performance III V race quasiconductor The requirement of CMOS technology.
Summary of the invention
(1) to solve the technical problem that
The main object of the present invention is to provide a kind of autoregistration GaAs PMOS device structure, with reality The now autoregistration PMOS device with GaAs channel material, it is achieved be ditch with high electron mobility The III V race semiconductor N MOS device of road material matches, and meets high-performance III V race quasiconductor The requirement of CMOS technology.
(2) technical scheme
For reaching above-mentioned purpose, the invention provides a kind of autoregistration GaAs PMOS device structure. Its structure is followed successively by:
One N-type gallium arsenide channel layer；
One InGaP in this N-type gallium arsenide channel layer source etches cutoff layer；
The one p-type GaAs ohmic contact layer on this InGaP etching cutoff layer；
The one source metal electrode formed on this p-type GaAs ohmic contact layer；
The one alumina medium layer on this N-type gallium arsenide channel layer with source material layer；
The one grid metal electrode formed on this alumina medium layer；
The one p-type ohmic contact regions formed on this N-type gallium arsenide channel layer；
The one drain terminal metal electrode formed on this p-type ohmic contact regions.
In such scheme, described InGaP etching cutoff layer is n-type doping, and doping content is 3 ×1017cm‐3；
In such scheme, described InGaP etching cutoff layer thickness is 2 nanometers；
In such scheme, described InGaP etch media layer thickness, grid medium thickness and grid gold The actual grid that genus width determines PMOS device are long；
In such scheme, the thickness of described p-type GaAs ohmic contact layer is 100 nanometers；
In such scheme, described source ohmic contact layer and the etching of InGaP etching cutoff layer Angle is 80 85 degree；
In such scheme, described grid metal electrode is the sidewall structure of etching.
(3) beneficial effect
From technique scheme it can be seen that the method have the advantages that
A kind of GaAs channel PMOS device structure that the present invention provides, utilizes GaAs Ohmic contact Layer and the steep property etched surface of InGaP etching cutoff layer, it is achieved gate medium and the steep quarter of grid metal Integrated on erosion face；The integrated of side wall technique is passed through at steep etched surface, it is achieved device by grid metal Effective control of part grid length；By drain terminal autoregistration ion implanting, it is achieved the fall of drain terminal dead resistance Low；So inventing this GaAs channel PMOS device structure, it is possible to achieve at GaAs channel PMOS Grid length on device reduces two large effects with source and drain dead resistance, thus meets high-performance III V race The requirement of semiconductor CMOS technology.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the GaAs raceway groove autoregistration PMOS device structure that the present invention provides；
Fig. 2 is the enforcement illustration of the GaAs raceway groove autoregistration PMOS device structure that the present invention provides；
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specifically Embodiment, and referring to the drawings 2, the present invention is described in more detail.
As in figure 2 it is shown, present embodiments provide a kind of gallium arsenide channel autoregistration PMOS device knot Structure.Its structure is followed successively by:
One N-type gallium arsenide channel layer (201)；
One InGaP etching cutoff layer (202) in this N-type gallium arsenide channel layer source；
The one p-type GaAs ohmic contact layer (203) on this InGaP etching cutoff layer (202)；
One at the upper source metal electrode (206) formed of this p-type GaAs ohmic contact layer (203)；
The one alumina medium layer (204) on this N-type gallium arsenide channel layer with source material layer；
One at the upper grid metal electrode (205) formed of this alumina medium layer (204)；
One in the upper p-type ohmic contact regions (201 D) formed of this N-type gallium arsenide channel layer (201)；
One at this p-type ohmic contact regions (201 D) the upper drain terminal metal electrode (206) formed.
In the present embodiment, described gallium arsenide channel layer is to use on semi-insulating GaAs substrate MBE or MBE growth, before growth channel layer, semi-insulating GaAs substrate is carried out surface Clean；
In the present embodiment, the thickness of gallium arsenide channel is 100 nanometers；
In the present embodiment, described InGaP etching cutoff layer is n-type doping, and impurity is Silicon, doping content is 3 × 1017cm‐3；
In the present embodiment, described InGaP etching cutoff layer thickness is 2 nanometers；
In the present embodiment, the thickness of described p-type GaAs ohmic contact layer is 100 nanometers；
In the present embodiment, described source ohmic contact layer and the etching of InGaP etching cutoff layer Angle is 80 85 degree；
In the present embodiment, described alumina medium thickness is 3 nanometers；
In the present embodiment, described grid metal is tungsten metal, uses the method integration of sputtering to being somebody's turn to do In structure, and the method using ICP to etch forms sidewall structure；
In the present embodiment, described drain terminal ion implanted region (101 D) uses ion injection method to exist Drain terminal is formed, and injects edge and aligns with grid metal edge；
In the present embodiment, described InGaP etch media layer thickness, grid medium thickness and grid gold The actual grid that genus width determines PMOS device are long；
In the present embodiment, described source and drain metal electrode uses electron-beam evaporation mode in p-type On GaAs material, deposition forms, and metal level is Pt/Ti/Pt/Au.
Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect Further describe, be it should be understood that the specific embodiment that the foregoing is only the present invention , be not limited to the present invention, all within the spirit and principles in the present invention, that is done appoints What amendment, equivalent, improvement etc., should be included within the scope of the present invention.

Claims (7)

1. an autoregistration GaAs channel PMOS device structure, its structure is as follows:
One N-type gallium arsenide channel layer；
One InGaP in this N-type gallium arsenide channel layer source etches cutoff layer；
The one p-type GaAs ohmic contact layer on this InGaP etching cutoff layer；
The one source metal electrode formed on this p-type GaAs ohmic contact layer；
The one alumina medium layer on this N-type gallium arsenide channel layer with source material layer；
The one grid metal electrode formed on this alumina medium layer；
The one p-type ohmic contact regions formed on this N-type gallium arsenide channel layer；
The one drain terminal metal electrode formed on this p-type ohmic contact regions.
A kind of autoregistration GaAs channel PMOS device structure the most according to claim 1, it is characterised in that this InGaP etching cutoff layer is n-type doping, and doping content is 3 × 1017cm-3。
A kind of autoregistration GaAs channel PMOS device structure the most according to claim 1, its characteristic is that this InGaP etching cutoff layer thickness is 2 nanometers.
A kind of autoregistration GaAs channel PMOS device structure the most according to claim 1, it is characterised in that the actual grid that this InGaP etch media layer thickness, grid medium thickness and grid metal width determine this device are long.
A kind of autoregistration GaAs channel PMOS device structure the most according to claim 1, it is characterised in that the thickness of this p-type GaAs ohmic contact layer is 100 nanometers.
A kind of autoregistration GaAs channel PMOS device structure the most according to claim 1, it is characterised in that the etching angle of this p-type GaAs ohmic contact layer is 80-85 degree.
A kind of autoregistration GaAs channel PMOS device structure the most according to claim 1, it is characterised in that this grid metal electrode is the sidewall structure of etching.
CN201610613952.XA 2016-07-29 2016-07-29 A kind of autoregistration GaAs-PMOS device architecture Active CN106024904B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911478A (en) * 2019-10-22 2020-03-24 清华大学 Two-dimensional thin film field effect transistor with sub-1 nm gate length

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190576A (en) * 1992-01-16 1993-07-30 Fujitsu Ltd Semiconductor device
CN1507074A (en) * 2002-11-26 2004-06-23 Nec化合物半导体器件株式会社 Heterojunction field effect type semiconductor device and producing method thereof
US20050104087A1 (en) * 2003-11-19 2005-05-19 Lan Ellen Y. InGaP pHEMT device for power amplifier operation over wide temperature range
CN101399285A (en) * 2007-09-25 2009-04-01 恩益禧电子股份有限公司 Field-effect transistor, semiconductor chip and semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190576A (en) * 1992-01-16 1993-07-30 Fujitsu Ltd Semiconductor device
CN1507074A (en) * 2002-11-26 2004-06-23 Nec化合物半导体器件株式会社 Heterojunction field effect type semiconductor device and producing method thereof
US20050104087A1 (en) * 2003-11-19 2005-05-19 Lan Ellen Y. InGaP pHEMT device for power amplifier operation over wide temperature range
CN101399285A (en) * 2007-09-25 2009-04-01 恩益禧电子股份有限公司 Field-effect transistor, semiconductor chip and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911478A (en) * 2019-10-22 2020-03-24 清华大学 Two-dimensional thin film field effect transistor with sub-1 nm gate length
CN110911478B (en) * 2019-10-22 2021-01-05 清华大学 Two-dimensional thin film field effect transistor with sub-1 nm gate length

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