CN106024806B - Thin film transistor structure, display panel and control method thereof - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 101
- 238000002161 passivation Methods 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000010408 film Substances 0.000 claims description 15
- 239000004973 liquid crystal related substance Substances 0.000 claims description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
The invention relates to a thin film transistor structure, a display panel and a control method thereof, and belongs to the technical field of display. The thin film transistor structure includes: a substrate base plate on which a gate is formed; forming a source drain metal pattern on the substrate base plate with the grid, wherein the source drain metal pattern comprises: a source and a drain; a passivation layer is formed on the substrate with the active drain metal pattern, and at least two through holes are formed on the passivation layer above the drain; and a pixel electrode is formed on the substrate base plate with the passivation layer, and the pixel electrode is connected with the drain electrode through at least two through holes. The invention solves the problem of poor display effect of the display panel and improves the display effect of the display panel. The invention is used for the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor structure, a display panel and a control method of the thin film transistor structure.
Background
The display panel comprises an array substrate and a color film substrate which are formed in a box-to-box mode, and liquid crystal located between the array substrate and the color film substrate. The color Film substrate comprises a common electrode, and the array substrate comprises a plurality of Thin Film Transistors (TFT) structures which are arranged in an array.
Each TFT structure may include a gate electrode connected to the gate line, a source electrode connected to the data line, a passivation layer formed on the drain electrode, and a via hole (via) formed on the passivation layer, wherein the drain electrode may be connected to the pixel electrode through the via hole on the passivation layer. Applying a sufficient gate voltage on the gate line to write a control voltage on the data line from the source and drain electrodes to the pixel electrode; the array substrate further includes a common electrode line, the common electrode line is connected to a common electrode in the color filter substrate, and a common voltage is applied to the common electrode line, so that the common voltage can be written into the common electrode. The liquid crystal between the pixel electrode and the common electrode can deflect under the action of the control voltage on the pixel electrode and the common voltage on the common electrode, the transmittance of the liquid crystal is changed, and then the area corresponding to the pixel electrode on the display panel is controlled to display preset colors, so that the display panel displays images.
In the related art, the pixel electrode in each TFT structure is connected to the drain electrode only through a small via hole, and the pixel electrode and the drain electrode are easily in poor contact, so that the control voltage on the data line cannot be written into the pixel electrode through the source electrode and the drain electrode, and further, the area corresponding to the pixel electrode on the display panel cannot display the preset color, and thus, the display effect of the display panel is poor.
Disclosure of Invention
In order to solve the problem of poor display effect of a display panel, embodiments of the present invention provide a thin film transistor structure, a display panel and a control method thereof. The technical scheme is as follows:
in a first aspect, a thin film transistor structure is provided, the thin film transistor structure comprising: a substrate base plate, a first substrate base plate,
a grid electrode is formed on the substrate base plate;
forming a source drain metal pattern on the substrate base plate on which the grid is formed, wherein the source drain metal pattern comprises: a source and a drain;
a passivation layer is formed on the substrate with the source and drain metal patterns, and at least two through holes are formed on the passivation layer above the drain;
and a pixel electrode is formed on the substrate base plate on which the passivation layer is formed, and the pixel electrode is connected with the drain electrode through the at least two through holes.
Optionally, the source and drain metal pattern includes: the transistor comprises n source electrodes and n drain electrodes, wherein n is an integer greater than or equal to 2, and at least one through hole is formed in the passivation layer above each drain electrode in the n drain electrodes.
Optionally, a via hole is formed on the passivation layer above each of the n drain electrodes.
Optionally, the pixel electrode includes n pixel sub-electrodes, any two adjacent pixel sub-electrodes of the n pixel sub-electrodes are connected to each other, and the n pixel sub-electrodes are connected to the n drains one by one through n vias.
Optionally, the pixel electrode includes n pixel sub-electrodes, the n pixel sub-electrodes are insulated from each other, and the n pixel sub-electrodes are connected to the n drains one by one through n via holes.
Optionally, a gate line connected to the gate electrode and data lines connected to the n source electrodes are further formed on the substrate,
wherein, the orthographic projection of the grid line on the pixel electrode is positioned on the pixel electrode.
Optionally, each of the n pixel sub-electrodes is formed with m slits, where m is an integer greater than or equal to 2.
Optionally, said n is equal to 2,
the n pixel sub-electrodes are arranged in an axisymmetric mode, and the symmetry axis is the orthographic projection of the grid line on the pixel electrode;
the m slits have at least 2 slit directions.
Optionally, a gate insulating layer is formed on the substrate base plate on which the gate electrode is formed;
an amorphous silicon layer is formed on the substrate with the gate insulating layer;
an ohmic contact layer is formed on the substrate with the amorphous silicon layer;
and the source and drain metal patterns are formed on the substrate base plate on which the ohmic contact layer is formed.
In a second aspect, there is provided a display panel comprising: an array substrate and a color film substrate which are formed in a box-to-box mode, and liquid crystal positioned between the array substrate and the color film substrate,
the array substrate includes: the color film substrate comprises a common electrode, and in the plurality of thin film transistor structures, a gate line in at least one thin film transistor structure is connected with the common electrode.
In a third aspect, there is provided a method for controlling a display panel, where the display panel is the display panel of the second aspect, the method including:
inputting grid voltage to the grids in different thin film transistor structures through the grid lines in different thin film transistor structures at different time periods;
and inputting a common voltage to the common electrode through a gate line in a target thin film transistor structure during a period when a gate voltage is not input to a gate electrode in the target thin film transistor structure, wherein the target thin film transistor is any one of the at least one thin film transistor.
In summary, the present invention provides a thin film transistor structure, a display panel and a control method thereof, in the thin film transistor structure, a gate electrode, a source/drain metal pattern, a passivation layer and a pixel electrode are formed on a substrate, at least two via holes are formed on the passivation layer, and the pixel electrode can be connected to a drain electrode on the substrate through the at least two via holes on the passivation layer. When one of the at least two via holes fails, the pixel electrode can be connected with the drain electrode on the substrate through the other via holes of the at least two via holes, and the control voltage on the data line is written into the pixel electrode, so that the area corresponding to the pixel electrode can display the preset color on the display panel where the thin film transistor structure is located, and the display effect of the display panel is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to illustrate the embodiments of the present invention more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being apparent that the drawings in the following description are only some embodiments of the invention, and that other drawings may be derived from those drawings by a person skilled in the art without inventive effort.
Fig. 1-1 is a top view of a thin film transistor according to an embodiment of the present invention;
fig. 1-2 are cross-sectional views of a thin film transistor according to an embodiment of the present invention;
fig. 2-1 is a top view of another thin film transistor provided in an embodiment of the present invention;
fig. 2-2 is a cross-sectional view of another thin film transistor provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a pixel electrode according to an embodiment of the present invention;
fig. 4-1 is a schematic partial structure diagram of a thin film transistor according to an embodiment of the present invention;
fig. 4-2 is a schematic partial structure diagram of another thin film transistor according to an embodiment of the present invention;
fig. 4-3 is a schematic partial structure diagram of another thin film transistor according to an embodiment of the present invention;
fig. 4-4 are schematic partial structural diagrams of another thin film transistor according to an embodiment of the present invention;
fig. 4-5 are schematic partial structural diagrams of a thin film transistor according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1-1 is a top view of a thin film transistor structure provided in an embodiment of the present invention, fig. 1-2 is a cross-sectional view of a thin film transistor provided in an embodiment of the present invention, and fig. 1-2 may be a cross-sectional view of the thin film transistor structure in fig. 1-1 at BB', for example. Referring to fig. 1-1 and 1-2, the thin film transistor structure 0 may include: a substrate base plate 01, wherein a grid 02 is formed on the substrate base plate 01; a source/drain metal pattern 03 is formed on the substrate 01 on which the gate electrode 02 is formed, and the source/drain metal pattern 03 may include, for example: source 031 and drain 032;
a passivation layer 04 is formed on the substrate 01 on which the active drain metal pattern 03 is formed, and at least two via holes a are formed on the passivation layer 04 above the drain 031; a pixel electrode 05 is formed on the substrate 01 having the passivation layer 04 formed thereon, and the pixel electrode 05 is connected to the drain electrode 031 through at least two via holes a formed on the passivation layer 04.
In summary, in the thin film transistor structure provided in the embodiments of the present invention, the substrate is formed with the gate, the source-drain metal pattern, the passivation layer and the pixel electrode, the passivation layer is formed with at least two via holes, and the pixel electrode can be connected to the drain electrode on the substrate through the at least two via holes on the passivation layer. When one of the at least two via holes fails, the pixel electrode can be connected with the drain electrode on the substrate through the other via holes of the at least two via holes, and the control voltage on the data line is written into the pixel electrode, so that the area corresponding to the pixel electrode can display the preset color on the display panel where the thin film transistor structure is located, and the display effect of the display panel is improved.
Optionally, the source/drain metal pattern 03 may include: n sources 031 and n drains 032, where n is an integer greater than or equal to 2, and at least one via a may be formed on the passivation layer 04 above each drain 032 of the n drains 032, and for example, one via a may be formed on the passivation layer 04 above each drain 031 of the n drains 031.
It should be noted that, in the embodiment of the present invention, n is equal to 2, and one via a may be formed on the passivation layer 04 above each drain 031 in the n drain 031 (that is, n via a are formed on the passivation layer 04, and the number of the via a on the passivation layer 04 is equal to the number of the drain 031), in practical applications, n may also be another integer greater than 2, and the number of the via a on the passivation layer above each drain in the n drain 031 may also be another integer greater than 1, which is not limited in this embodiment of the present invention.
Fig. 2-1 is a top view of a tft structure provided in an embodiment of the present invention, fig. 2-2 is a cross-sectional view of an example of a tft structure provided in an embodiment of the present invention, and fig. 2-2 may be a cross-sectional view of the tft structure in fig. 2-1 at BB'.
Referring to fig. 2-1 and 2-2, the pixel electrode 05 may include n pixel sub-electrodes 051, any two adjacent pixel sub-electrodes 051 in the n pixel sub-electrodes 051 are connected to each other, and the n pixel sub-electrodes 051 may be connected to the n drains 032 through the n vias a. That is, the n pixel sub-electrodes 051 are connected with each other to form one electrode, and the one electrode is connected with the n drain electrodes 032 through the n through holes. And because any two pixel sub-electrodes 051 in the n pixel sub-electrodes 051 are mutually connected, when a certain via hole A fails, the pixel sub-electrode 051 connected with the failed via hole A can acquire voltage through the drain electrode 032 connected with other pixel sub-electrodes 051 through other pixel sub-electrodes 051.
It should be noted that the thin film transistor structures arranged in an array may form an array substrate in the display panel, the display panel may further include a color film substrate disposed opposite to the array substrate, and a liquid crystal located between the array substrate and the color film substrate, the color film substrate may be formed with a common electrode, and the liquid crystal may be deflected under the action of a voltage on the common electrode and a voltage on the pixel electrode.
In the related art, the tft structure may further include a Common electrode line (also referred to as Common line) formed on the substrate, and the Common electrode line may be connected to a Common electrode on the color filter substrate, and when a voltage needs to be input to the Common electrode, the voltage may be input to the Common electrode through the Common electrode line. And the orthographic projection of the common electrode line on the pixel electrode can be positioned on the pixel electrode, and the common electrode line and the pixel electrode can form a storage capacitor. However, since the common electrode line in the related art is narrow, the common electrode line is easily broken, so that a voltage cannot be input to the common electrode, and liquid crystal between the array substrate and the color film substrate cannot be effectively deflected.
In the embodiment of the present invention, a gate line 1 connected to the gate electrode 02 and data lines 2 connected to the n source electrodes 031 may be further formed on the substrate 01. For example, the 2 pixel sub-electrodes 051 in the embodiment of the present invention may be arranged in an axisymmetric manner, and the symmetry axis may be an orthogonal projection of the gate line 1 on the pixel electrode 05. That is, a common electrode line is not formed on the substrate 01, and the gate line 1 on the substrate 01 may be connected to a common electrode on the color filter substrate, so as to input a voltage to the common electrode instead of the common electrode line in the related art, and an orthographic projection of the gate line 1 on the pixel electrode 05 may be located on the pixel electrode 05, so that the gate line 1 may also form a storage capacitor instead of the common electrode line and the pixel electrode 05 in the related art. And because the grid line 1 is wider than the public electrode line in the related art, the grid line 1 is less prone to fracture, and therefore, voltage can be effectively input to the public electrode, and normal deflection of liquid crystal is guaranteed.
Further, m slits X may be formed on each pixel sub-electrode 051 of the n pixel sub-electrodes 051, the m slits X have at least 2 kinds of slit directions, and m is an integer greater than or equal to 2. Specifically, each pixel sub-electrode 051 can be provided with m slits X, and the m slits X can promote liquid crystal between the substrate and the color film substrate to have at least two deflection angles, so that the brightness difference of the display panel during display can be reduced and the color difference of the display panel during display can be reduced by combining the averaging effect of liquid crystal orientation at different viewing angles of the display panel, thereby improving the quality of the display image of the display panel.
A gate insulating layer 06 may be formed on the substrate base 01 on which the gate electrode 02 is formed; an amorphous silicon layer 07 may be formed on the substrate 01 on which the gate insulating layer 06 is formed; an ohmic contact layer 08 may be formed on the substrate base plate 01 on which the amorphous silicon layer 07 is formed; the source and drain metal patterns 03 may be formed on the substrate base 01 on which the ohmic contact layer 08 is formed.
Optionally, fig. 3 is a top view of a pixel electrode 05 according to an embodiment of the present invention, as shown in fig. 3, the pixel electrode 05 may further include n pixel sub-electrodes 051, the n pixel sub-electrodes 051 are insulated from each other, the n pixel sub-electrodes are connected to the n drains one by one through n vias, for example, in fig. 3, the pixel electrode 05 includes 2 pixel sub-electrodes 051 insulated from each other, and in practical application, the number of the pixel sub-electrodes 051 that the pixel electrode 05 may further include may be greater than 2. Since the n pixel sub-electrodes 051 are insulated from each other, when the via hole A corresponding to a certain pixel sub-electrode 051 fails, the area corresponding to the pixel sub-electrode 051 on the display panel cannot display the preset color, but the areas corresponding to other pixel sub-electrodes 051 on the display panel can display the preset color, and the area of each pixel sub-electrode 051 in the invention is smaller than that of the pixel electrode in the related technology, so that the area of the area which cannot display the preset color on the display panel can be reduced, and the display effect of the display panel is improved.
For example, as shown in fig. 4-1, in forming the thin film transistor structure, a gate electrode 02 may be first formed on a substrate base substrate 01; then, as shown in fig. 4-2, a gate insulating layer 06, an amorphous silicon layer 07, and an ohmic contact layer 08 may be sequentially formed on the substrate base 01 on which the gate electrode 02 is formed. As shown in fig. 4-3, a source and drain metal pattern 03 may be formed on the substrate 01 on which the ohmic contact layer 08 is formed, and the source and drain metal pattern 03 may include n sources 031 and n drains 032; as shown in fig. 4 to 4, a passivation layer 04 may be formed on the substrate base 01 on which the active drain metal pattern 03 is formed, wherein one via a may be formed on the passivation layer 04 above each drain 031; as shown in fig. 4 to 5, a pixel electrode 05 may be formed on the substrate base 01 on which the passivation layer 04 is formed, the pixel electrode 05 may be connected to at least two drain electrodes 031 through at least two via holes a formed on the passivation layer 04, and at least two slits X may be formed on each pixel sub-electrode 051.
It should be noted that, when the gate electrode is formed on the substrate, the gate line connected to the gate electrode may be formed on the substrate at the same time, and when the source/drain metal pattern is formed on the substrate, the data line may be formed on the substrate at the same time, and the data line may be connected to n source electrodes in the source/drain metal pattern.
In summary, in the thin film transistor structure provided in the embodiments of the present invention, the substrate is formed with the gate, the source-drain metal pattern, the passivation layer and the pixel electrode, the passivation layer is formed with at least two via holes, and the pixel electrode can be connected to the drain electrode on the substrate through the at least two via holes on the passivation layer. When one of the at least two via holes fails, the pixel electrode can be connected with the drain electrode on the substrate through the other via holes of the at least two via holes, and the control voltage on the data line is written into the pixel electrode, so that the area corresponding to the pixel electrode can display the preset color on the display panel where the thin film transistor structure is located, and the display effect of the display panel is improved.
As shown in fig. 5, an embodiment of the present invention provides a display panel 5, where the display panel 5 may include: the liquid crystal display panel comprises an array substrate 51 and a color filter substrate 52 which are formed in a box-to-box mode, and liquid crystals 53 positioned between the array substrate 51 and the color filter substrate 52.
The array substrate 51 may include a plurality of thin film transistor structures 0 arranged in an array, and the thin film transistor structure 0 may be the thin film transistor structure 0 shown in fig. 1-1, fig. 1-2, fig. 2-1, or fig. 2-2. The color filter substrate 52 may include a substrate 521 and a common electrode 522, and in the plurality of thin film transistor structures 0 in the array substrate 51, the gate line in at least one thin film transistor structure 0 is connected to the common electrode 522.
Further, the display device on which the display panel 5 is located may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
In summary, in the thin film transistor structure in the display panel provided in the embodiment of the present invention, the substrate is formed with the gate electrode, the source-drain metal pattern, the passivation layer and the pixel electrode, the passivation layer is formed with at least two via holes, and the pixel electrode can be connected to the drain electrode on the substrate through the at least two via holes on the passivation layer. When one of the at least two via holes fails, the pixel electrode can be connected with the drain electrode on the substrate through other via holes of the at least two via holes, and the control voltage on the data line is written into the pixel electrode, so that the area corresponding to the pixel electrode on the display panel where the array substrate is located can display the preset color, and the display effect of the display panel is improved.
An embodiment of the present invention provides a control method for a display panel, where the display panel may be the display panel 5 shown in fig. 5, and the control method for the display panel may include:
inputting grid voltage to the grids in different thin film transistor structures through the grid lines in different thin film transistor structures at different time periods; and inputting a common voltage to the common electrode through the gate line in the target thin film transistor structure during a period in which the gate voltage is not input to the gate electrode in the target thin film transistor structure, wherein the target thin film transistor is any one of the at least one thin film transistor.
For example, the plurality of thin film transistors may include: thin film transistor structure 1, thin film transistor structure 2, thin film transistor structure 3, thin film transistor structure 4, and thin film transistor structure 5. Wherein, the gate lines in the thin film transistor structure 2 and the thin film transistor structure 5 are connected to the common electrode.
When the display panel is controlled, gate voltages may be sequentially input to the gates in the plurality of thin film transistor structures, and specifically, when a gate voltage is input to the gate in the thin film transistor structure 1 (at this time, a gate voltage is not input to the gate in the transistor structure 2 or the transistor structure 5 connected to the common electrode), a common voltage may also be input to the common electrode through a gate line in a target transistor structure (such as the transistor structure 2 or the transistor structure 5); when a gate voltage is input to the thin film transistor structure 2 (at this time, the gate voltage is not input to the gate electrode in the transistor structure 5 connected to the common electrode), a common voltage may also be input to the common electrode through a gate line in a target transistor structure (e.g., the transistor structure 5); when a gate voltage is input to the thin film transistor structure 3 (at this time, the gate voltage is not input to the gate electrode in the transistor structure 2 or the transistor structure 5 connected to the common electrode), a common voltage may also be input to the common electrode through a gate line in a target transistor structure (e.g., the transistor structure 2 or the transistor structure 5); when a gate voltage is input to the thin film transistor structure 4 (at this time, the gate voltage is not input to the gate electrode in the transistor structure 2 or the transistor structure 5 connected to the common electrode), a common voltage may also be input to the common electrode through a gate line in a target transistor structure (e.g., the transistor structure 2 or the transistor structure 5); when a gate voltage is input to the thin film transistor structure 5 (at this time, the gate voltage is not input to the gate electrode in the transistor structure 2 connected to the common electrode), a common voltage may also be input to the common electrode through the gate line in the target transistor structure (e.g., the transistor structure 2).
For example, an Array substrate line driver (GOA) circuit may be used to input Gate voltages to gates of different tft structures at different time periods. Specifically, when the clock signal of the GOA circuit is at a high level, the GOA circuit may input a gate voltage to a gate electrode of a certain thin film transistor structure through a gate line of the thin film transistor structure, so that the thin film transistor structure is in an operating state, that is, a control voltage on a data line of the thin film transistor may be input to a pixel electrode through a source electrode and a drain electrode. It should be noted that, in the related art, the common voltage is smaller than the gate voltage, and when the gate voltage is applied to the gate, the source and the drain corresponding to the gate can be turned on, but when the common voltage is applied to the gate, the source and the drain corresponding to the gate cannot be turned on.
In summary, in the control method of the display panel provided by the present invention, in different time periods, gate voltages are respectively input to gates in different tft structures through gate lines in different tft structures, so that a control voltage on a data line in a tft structure to which the gate voltage is input can be input to a pixel electrode through a source and a drain, and in a time period in which the gate voltage is not input to a gate in a target tft structure, a common voltage is input to a common electrode through the gate line in the target tft structure. The control voltage is input to the pixel electrode, the common voltage is input to the common electrode, liquid crystals can deflect under the action of the control voltage and the common voltage, and the display panel displays images.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (4)
1. A thin film transistor structure, comprising: a substrate base plate, a first substrate base plate,
a grid electrode, a grid line connected with the grid electrode and a data line are formed on the substrate base plate, and the grid line is used for being connected with a common electrode in the color film base plate;
a gate insulating layer is formed on the substrate base plate on which the gate electrode is formed;
an amorphous silicon layer is formed on the substrate with the gate insulating layer;
an ohmic contact layer is formed on the substrate with the amorphous silicon layer;
forming a source drain metal pattern on the substrate with the ohmic contact layer, wherein the source drain metal pattern comprises: n source electrodes and n drain electrodes, the data line being connected to the n source electrodes, n being equal to 2;
a passivation layer is formed on the substrate with the source and drain metal patterns, and at least one through hole is formed on the passivation layer above each drain in the n drains;
a pixel electrode is formed on the substrate base plate on which the passivation layer is formed, wherein the orthographic projection of the grid line on the pixel electrode is positioned on the pixel electrode, the pixel electrode comprises n pixel sub-electrodes, the n pixel sub-electrodes correspond to the n drain electrodes one by one, and each pixel sub-electrode is connected with the corresponding drain electrode through a through hole formed in the passivation layer above the corresponding drain electrode;
the n pixel sub-electrodes are arranged in an axisymmetric mode, and the symmetry axis is the orthographic projection of the grid line on the pixel electrode; each of the n pixel sub-electrodes is formed with m slits, where m is an integer greater than or equal to 2, and the m slits have at least 2 kinds of slit directions;
any two adjacent pixel sub-electrodes of the n pixel sub-electrodes are connected with each other, or the n pixel sub-electrodes are insulated from each other.
2. The thin film transistor structure of claim 1,
a via is formed on the passivation layer over each of the n drains.
3. A display panel, comprising: an array substrate and a color film substrate which are formed in a box-to-box mode, and liquid crystal positioned between the array substrate and the color film substrate,
the array substrate includes: the liquid crystal display panel comprises a plurality of thin film transistor structures arranged in an array, wherein the thin film transistor structures are the thin film transistor structures in claim 1 or 2, the color film substrate comprises a common electrode, and in the plurality of thin film transistor structures, a grid line in at least one thin film transistor structure is connected with the common electrode.
4. A method for controlling a display panel according to claim 3, the method comprising:
inputting grid voltage to the grids in different thin film transistor structures through the grid lines in different thin film transistor structures at different time periods;
and inputting a common voltage to the common electrode through a gate line in a target thin film transistor structure during a period when a gate voltage is not input to a gate electrode in the target thin film transistor structure, wherein the target thin film transistor is any one of the at least one thin film transistor.
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| CN107026177B (en) * | 2017-03-31 | 2020-02-28 | 京东方科技集团股份有限公司 | COA substrate, preparation method thereof and display device |
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| TWI402596B (en) * | 2009-10-01 | 2013-07-21 | Chunghwa Picture Tubes Ltd | Pixel structure having capacitor compensation |
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