CN106024806A - Thin-film transistor structure, display panel and control method of display panel - Google Patents
Thin-film transistor structure, display panel and control method of display panel Download PDFInfo
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- CN106024806A CN106024806A CN201610390169.1A CN201610390169A CN106024806A CN 106024806 A CN106024806 A CN 106024806A CN 201610390169 A CN201610390169 A CN 201610390169A CN 106024806 A CN106024806 A CN 106024806A
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- 239000010409 thin film Substances 0.000 title claims abstract description 106
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 238000002161 passivation Methods 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000012528 membrane Substances 0.000 claims description 17
- 239000004973 liquid crystal related substance Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 7
- 208000034699 Vitreous floaters Diseases 0.000 claims 5
- 230000000694 effects Effects 0.000 abstract description 13
- 238000010276 construction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 230000005611 electricity Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The invention relates to a thin-film transistor structure, a display panel and a control method of display panel, and belongs to the technical field of display. The thin-film transistor structure comprises a substrate, wherein a grid is formed on the substrate; a source-drain metal pattern is formed on the substrate formed with the grid and comprises a source and a drain; a passivation layer is formed on the substrate formed with the source-drain metal pattern; at least two via holes are formed in the passivation layer at the upper part of the drain; a pixel electrode is formed on the substrate formed with the passivation layer; and the pixel electrode is connected with the drain through the at least two via holes. The problem of a relatively poor display effect of the display panel is solved; the display effect of the display panel is improved; and the thin-film transistor structure is applied to the display panel.
Description
Technical field
The present invention relates to Display Technique field, particularly to a kind of thin-film transistor structure, display floater and
Control method.
Background technology
Display floater includes array base palte and the color membrane substrates shaping box, and is positioned at array base palte and color film
Liquid crystal between substrate.Color membrane substrates includes that public electrode, array base palte include the thin film of multiple array arrangement
Transistor is (English: Thin Film Transistor；It is called for short: TFT) structure.
Each TFT structure can include grid, source electrode, drain electrode and pixel electrode, wherein, grid and grid line
Being connected, source electrode is connected with data wire, drain electrode is formed on passivation layer, and passivation layer and is formed with via
(English: via), drain electrode can be connected with pixel electrode by the via on this passivation layer.On grid line
Apply enough grid voltages, it is possible to by the control voltage on data wire from source electrode and drain electrode writing pixel electrode；
It should be noted that array base palte also includes public electrode wire, public with color membrane substrates of public electrode wire
Electrode is connected, and applies common electric voltage, it is possible to common electric voltage is write public electrode on public electrode wire.
Liquid crystal between pixel electrode and public electrode, it is possible to control voltage on the pixel electrode and public
Deflect under the effect of the common electric voltage on electrode, change the transmittance of liquid crystal, and then control display floater
The region display preset color that this pixel electrode upper is corresponding so that display floater display image.
Due in correlation technique, the pixel electrode in each TFT structure only by a slight via with
Drain electrode is connected, and pixel electrode and drain electrode are easier to loose contact so that the control voltage on data wire cannot
By source electrode and drain electrode writing pixel electrode, and then the region that on display floater, pixel electrode is corresponding cannot show
Preset color, therefore, the display effect of display floater is poor.
Summary of the invention
The problem poor in order to solve the display effect of display floater, embodiments provides a kind of thin film
Transistor arrangement, display floater and control method thereof.Described technical scheme is as follows:
First aspect, it is provided that can a kind of thin-film transistor structure, described thin-film transistor structure includes: substrate
Substrate,
It is formed with grid on described underlay substrate；
It is formed on the underlay substrate of described grid and is formed with source-drain electrode metal pattern, described source-drain electrode metal figure
Case includes: source electrode and drain electrode；
It is formed on the underlay substrate of described source-drain electrode metal pattern and is formed with passivation layer, be positioned in described drain electrode
It is formed with at least two via on the described passivation layer of side；
It is formed on the underlay substrate of described passivation layer and is formed with pixel electrode, and described pixel electrode passes through institute
State at least two via to be connected with described drain electrode.
Optionally, described source-drain electrode metal pattern includes: n source electrode and n drain electrode, described n for more than or
Integer equal to 2, the described passivation layer above each drain electrode in described n drain electrode is formed with at least one
Individual via.
Optionally, the described passivation layer above each drain electrode in described n drain electrode is formed with a via.
Optionally, described pixel electrode includes appointing in n pixel sub-electrode, and described n pixel sub-electrode
Two adjacent pixel sub-electrodes of anticipating are connected with each other, and described n pixel sub-electrode is by n via and described n
Individual drain electrode connects one by one.
Optionally, described pixel electrode includes n pixel sub-electrode, and described n pixel sub-electrode is mutual
Insulation, described n pixel sub-electrode is connected with described n drain electrode one by one by n via.
Optionally, described underlay substrate is also formed with the grid line being connected with described grid, and with described n
The data wire that individual source electrode is connected,
Wherein, the orthographic projection on described pixel electrode of the described grid line is positioned on described pixel electrode.
Optionally, each pixel sub-electrode in described n pixel sub-electrode has been respectively formed on m slit,
Described m is the integer more than or equal to 2.
Optionally, described n is equal to 2,
Described n pixel sub-electrode axial symmetry is arranged, and axis of symmetry is that described grid line is on described pixel electrode
Orthographic projection；
Described m slit has at least 2 kinds of slit direction.
Optionally, it is formed on the underlay substrate of described grid and is formed with gate insulation layer；
It is formed on the underlay substrate of described gate insulation layer and is formed with amorphous silicon layer；
It is formed on the underlay substrate of described amorphous silicon layer and is formed with ohmic contact layer；
It is formed on the underlay substrate of described ohmic contact layer and is formed with described source-drain electrode metal pattern.
Second aspect, it is provided that a kind of display floater, described display floater includes: the array base shaping box
Plate and color membrane substrates, and the liquid crystal between described array base palte and color membrane substrates,
Described array base palte includes: multiple thin-film transistor structures of array arrangement, and described thin film transistor (TFT) is tied
Structure is the thin-film transistor structure described in first aspect, and described color membrane substrates includes public electrode, described many
In individual thin-film transistor structure, the grid line at least one thin-film transistor structure is connected with described public electrode
Connect.
The third aspect, it is provided that the control method of a kind of display floater, described display floater is second aspect institute
The display floater stated, described method includes:
In the different time periods, respectively by the grid line in different thin-film transistor structures to different thin film
Grid input grid voltage in transistor arrangement；
In the time period of the not grid in aimed thin film transistor arrangement input grid voltage, by described mesh
Grid line in mark thin-film transistor structure inputs common electric voltage, described aimed thin film crystal to described public electrode
Pipe is the arbitrary thin film transistor (TFT) at least one thin film transistor (TFT) described.
In sum, the invention provides a kind of thin-film transistor structure, display floater and control method thereof,
In this thin-film transistor structure, underlay substrate is formed grid, source-drain electrode metal pattern, passivation layer and
Pixel electrode, passivation layer is formed at least two via, and pixel electrode can by passivation layer extremely
Few two vias are connected with the drain electrode on underlay substrate.When a certain via in this at least two via lost efficacy
Time, pixel electrode can also by other vias in this at least two via with the drain electrode on underlay substrate even
Connect, by the control voltage writing pixel electrode on data wire so that the display at this thin-film transistor structure place
On panel, the region that pixel electrode is corresponding can show preset color, so, improve the aobvious of display floater
Show effect.
It should be appreciated that it is only exemplary that above general description and details hereinafter describe, can not
Limit the present invention.
Accompanying drawing explanation
In order to be illustrated more clearly that embodiments of the invention, required use in embodiment being described below
Accompanying drawing is briefly described, it should be apparent that, the accompanying drawing in describing below is only some enforcements of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to root
Other accompanying drawing is obtained according to these accompanying drawings.
The top view of a kind of thin film transistor (TFT) that Fig. 1-1 provides for the embodiment of the present invention；
The sectional view of a kind of thin film transistor (TFT) that Fig. 1-2 provides for the embodiment of the present invention；
The top view of the another kind of thin film transistor (TFT) that Fig. 2-1 provides for the embodiment of the present invention；
The sectional view of the another kind of thin film transistor (TFT) that Fig. 2-2 provides for the embodiment of the present invention；
The structural representation of a kind of pixel electrode that Fig. 3 provides for the embodiment of the present invention；
The partial structurtes schematic diagram of a kind of thin film transistor (TFT) that Fig. 4-1 provides for the embodiment of the present invention；
The partial structurtes schematic diagram of the another kind of thin film transistor (TFT) that Fig. 4-2 provides for the embodiment of the present invention；
The partial structurtes schematic diagram of another thin film transistor (TFT) that Fig. 4-3 provides for the embodiment of the present invention；
The partial structurtes schematic diagram of another thin film transistor (TFT) that Fig. 4-4 provides for the embodiment of the present invention；
The partial structurtes schematic diagram of a kind of thin film transistor (TFT) that Fig. 4-5 provides for another embodiment of the present invention；
The structural representation of a kind of display floater that Fig. 5 provides for the embodiment of the present invention.
Accompanying drawing herein is merged in description and constitutes the part of this specification, it is shown that meet the present invention
Embodiment, and for explaining the principle of the present invention together with description.
Detailed description of the invention
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this
Bright it is described in further detail, it is clear that described embodiment is only some embodiments of the present invention,
Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out all other embodiments obtained under creative work premise, broadly fall into the scope of protection of the invention.
The top view of a kind of thin-film transistor structure that Fig. 1-1 provides for the embodiment of the present invention, Fig. 1-2 is this
The sectional view of a kind of thin film transistor (TFT) that bright embodiment provides, example, Fig. 1-2 can be thin in Fig. 1-1
Film transistor structure is at the sectional view at BB ' place.Refer to Fig. 1-1 and Fig. 1-2, this thin-film transistor structure 0
May include that underlay substrate 01, underlay substrate 01 is formed grid 02；It is formed with the substrate of grid 02
Being formed with source-drain electrode metal pattern 03 on substrate 01, example, this source-drain electrode metal pattern 03 may include that
Source electrode 031 and drain electrode 032；
It is formed on the underlay substrate 01 of source-drain electrode metal pattern 03 and is formed with passivation layer 04, be positioned at drain electrode 031
It is formed with at least two via A on the passivation layer 04 of top；It is formed on the underlay substrate 01 of passivation layer 04
It is formed with pixel electrode 05, and pixel electrode 05 is by least two via A formed on this passivation layer 04
It is connected with drain electrode 031.
In sum, in the thin-film transistor structure that the embodiment of the present invention provides, underlay substrate is formed with grid
Pole, source-drain electrode metal pattern, passivation layer and pixel electrode, passivation layer is formed at least two via,
And pixel electrode can be connected with the drain electrode on underlay substrate by least two via on passivation layer.When
When a certain via in this at least two via lost efficacy, pixel electrode can also be by this at least two via
Other vias be connected with the drain electrode on underlay substrate, by the control voltage writing pixel electrode on data wire,
Making on the display floater at this thin-film transistor structure place, the region that pixel electrode is corresponding can show default
Color, so, improve the display effect of display floater.
Optionally, this source-drain electrode metal pattern 03 may include that n source electrode 031 and n drain electrode 032,
Wherein, n is the integer more than or equal to 2, and this n drain electrode 032 in each drain electrode 032 above blunt
Change and could be formed with at least one via A on layer 04, example, each drain electrode 031 in n drain electrode 031
A via A is all could be formed with on the passivation layer 04 of top.
It should be noted that in the embodiment of the present invention, with n equal to 2, and each leakage in n drain electrode 031
All could be formed with a via A on passivation layer 04 above pole 031 (namely to be formed altogether on passivation layer 04
Having n via A, on passivation layer 04, the number of via A is equal with the number of drain electrode 031) as a example by, actual
In application, n can also be for other integers more than 2, on the passivation layer above each drain electrode in n drain electrode
Via number can also for other more than 1 integer, this is not construed as limiting by the embodiment of the present invention.
The top view of a kind of thin-film transistor structure that Fig. 2-1 provides for the embodiment of the present invention, Fig. 2-2 is this
The profile example of a kind of thin-film transistor structure that bright embodiment provides, Fig. 2-2 can be thin in Fig. 2-1
Film transistor structure is at the sectional view at BB ' place.
Incorporated by reference to Fig. 2-1 and Fig. 2-2, pixel electrode 05 can include n pixel sub-electrode 051, and n
The pixel sub-electrode 051 that in pixel sub-electrode 051, any two is adjacent is connected with each other, n pixel sub-electrode
051 can be connected one by one by n via A with n drain electrode 032.That is, this n pixel sub-electrode
051 is connected to an electrode, and this electrode is connected with n drain electrode 032 by n via.
And due in n pixel sub-electrode 051 any two pixel sub-electrode 051 be connected with each other, as a certain via A
During inefficacy, the pixel sub-electrode 051 being connected with the via A of this inefficacy can pass through other pixel sub-electrodes
051, the drain electrode 032 being connected with other pixel sub-electrodes 051 obtains voltage.
It should be noted that the thin-film transistor structure of array arrangement can form the array base in display floater
Plate, display floater can also include the color membrane substrates being oppositely arranged with array base palte, and be positioned at array base palte
And the liquid crystal between color membrane substrates, color membrane substrates could be formed with public electrode, and liquid crystal can be in common electrical
Deflect under the effect of the voltage on the voltage extremely gone up and pixel electrode.
In correlation technique, thin-film transistor structure can also include the public electrode wire being formed on underlay substrate
(also known as Common line), and public electrode wire can be connected with the public electrode on color membrane substrates,
Need during input voltage, public electrode alignment public electrode input voltage to be passed through on public electrode.And
Public electrode wire orthographic projection on the pixel electrode may be located on pixel electrode, public electrode wire and pixel electricity
Pole can form storage electric capacity.But, owing in correlation technique, public electrode wire is narrower, so public electrode
Line is easier to rupture, thus cannot on public electrode input voltage, be positioned at array base palte and color film base
Liquid crystal between plate cannot effectively deflect.
In the embodiment of the present invention, underlay substrate 01 can also be formed with the grid line 1 being connected with grid 02,
And the data wire 2 being connected with n source electrode 031.Example, 2 pixel in the embodiment of the present invention
Electrode 051 can be arranged with axial symmetry, and axis of symmetry can be the grid line 1 orthographic projection on pixel electrode 05.
That is, the grid line 1 not formed on underlay substrate 01 on public electrode wire, and underlay substrate 01 is permissible
It is connected with the public electrode on color membrane substrates, for replacing the public electrode alignment common electrical in correlation technique
Pole input voltage, and the orthographic projection that grid line 1 is on pixel electrode 05 may be located on pixel electrode 05, makes
Obtaining grid line 1 can also replace the public electrode wire in correlation technique to form storage electric capacity with pixel electrode 05.And
Due to grid line 1 ratio public electrode live width in correlation technique, so grid line 1 less easily ruptures, because of
This, it is possible to effective input voltage on public electrode, it is ensured that the normal deflection of liquid crystal.
Further, each pixel sub-electrode 051 in this n pixel sub-electrode 051 all can be formed
Having m slit X, m slit X to have at least 2 kinds of slit direction, m is the integer more than or equal to 2.
Concrete, owing to all could be formed with m slit X, and this m slit on each pixel sub-electrode 051
X can promote the liquid crystal between underlay substrate and color membrane substrates to have at least two deflection angle, aobvious
Show the different visual angles of panel, in conjunction with the averaging effect of liquid crystal aligning, can alleviate when display floater shows
Luminance difference, alleviates aberration during display floater display picture, thus improves the product of display floater display picture
Matter.
Gate insulation layer 06 can also be formed with it should be noted that be formed on the underlay substrate 01 of grid 02；
It is formed on the underlay substrate 01 of gate insulation layer 06 and could be formed with amorphous silicon layer 07；It is formed with amorphous silicon layer
Ohmic contact layer 08 is could be formed with on the underlay substrate 01 of 07；It is formed with the substrate base of ohmic contact layer 08
This source-drain electrode metal pattern 03 is could be formed with on plate 01.
Optionally, the top view of a kind of pixel electrode 05 that Fig. 3 provides for the embodiment of the present invention, such as Fig. 3 institute
Showing, pixel electrode 05 can also include n pixel sub-electrode 051, and n pixel sub-electrode 051 is mutual
Insulation, n pixel sub-electrode is connected with n drain electrode, with this pixel electrode in Fig. 3 one by one by n via
As a example by the 05 pixel sub-electrode 051 including 2 mutually insulateds, in actual application, this pixel electrode 05 also may be used
The number of the pixel sub-electrode 051 to include can also be more than 2.Owing to this n pixel sub-electrode 051 is mutual
Insulation, when the via A of a certain pixel sub-electrode 051 correspondence lost efficacy, this pixel sub-electrode on display floater
The region of 051 correspondence cannot show preset color, but other pixel sub-electrode 051 correspondences on display floater
Region can show the area ratio correlation technique of each pixel sub-electrode 051 in preset color, and the present invention
In the area of pixel electrode little, therefore can reduce the region that cannot show preset color on display floater
Area, thus improve the display effect of display floater.
Example, as shown in Fig. 4-1, when forming this thin-film transistor structure, can be first at underlay substrate
Grid 02 is formed on 01；Then, as shown in the Fig. 4-2, the underlay substrate 01 of grid 02 can be formed with
On sequentially form gate insulation layer 06, amorphous silicon layer 07 and ohmic contact layer 08.As shown in Fig. 4-3, Ke Yi
It is formed with on the underlay substrate 01 of ohmic contact layer 08 formation source-drain electrode metal pattern 03, this source-drain electrode metal
Pattern 03 can include n source electrode 031 and n drain electrode 032；As shown in Fig. 4-4, can be formed
Form passivation layer 04 on the underlay substrate 01 of source-drain electrode metal pattern 03, wherein, be positioned at each drain electrode 031
A via A is could be formed with on the passivation layer 04 of top；As illustrated in figures 4-5, passivation can be formed with
Forming pixel electrode 05 on the underlay substrate 01 of layer 04, this pixel electrode 05 can be by passivation layer 04
At least two via A formed is connected with at least two drain electrode 031, on each pixel sub-electrode 051 all
Could be formed with at least two slit X.
During it should be noted that form grid on underlay substrate, can be formed on underlay substrate simultaneously with
The grid line that grid is connected, when underlay substrate forms source-drain electrode metal pattern, can be simultaneously at substrate base
Form data wire on plate, and this data wire can be connected with n source electrode in this source-drain electrode metal pattern.
In sum, in the thin-film transistor structure that the embodiment of the present invention provides, underlay substrate is formed with grid
Pole, source-drain electrode metal pattern, passivation layer and pixel electrode, passivation layer is formed at least two via,
And pixel electrode can be connected with the drain electrode on underlay substrate by least two via on passivation layer.When
When a certain via in this at least two via lost efficacy, pixel electrode can also be by this at least two via
Other vias be connected with the drain electrode on underlay substrate, by the control voltage writing pixel electrode on data wire,
Making on the display floater at this thin-film transistor structure place, the region that pixel electrode is corresponding can show default
Color, so, improve the display effect of display floater.
As it is shown in figure 5, embodiments provide a kind of display floater 5, this display floater 5 may include that
The array base palte 51 that box is shaped and color membrane substrates 52, and it is positioned at this array base palte 51 and color membrane substrates 52
Between liquid crystal 53.
This array base palte 51 can include multiple thin-film transistor structures 0 of array arrangement, this thin film transistor (TFT)
Structure 0 can be for the thin-film transistor structure 0 shown in Fig. 1-1, Fig. 1-2, Fig. 2-1 or Fig. 2-2.Color film base
Plate 52 can include underlay substrate 521 and public electrode 522, the multiple thin film transistor (TFT)s in array base palte 51
In structure 0, the grid line at least one thin-film transistor structure 0 is connected with public electrode 522.
Further, the display device at this display floater 5 place can be: Electronic Paper, mobile phone, flat board electricity
Any product with display function or the portions such as brain, television set, notebook computer, DPF, navigator
Part.
In sum, in the thin-film transistor structure in the display floater that the embodiment of the present invention provides, substrate base
Be formed with grid, source-drain electrode metal pattern, passivation layer and pixel electrode on plate, passivation layer is formed to
Few two vias, and pixel electrode can be by least two via on passivation layer and the leakage on underlay substrate
Pole is connected.When a certain via in this at least two via lost efficacy, pixel electrode can also by this extremely
Other vias in few two vias are connected with the drain electrode on underlay substrate, are write by the control voltage on data wire
Entering pixel electrode so that on the display floater at this array base palte place, the region that pixel electrode is corresponding can show
Show preset color, so, improve the display effect of display floater.
Embodiments providing the control method of a kind of display floater, this display floater can be for Fig. 5 institute
The display floater 5 shown, the control method of this display floater may include that
In the different time periods, respectively by the grid line in different thin-film transistor structures to different thin film
Grid input grid voltage in transistor arrangement；Input at the not grid in aimed thin film transistor arrangement
The time period of grid voltage, input common electrical by the grid line in aimed thin film transistor arrangement to public electrode
Pressure, aimed thin film transistor is the arbitrary thin film transistor (TFT) at least one thin film transistor (TFT).
Example, the plurality of thin film transistor (TFT) may include that thin-film transistor structure 1, thin-film transistor structure
2, thin-film transistor structure 3, thin-film transistor structure 4 and thin-film transistor structure 5.Wherein, thin film is brilliant
Body tubular construction 2 is connected with public electrode with the grid line in thin-film transistor structure 5.
When controlling this display floater, grid can be inputted by the grid in the plurality of thin-film transistor structure successively
Pole tension, concrete, in thin-film transistor structure 1 grid input grid voltage time (the most not to
Grid input grid voltage in the transistor arrangement 2 being connected with public electrode or transistor arrangement 5),
The grid line in target crystal tubular construction (such as transistor arrangement 2 or transistor arrangement 5) can also be passed through to public
Electrode input common electric voltage；When inputting grid voltage to thin-film transistor structure 2 (the most not to public
Grid input grid voltage in the transistor arrangement 5 that electrode is connected), it is also possible to pass through target transistors
Grid line in structure (such as transistor arrangement 5) inputs common electric voltage to public electrode；Tying to thin film transistor (TFT)
(the most not to the transistor arrangement 2 being connected with public electrode or transistor junction when structure 3 inputs grid voltage
Grid input grid voltage in structure 5), it is also possible to by target crystal tubular construction (such as transistor arrangement 2
Or transistor arrangement 5) in grid line input common electric voltage to public electrode；Defeated to thin-film transistor structure 4
When entering grid voltage (the most not in the transistor arrangement 2 being connected with public electrode or transistor arrangement 5
Grid input grid voltage), it is also possible to by target crystal tubular construction (such as transistor arrangement 2 or crystal
Tubular construction 5) in grid line input common electric voltage to public electrode；Grid is inputted to thin-film transistor structure 5
During voltage (the most not input of the grid in the transistor arrangement 2 being connected with public electrode grid voltage),
Common electrical can also be inputted to public electrode by the grid line in target crystal tubular construction (such as transistor arrangement 2)
Pressure.
Example, array base palte row cutting can be used (English: Gate driver On Array；It is called for short: GOA)
Circuit, in the different time periods, the input of the grid in different thin-film transistor structures grid voltage respectively.
Concrete, can be when the clock signal of this GOA circuit be high level, this GOA circuit can pass through certain
The grid line in one thin-film transistor structure grid input grid voltage in this thin-film transistor structure so that
This thin-film transistor structure is in running order, namely the control voltage on the data wire in this thin film transistor (TFT)
Can be by source electrode and drain electrode input pixel electrode.It should be noted that the common electric voltage in correlation technique is little
In grid voltage, when grid voltage is loaded on grid, source electrode and drain electrode that this grid is corresponding can be led
Logical, but when common electric voltage is loaded on grid, source electrode and drain electrode that this grid is corresponding cannot be switched on.
In sum, in the control method of the display floater that the present invention provides, in the different time periods, respectively
By the grid input grid electricity in different thin-film transistor structures of the grid line in different thin-film transistor structures
Pressure so that the control voltage being transfused on the data wire in the thin-film transistor structure of grid voltage can pass through
Source electrode and drain electrode input are to pixel electrode, and input grid at the not grid in aimed thin film transistor arrangement
The time period of voltage, input common electric voltage by the grid line in aimed thin film transistor arrangement to public electrode.
Achieve and control voltage to pixel electrode input, and on public electrode, input common electric voltage so that liquid crystal
Can deflect under controlling the voltage effect with common electric voltage so that display floater display image.
Those skilled in the art, after considering description and putting into practice invention disclosed herein, will readily occur to this
Other bright embodiment.The application is intended to any modification, purposes or the adaptations of the present invention,
These modification, purposes or adaptations are followed the general principle of the present invention and include that the present invention is not disclosed
Common knowledge in the art or conventional techniques means.Description and embodiments is considered only as exemplary
, true scope and spirit of the invention are pointed out by claim.
It should be appreciated that the invention is not limited in accurate knot described above and illustrated in the accompanying drawings
Structure, and various modifications and changes can carried out without departing from the scope.The scope of the present invention is only by appended
Claim limits.
Claims (11)
1. a thin-film transistor structure, it is characterised in that described thin-film transistor structure includes: substrate base
Plate,
It is formed with grid on described underlay substrate；
It is formed on the underlay substrate of described grid and is formed with source-drain electrode metal pattern, described source-drain electrode metal figure
Case includes: source electrode and drain electrode；
It is formed on the underlay substrate of described source-drain electrode metal pattern and is formed with passivation layer, be positioned in described drain electrode
It is formed with at least two via on the described passivation layer of side；
It is formed on the underlay substrate of described passivation layer and is formed with pixel electrode, and described pixel electrode passes through institute
State at least two via to be connected with described drain electrode.
Thin-film transistor structure the most according to claim 1, it is characterised in that described source-drain electrode metal
Pattern includes: n source electrode and n drain electrode, and described n is the integer more than or equal to 2,
It is formed with at least one via on the described passivation layer above each drain electrode in described n drain electrode.
Thin-film transistor structure the most according to claim 2, it is characterised in that
It is formed with a via on the described passivation layer above each drain electrode in described n drain electrode.
Thin-film transistor structure the most according to claim 3, it is characterised in that
Described pixel electrode includes any two phase in n pixel sub-electrode, and described n pixel sub-electrode
Adjacent pixel sub-electrode is connected with each other, and described n pixel sub-electrode is by n via and described n drain electrode
Connect one by one.
Thin-film transistor structure the most according to claim 3, it is characterised in that
Described pixel electrode includes n pixel sub-electrode, and described n pixel sub-electrode mutually insulated, institute
State n pixel sub-electrode to be connected one by one with described n drain electrode by n via.
Thin-film transistor structure the most according to claim 4, it is characterised in that on described underlay substrate
It is also formed with the grid line being connected with described grid, and the data wire being connected with described n source electrode,
Wherein, the orthographic projection on described pixel electrode of the described grid line is positioned on described pixel electrode.
Thin-film transistor structure the most according to claim 6, it is characterised in that
Each pixel sub-electrode in described n pixel sub-electrode has been respectively formed on m slit, and described m is
Integer more than or equal to 2.
Thin-film transistor structure the most according to claim 7, it is characterised in that described n is equal to 2,
Described n pixel sub-electrode axial symmetry is arranged, and axis of symmetry is that described grid line is on described pixel electrode
Orthographic projection；
Described m slit has at least 2 kinds of slit direction.
Thin-film transistor structure the most according to claim 1, it is characterised in that
It is formed on the underlay substrate of described grid and is formed with gate insulation layer；
It is formed on the underlay substrate of described gate insulation layer and is formed with amorphous silicon layer；
It is formed on the underlay substrate of described amorphous silicon layer and is formed with ohmic contact layer；
It is formed on the underlay substrate of described ohmic contact layer and is formed with described source-drain electrode metal pattern.
10. a display floater, it is characterised in that described display floater includes: the array base that box is shaped
Plate and color membrane substrates, and the liquid crystal between described array base palte and color membrane substrates,
Described array base palte includes: multiple thin-film transistor structures of array arrangement, and described thin film transistor (TFT) is tied
Structure is the arbitrary described thin-film transistor structure of claim 1 to 9, and described color membrane substrates includes public electrode,
In the plurality of thin-film transistor structure, the grid line at least one thin-film transistor structure is public with described
Electrode is connected.
The control method of 11. 1 kinds of display floaters, it is characterised in that described display floater is claim 10
Described display floater, described method includes:
In the different time periods, respectively by the grid line in different thin-film transistor structures to different thin film
Grid input grid voltage in transistor arrangement；
In the time period of the not grid in aimed thin film transistor arrangement input grid voltage, by described mesh
Grid line in mark thin-film transistor structure inputs common electric voltage, described aimed thin film crystal to described public electrode
Pipe is the arbitrary thin film transistor (TFT) at least one thin film transistor (TFT) described.
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