CN106020769B - Floating-point divider and Floating-point divider operating method - Google Patents
Floating-point divider and Floating-point divider operating method Download PDFInfo
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
It is candidate to wait for that measured value generates multiple Part III remainders in addition to generating second part remainder according to first part's remainder, divisor and the first quotient also according to the second part remainder, the divisor and multiple second quotients for a kind of Floating-point divider.First quotient table is through inquiring, and in addition to the corresponding second part remainder of supply and the second quotient of the divisor, also multiple third quotients of the corresponding Part III remainder candidate of supply and the divisor are candidate.First multiplexer selects the corresponding second quotient person as third quotient from the third quotient candidate.The third quotient is used as the part position of the combination quotient of next round operation or the part position as the combination quotient when wheel but is additionally operable to content needed for prediction next round operation.
Description
Technical field
The present invention relates to Floating-point divider (floating-point dividers).
Background technology
Floating-point divider needs to iterate carries out the quotients calculating taken turns more.However, in face of the design of large cardinal (radix)
Demand, Floating-point divider, which often takes turns calculated quotient, has considerable bit quantity, Logic Circuit Design quite lengthy and jumbled.
Invention content
The present invention proposes a kind of Floating-point divider, and by the short position amount quotient for acquisition of repeatedly tabling look-up, combination exists in a wheel operation
Together, it is in the combination quotient output of long position amount, wherein respectively wheel operation further includes the combination quotient predicted obtained by next round operation
Part position.
The Floating-point divider realized according to one embodiment of the present invention includes more than wheel partial remainder generator, the part
Number emulator, the first quotient table and the first multiplexer.Partial remainder generator should be taken turns according to first part's remainder, divisor
And first quotient, generate second part remainder.The partial remainder emulator, according to the second part remainder, the divisor and
Multiple second quotients wait for measured value, and it is candidate to generate multiple Part III remainders.The first quotient table through inquiry, supply it is corresponding this
Second quotient of two partial remainders and the divisor.Also through inquiry, supply corresponds to more than the Part III the first quotient table
Multiple third quotients of number candidate and the divisor are candidate.First multiplexer selects corresponding be somebody's turn to do from the third quotient candidate
Second quotient person exports, as third quotient.The third quotient is used as the part position of the combination quotient of next round operation or uses
Make when the part of the combination quotient of wheel position but is additionally operable to content needed for prediction next round operation.
A kind of Floating-point divider operating method realized according to one embodiment of the present invention, to operate including first
The Floating-point divider of quotient table, including：According to first part's remainder, divisor and the first quotient, second part remainder is generated；
Measured value is waited for according to the second part remainder, the divisor and multiple second quotients, and it is candidate to generate multiple Part III remainders；Inquiry
The first quotient table supplies the corresponding second part remainder and the second quotient of the divisor；The first quotient table is inquired,
Multiple third quotients of the corresponding Part III remainder candidate of supply and the divisor are candidate；And the first multiplexer is provided,
Corresponding second quotient person output is selected from the third quotient candidate, as third quotient.The third quotient is used as next
It takes turns the part position of the combination quotient of operation or the part position as the combination quotient when wheel but is additionally operable to prediction next round operation
Required content.
The invention enables a wheel operations of Floating-point divider not only to carry out a quotient table lookup.The quotient repeatedly obtained
Table lookup result is combinable, in a wheel operation of Floating-point divider makees that quotient is combined to export.The larger floating-point division of radix
Device the every length position quotient that should export of wheel operation thus can be by the multiple short position data combinations for acquisition of tabling look-up.In addition, of the invention
Each wheel operation of Floating-point divider further includes the part position for the combination quotient for predicting that next round operation is exported, and efficiency is much better than
Traditional Floating-point divider framework.
Special embodiment below, and coordinate appended diagram, content that the present invention will be described in detail.
Description of the drawings
Figure 1A illustrates each operand of division arithmetic；
Figure 1B and Fig. 1 C show quotient table with two-dimensional coordinate；
Fig. 2 illustrates Floating-point divider 200 according to one embodiment of the present invention；
Fig. 3 is flow chart, the operating method of 2 Floating-point divider 200 of schematic thinking, to provide division arithmetic (w/d)；
Fig. 4 illustrates Floating-point divider 400 according to another embodiment of the present invention；And
Fig. 5 A, Fig. 5 B are flow chart, the operating method of 4 Floating-point divider 400 of schematic thinking, to provide division arithmetic (w/d).
Specific implementation mode
The various embodiments described below for enumerating the present invention.The basic conception described below for introducing the present invention, and not anticipate
Figure limitation the content of present invention.Practical invention scope should define it according to claim.
Figure 1A illustrates each operand of division arithmetic, including dividend w and divisor d, and quotient is sequentially obtained in operation
Value q0, q1, q2, q3.It is worth noting that, to obtain 4 quotient q0~q3 merely illustrative for operation here, the present invention is not limited to
This, when dividend d is eliminated or is restrained determines by divisor w for the quantity of quotient, therefore division arithmetic is likely to obtain other numbers
The quotient of amount, however it is not limited to 4.The present embodiment uses radix (radix) 4, i.e., each clock cycle to generate 2 quotients.Quotient
It is needed during value q0, q1, q2, q3 operation by the decimal point right shift 2 (i.e. 4 × wi) of intermediate remainder wi, i is number.This hair
It is bright that numerical value wi and 4 × wi are referred to as partial remainder (partial remainder), label S (i+1).Quotient q (i+1) can
It is obtained with lookup table mode according to partial remainder S (i+1) and divisor d.
Figure 1B shows quotient table with two-dimensional coordinate.A kind of lookup table mode is to utilize 4 × wi of partial remainder (i.e. S (i+1))
It tables look-up, by 4 × wi of partial remainder (i.e. S (i+1)) compared with the various multiples of divisor d, you can obtain corresponding quotient q (i+1)
Lines.On quotient q (i+1) lines, it is rendered as 4 × wi of partial remainder of the certain multiple of divisor d, quotient in a certain range
Value q (i+1) is identical, in Figure 1B, is rendered as4 × wi of partial remainder in section corresponds to quotient q (i+1)=0.Under
How face in conjunction with Figure 1A inquires the corresponding quotient of quotient table acquisition, such as 4 × w0=1.110101B of partial remainder if being illustrated
≈ 1.75D (wherein B represents binary number, and D represents decimal number), divisor d=1.101B ≈ 1.625D, then partial remainder 4 ×
W0 is rendered as about 1.08 times of divisor d, therefore corresponding quotient q1=1 known to the quotient table in query graph 1B.Partial remainder 4
Multiple critical values can be also designed on × wi (i.e. S (i+1)) axis so that the partial remainder 4 of corresponding a plurality of quotient q (i+1) lines ×
Wi is able to correctly select correct corresponding person from quotient q (i+1) lines.Fig. 1 C show quotient-meter, with another two-dimensional coordinate
Lattice, wherein being to use wi for partial remainder, i.e. value on S (i+1) axis is the value of wi, is tabled look-up using partial remainder wi, by part
Remainder wi is compared with the various multiples of divisor d, you can obtains corresponding quotient q (i+1) lines.The quotient-meter, of Figure 1B or Fig. 1 C
Lattice are to obtain quotient q (i+1) for tabling look-up according to partial remainder S (i+1) and divisor d.The above quotient table concept can be used
In the Floating-point divider application of various radixes.The present embodiment uses radix (radix) 4, i.e., each clock cycle to generate 2
Quotient, if can only inquire a quotient table per the clock cycle, the value range of quotient is { -2, -1,0,1,2 }.It is adopting
In embodiment with other radixes, for example, by using radix 16, then each clock cycle generates 4 quotients, if the week per clock
Phase can only inquire a quotient table, then the value range of quotient be -15, -14, -13, -12 ... -1,0,1 ... 12,13,
14,15 }, i.e., [- 15,15], but the present invention is not limited thereto, when taking different quotient coding modes, the value range of quotient
It will be different.It inquires quotient table in floating-point division operation relatively to take, and the quotient digit tabled look-up every time is more,
Then hardware spending is bigger.Therefore the present invention proposes a kind of one and takes turns the Floating-point divider that operation carries out multiple quotient table lookup,
Even if using the smaller quotient table of hardware spending, for example, even if using the table for the quotient for being only capable of obtaining 2 of tabling look-up every time
Lattice (such as quotient table of query graph 1B), a wheel operation inquiry can also obtain 4 quotients, that is, realize base 16, example twice
Such as SRT-16, without use hardware spending larger quotient value range for the quotient table of [- 15,15].
The invention enables a wheel operations of Floating-point divider not only to carry out a quotient table lookup.The quotient repeatedly obtained
Table lookup result is combinable, in a wheel operation of Floating-point divider makees that quotient is combined to export.The larger floating-point division of radix
Device the every length position quotient that should export of wheel operation thus can be combined by the short position data for acquisition of tabling look-up.In addition, floating-point of the present invention
Each wheel operation of divider further includes the part position for the combination quotient for predicting that next round operation is exported, and efficiency is much better than tradition
Floating-point divider framework.
Fig. 2 illustrates Floating-point divider 200 according to one embodiment of the present invention, including when wheel partial remainder generator 202,
Partial remainder emulator 204, the first quotient table 206 and the first multiplexer 207, the second quotient table and the second multiplexer
(being indicated in conjunction with square 208), quotient converter 210 and subsequent rounds partial remainder generator 212.
Partial remainder generator 202 should be taken turns and generate second according to first part remainder Sa, divisor d and the first quotient qa
Partial remainder Sb.The partial remainder emulator 204 is waited for according to second part remainder Sb, divisor d and multiple second quotients
Measured value qp1 ... qpN generates multiple Part III remainder candidate San1 ... SanN.Second quotient waits for that measured value qp1 ... qpN can be
The be possible to numerical value of second quotient qb, for example, qp1 ... qpN values be Figure 1B or Fig. 1 C quotient table in it is all can
The quotient of energy.The first quotient table 206 supplies the second quotient of corresponding second part remainder Sb and divisor d through inquiry
Value qb.The first quotient table 206 is additionally operable to the corresponding Part III remainder candidate San1 ... SanN of inquiry supply and should
Multiple third quotient candidate qan1 ... qanN of divisor d transfer to first multiplexer 207 according to the second quotient qb from described
The output that corresponding second quotient qb is selected in three quotient candidate qan1 ... qanN, as third quotient qan, i.e. selection should
Part III remainder candidate (San1 ... corresponding to second quotient qb (waiting for one of measured value qp1 ... qpN as multiple second quotients)
One of SanN) corresponding to third quotient candidate (one of qan1 ... qanN) be used as third quotient qan.In particular, second quotient
Value table and the second multiplexer (208) are used in the first round operation of the Floating-point divider 200, corresponding dividend w with
And divisor d supplies above-mentioned first quotient qa and first part remainder Sa should extremely take turns partial remainder generator 202.Such as figure
Shown, quotient converter 210 is in each wheel operation, by each the first quotient qa and second quotient qb for providing M information
Combination the quotient Q, above-mentioned M that conversion is combined into 2M are numerical value.As for third quotient qan, this embodiment is used as down
Part position of one wheel in conjunction with quotient Q.The third quotient qan will be supplied as down through second multiplexer switching in square 208
First quotient qa that one wheel operation uses.As for the next round required first part remainder Sa of combination quotient Q operations, then
It is to be provided by the subsequent rounds partial remainder generator 212.The subsequent rounds partial remainder generator 212 is according to the second part remainder
Sb, divisor d and second quotient qb generate Part III remainder San, switch through second multiplexer in square 208 and supply
It should be used as the required first part remainder Sa of next round operation.As previously mentioned, the second quotient table and the second multiplexer
(208) only in the first round operation of the Floating-point divider 200 first part's remainder is obtained for dividend w and divisor d inquiries
Sa and the first quotient qa are used；And in the operation of subsequent rounds, without using the second quotient table in square 208, but by
Second multiplexer in square 208 directly selects first of the third quotient qan obtained by previous round operation as epicycle operation
Quotient qa, and select the Part III remainder San obtained by previous round operation as the first part remainder Sa of epicycle operation.
In one embodiment, partial remainder generator 202, the partial remainder emulator 204 and the subsequent rounds should be taken turns
Partial remainder generator 212 is all based on r × wi-q (i+1) × d=w (i+1) operations and designs, and wherein r is intermediate remainder wi
Shift position amount.Such as in the embodiment of Figure 1A, r values are 4, w (i+1)=4 × wi-q (i+1) × d, and partial remainder S (i+1)
=4 × wi, for concrete example, d=1.101B, and quotient is inquired according to first part remainder S1=4 × w0=1.110101B
Value table obtains q1=1；Then w1=4 × w0-q1 × d=1.110101B-1 × 1.101B=0.001101B, then second part
Remainder S2=4 × w1=0.1101B.Depending on different definition ways (e.g., S (i+1)=r × wi or S (i+ of partial remainder S (i+1)
1)=wi), partial remainder generator 202, the partial remainder emulator 204 and the subsequent rounds partial remainder generator should be taken turns
212 Logic Circuit Design can be adjusted accordingly.Partial remainder generator 202, the partial remainder emulator 204 should be taken turns and be somebody's turn to do
Subsequent rounds partial remainder generator 212 can be used serial adder, adder and multiplier ... that logical operations pieces is waited to realize
Above-mentioned r × wi-q (i+1) × d=w (i+1) operation, makes according to partial remainder S (i+1) (i.e. r × wi or wi), divisor d and quotient
Value q (i+1) output par, c remainder S (i+2) (i.e. r × w (i+1) or w (i+1)).First quotient table 206 is also to regard partial remainder
It defines and establishes.
By taking radix 256 as an example, the combination quotient Q that respectively wheel operation should export of Floating-point divider 200 is 8, wherein higher by 4
Position is provided by the first quotient qa, and relatively low 4 are provided by the second quotient qb.Far beyond 8 hardware spendings of 4 quotient operations are small and simple
Easily, wherein displacement only 2 to intermediate remainder wi4Position, far below traditional Floating-point divider framework required 28Position.In addition, closing
In 200 framework of Floating-point divider of radix 256, the second quotient wait for measured value qp1 ... qpN may be set to -15, -14, -13, -
12 ... -1,0,1 ... 12,13,14,15 } such 31 numerical value, it is candidate to estimate 31 Part III remainders.Certainly, this hair
The bright quotient ranging from [- 15,15] being not limited to about radix 256, when taking different quotient coding modes, the value of quotient
Range will be different, and 2N+1 numerical value, wherein N ∈ { 8,9,10,11,12,13,14,15 } are had altogether for [- N, N].
Fig. 3 is flow chart, the operating method of 2 Floating-point divider 200 of schematic thinking, to provide division arithmetic (w/d).
Step S302 receives dividend w and divisor d, and the second quotient table in query block 208 obtains the first quotient according to this
Value qa.Step S304 operations should take turns partial remainder generator 202 and (combine quotient Q operations as the first round according to dividend w
First part remainder Sa), divisor d and the first quotient qa generate second part remainder Sb.Step S306 operates the partial remainder
Emulator 204 waits for that measured value qp1 ... qpN generates Part III remainder and waits according to second part remainder Sb, divisor d and the second quotient
The SanN that selects San1 ....Step S308 obtains second according to second part remainder Sb and divisor d, the first quotient table 206 of inquiry
Quotient qb.Step S310 is obtained according to Part III remainder candidate San1 ... SanN and divisor d, the first quotient table 206 of inquiry
Third quotient candidate qan1 ... qanN, transfer to the second quotient qb that the first multiplexer 207 is generated according to step S308 from described
The output that corresponding second quotient qb is selected in third quotient candidate qan1 ... qanN, as third quotient qan.Step
S312 operates subsequent rounds partial remainder generator 212 and generates third according to second part remainder Sb, divisor d and the second quotient qb
Partial remainder San.In step S314, above-mentioned third quotient qan and Part III remainder San through in square 208 this second
Multiplexer transfers to take turns partial remainder generator 202 respectively as the first quotient needed for 200 new round operation of Floating-point divider
Value qa and first part remainder Sa, i other words, the third quotient qan that last round of operation generates is as needed for new round operation
First quotient qa, the Part III remainder San that last round of operation generates as the first part remainder Sa needed for new round operation,
The second part remainder Sb of the new round operation, and then flow resumes step S306 are generated according to this.The recyclable fortune of flow shown in Fig. 3
Make until partial remainder digit is insufficient.Disclosed division flow will obtain the first quotient qa and the second quotient in each wheel operation
Value qb, conversion are combined into conjunction with quotient Q.All combination quotient Q that difference wheel operation obtains will be in conjunction with as division arithmetic w/d
Result.In other embodiment, step S308 can be arranged in before step S306, or be arranged among step S310,
That is step S306 and step S308 in no particular order sequence.
Fig. 4 illustrates Floating-point divider 400 according to another embodiment of the present invention, is corresponded to compared to Floating-point divider 200
It corrects and partial remainder emulator 410, the first quotient table and the first multiplexer (being indicated in conjunction with square 420), quotient is provided
Converter 430 and subsequent rounds partial remainder generator 440, it is by three quotients to make the combination quotient Q that every wheel operation is obtained
Qa, qb and qc are combined and are converted into.
Partial remainder emulator 410 is in addition to be measured according to second part remainder Sb, divisor d and multiple second quotients
Value qp1 ... qpN generates multiple Part III remainder candidate Sc1 ... ScN, also according to the Part III remainder candidate Sc1 ...
It is candidate that ScN, divisor d and multiple third quotients wait for that measured value (this example is similarly qp1 ... qpN) generates multiple Part IV remainders
San11…San1N、…、SanN1…SanNN.For the first quotient table in square 420 through inquiry, supply is this second corresponding
Divide the second quotient qb of remainder Sb and divisor d；The first quotient table in square 420 is also queried, and corresponding described the
Three parts remainder candidate Sc1 ... ScN and divisor d supply multiple third quotient candidate qc1 ... qcN (not shown) sides of transferring to
The first multiplexer in block 420 selects corresponding second quotient according to the second quotient qb from the third quotient candidate qc1 ... qcN
An output of value qb is third quotient qc, i.e., second quotient qb is first selected (to wait for measured value qp1 ... as multiple second quotients
One of qpN) corresponding to Part III remainder candidate (one of Sc1 ... ScN) corresponding to third quotient it is candidate (qc1 ... qcN it
One) it is used as third quotient qc.In addition, the first quotient table in square 420 is also queried, according to (N × N number of) the 4th
Point remainder candidate San11 ... San1N ..., SanN1 ... SanNN and divisor d, supply multiple 4th quotient candidate qan11 ...
Qan1N ..., qanN1 ... qanNN (not shown), transfer to the first multiplexer in square 420 correspond to the second quotient qb and
Third quotient qc chooses one as the 4th quotient qan outputs.For concrete example, the first multiplexer in square 420 is according to looking into
The second quotient qb obtained by table selects second quotient qb (waiting for one of measured value qp1 ... qpN as multiple second quotients) corresponding
That corresponding N number of Part IV remainder of Part III remainder candidate (one of Sc1 ... ScN) it is candidate (San11 ... San1N ...,
One group in SanN1 ... SanNN, for example, Sani1 ... SaniN)；Further according to gained of tabling look-up third quotient qc from aforementioned selected
Select third quotient qc (as multiple thirds in that the N number of Part IV remainder candidate (being Sani1 ... SaniN as preceding) selected
Quotient waits for measured value, one of the qpN that is similarly qp1 ...) corresponding to candidate (for one of Sani1 ... the SaniN) institute of Part IV remainder
That corresponding the 4th quotient candidate (for one of qani1 ... qaniN) is as the 4th quotient qan outputs.In other embodiment
In, the second quotient qb can also input the partial remainder emulator 410, and the partial remainder emulator 410 no longer redundancy is made to provide institute
State in Part III remainder candidate Sc1 ... ScN and the Part IV remainder candidate San11 ... San1N ..., SanN1 ...
Second quotient qb person is not corresponded in SanNN.
It as the quotient converter 430, is designed in each wheel operation, by each first quotient qa for providing M information, is somebody's turn to do
Combination the quotient Q, above-mentioned M that second quotient qb and third quotient qc conversions are combined into 3M are numerical value.With radix 29For
Example, Floating-point divider 400 can generate 9 combination quotient Q in each wheel operation, be by 3 the first quotient qa, the of 3
Two quotient qb and 3 third quotient qc are obtained in conjunction with conversion.
Subsequent rounds partial remainder generator 440 acts as follows.According to second part remainder Sb, divisor d and this
Two quotient qb, the subsequent rounds partial remainder generator 440 generate Part III remainder Sc (inside square 440, not shown),
And also according to Part III remainder Sc (not shown), divisor d and third quotient qc, generate Part IV remainder
San.Floating-point divider 400 generate the 4th quotient qan and Part IV remainder San be by square 208 this more than second
For work device after the first round operation of the Floating-point divider 400, the above-mentioned first quotient qa needed for next round operation is made in switching output
And first part remainder Sa.Compared to Floating-point divider 200, the third quotient qc that Floating-point divider 400 generates is used as working as
The part position of the combination quotient Q of wheel, but content needed for prediction next round operation is additionally operable to (for example, qan and San is to be obtained based on qc
).Compared to Floating-point divider 200, Floating-point divider 400 has carried out 3 quotient table lookups parallel in same wheel operation
Action, which part remainder emulator 410 carries out operation and generates N number of Part III remainder candidate Sc1 ... ScN, and then root
Nested operation, which is carried out, according to generated N number of Part III remainder candidate Sc1 ... ScN generates N × N number of Part IV remainder candidate
San11 ... San1N ..., SanN1 ... SanNN, by determining qb and qc as the multiplexer in the first multiplexer in square 420
The selection signal of logic, from N × N number of Part IV remainder candidate San11 ... San1N ..., the corresponding N × N of SanN1 ... SanNN
One selected in a q values exports as qan.The embodiment of Fig. 4 will be than the relatively time-consuming quotient three times for exporting qb, qc and qan
Table lookup operation carries out side by side, so that it is completed in same wheel operation, the first round that has to wait for compared with the prior art looks into
Table obtains the second quotient qb and then calculates Part III remainder Sc by the second quotient qb tables look-up by third quotient to carry out the second wheel
Value qc by third quotient qc calculates Part IV remainder San again later and is tabled look-up to obtain qan with carrying out third round, takes and substantially reduce.
Fig. 5 A, Fig. 5 B are flow chart, the operating method of 4 Floating-point divider 400 of schematic thinking, to provide division arithmetic (w/d).
Step S502 receives dividend w and divisor d, and the second quotient table in query block 208 obtains the first quotient according to this
Value qa.Step S504 operations should take turns partial remainder generator 202 and (combine quotient Q operations as the first round according to dividend w
First part remainder Sa), divisor d and the first quotient qa generate second part remainder Sb.Step S506 operates the partial remainder
Emulator 410 waits for that measured value qp1 ... qpN generates Part III remainder and waits according to second part remainder Sb, divisor d and the second quotient
The ScN that selects Sc1 ....Step S508 operate again the partial remainder emulator 410 according to Part III remainder candidate Sc1 ... ScN, remove
Number d and third quotient wait for measured value (this example is all qp1 ... qpN) generate Part IV remainder candidate San11 ... San1N ...,
SanN1…SanNN.Step S510 is according to second part remainder Sb and divisor d, the first quotient table in query block 420
Obtain the second quotient qb.Step S512 is according to Part III remainder candidate Sc1 ... ScN and divisor d, in query block 420
First quotient table obtains third quotient candidate qc1 ... qcN, and the first multiplexer in square 420 is transferred to be produced according to step S510
The second raw quotient qb selects an output of corresponding second quotient qb from the third quotient candidate qc1 ... qcN, as
Third quotient qc.Step S514 according to Part IV remainder candidate San11 ... San1N ..., SanN1 ... SanNN (N × N number of) with
And divisor d, the first quotient table in query block 420 obtain the 4th quotient candidate qan11 ... qan1N ..., qanN1 ...
QanNN (N × N number of) transfers to the first multiplexer in square 420 that corresponding second and third quotient qb is selected to be exported with qc person,
As the 4th quotient qan.Step S516 operation subsequent rounds partial remainder generator 440 according to second part remainder Sb, divisor d with
And second quotient qb generate Part III remainder Sc (inside square 440), and also according to Part III remainder Sc, the divisor
D and third quotient qc generates Part IV remainder San.In step S518, above-mentioned 4th quotient qan and Part IV
Remainder San transfers to take turns partial remainder generator 202 respectively as Floating-point divider through second multiplexer in square 208
The first quotient qa needed for 400 new round operations and first part remainder Sa, generates second of the new round operation according to this
Divide remainder Sb, and then flow resumes step S506.The recyclable running of flow shown in Fig. 5 A, Fig. 5 B until partial remainder digit not
Foot.Disclosed division flow will obtain the first quotient qa, the second quotient qb and third quotient qc in each wheel operation, operation
The conversion of quotient converter 430 is combined into conjunction with quotient Q.Difference wheel operations obtain all combination quotient Q will in conjunction with as except
The result of method operation w/d.In other embodiment, step S510 and fine-tuning to the front or rear steps of S512.
In other embodiments, the quotient quantity that partial remainder emulator can emulate, can be not only in shown in Fig. 2
One (qan) or (qc and qan) two shown in Fig. 4.According to above-mentioned same concept, partial remainder emulator can even emulate more
In two quotients.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention, any to be familiar with this
Those skilled in the art, without departing from the spirit and scope of the present invention, when can do it is a little change and retouch, therefore protection scope of the present invention
Subject to being defined depending on claims.
Claims (16)
1. a kind of Floating-point divider, which is characterized in that including：
When wheel partial remainder generator generates second part remainder according to first part's remainder, divisor and the first quotient；
Partial remainder emulator waits for measured value according to the second part remainder, the divisor and multiple second quotients, generates multiple the
Three parts remainder is candidate；And
First quotient table and the first multiplexer,
Wherein：
The first quotient table supplies the corresponding second part remainder and the second quotient of the divisor through inquiry；
For the first quotient table also through inquiry, supply corresponds to the Part III remainder candidate and multiple third quotient of the divisor
Value is candidate；And
First multiplexer selects corresponding second quotient person output from the third quotient candidate, as third quotient.
2. Floating-point divider according to claim 1, which is characterized in that first multiplexer selection with second quotient in
Above-mentioned multiple second quotients wait for the above-mentioned third corresponding to the above-mentioned Part III remainder candidate among measured value corresponding to corresponding person
Quotient candidate is as above-mentioned third quotient.
3. Floating-point divider according to claim 1, which is characterized in that further include the second quotient table, wherein：
In the first round operation of the Floating-point divider, which supplies through inquiry, corresponding dividend and the divisor
Answer above-mentioned first quotient；And
In above-mentioned first round operation, which, which is used as first part's remainder input, should take turns partial remainder generator.
4. Floating-point divider according to claim 1, which is characterized in that further include：
Quotient converter, in each wheel operation, by each first quotient and the second quotient Change-over knot for providing M position information
The quotient of 2M position is synthesized, above-mentioned M is numerical value.
5. Floating-point divider according to claim 1, which is characterized in that further include：
Subsequent rounds partial remainder generator generates Part III according to the second part remainder, the divisor and second quotient
Remainder；And
Second multiplexer, switching export the third quotient as above-mentioned first quotient, and it is above-mentioned to export the Part III remainder
First part's remainder.
6. Floating-point divider according to claim 1, it is characterised in that：
The partial remainder emulator is also according to corresponding to second quotient person, the divisor and more in the Part III remainder candidate
A third quotient waits for measured value, and it is candidate to generate multiple Part IV remainders；
For the first quotient table also through inquiry, supply corresponds to the Part IV remainder candidate and multiple 4th quotient of the divisor
Value is candidate；And
First multiplexer selects corresponding third quotient person output also from the 4th quotient candidate, as the 4th quotient.
7. Floating-point divider according to claim 6, which is characterized in that further include：
Subsequent rounds partial remainder generator generates Part III according to the second part remainder, the divisor and second quotient
Remainder, and also according to the Part III remainder, the divisor and the third quotient, generate Part IV remainder；And
Second multiplexer, switching the 4th quotient of output is as above-mentioned first quotient, and it is above-mentioned to export the Part IV remainder
First part's remainder.
8. Floating-point divider according to claim 1, which is characterized in that further include：
Quotient converter, in each wheel operation, by each first quotient that M position information is provided, second quotient and this
Three quotients convert the quotient for being combined into 3M position, and above-mentioned M is numerical value.
9. a kind of Floating-point divider operating method, to operate the Floating-point divider for including the first quotient table, which is characterized in that
Including：
According to first part's remainder, divisor and the first quotient, second part remainder is generated；
Measured value is waited for according to the second part remainder, the divisor and multiple second quotients, and it is candidate to generate multiple Part III remainders；
The first quotient table is inquired, the corresponding second part remainder and the second quotient of the divisor are supplied；
Inquire multiple third quotients time of the first quotient table, the corresponding Part III remainder candidate of supply and the divisor
Choosing；And
First multiplexer is provided, corresponding second quotient person output is selected from the third quotient candidate, as third quotient.
10. Floating-point divider operating method according to claim 9, which is characterized in that operate first multiplexer selection
With above-mentioned Part III remainder candidate institute of second quotient among above-mentioned multiple second quotients wait for measured value corresponding to corresponding person
Corresponding above-mentioned third quotient candidate is as above-mentioned third quotient.
11. Floating-point divider operating method according to claim 9, which is characterized in that further include：
Second quotient table is provided；
In each wheel operation of the Floating-point divider, the second quotient table is inquired, corresponding dividend and the divisor are supplied
State the first quotient；And
In first round operation, using the dividend as first part's remainder.
12. Floating-point divider operating method according to claim 9, which is characterized in that further include：
Quotient converter is provided, in each wheel operation, by each first quotient and second quotient turn for providing M position information
The quotient for being combined into 2M position is changed, above-mentioned M is numerical value.
13. Floating-point divider operating method according to claim 9, which is characterized in that further include：
According to the second part remainder, the divisor and second quotient, Part III remainder is generated；And
The second multiplexer is provided, switching exports the third quotient as above-mentioned first quotient, and exports the Part III remainder and be
Above-mentioned first part's remainder.
14. Floating-point divider operating method according to claim 9, which is characterized in that further include：
Measured value is waited for according to second quotient person, the divisor and multiple third quotients is corresponded in the Part III remainder candidate,
It is candidate to generate multiple Part IV remainders；
Inquire multiple 4th quotients time of the first quotient table, the corresponding Part IV remainder candidate of supply and the divisor
Choosing；And
Corresponding third quotient person output is selected from the 4th quotient candidate with first multiplexer, as the 4th quotient.
15. Floating-point divider operating method according to claim 14, which is characterized in that further include：
Part III remainder is generated according to the second part remainder, the divisor and second quotient, and also according to the third portion
Divide remainder, the divisor and the third quotient, generates Part IV remainder；And
The second multiplexer is provided, switching the 4th quotient of output exports the Part IV remainder and be as above-mentioned first quotient
Above-mentioned first part's remainder.
16. Floating-point divider operating method according to claim 9, which is characterized in that further include：
There is provided quotient converter, in each wheel operation, by each first quotient that M position information is provided, second quotient and
The third quotient converts the quotient for being combined into 3M position, and above-mentioned M is numerical value.
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| CN201610459035.0A CN106020769B (en) | 2016-06-22 | 2016-06-22 | Floating-point divider and Floating-point divider operating method |
| TW105138802A TWI606391B (en) | 2016-06-22 | 2016-11-25 | Floating-point divider and method for operating floating-point divider |
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| Publication number | Publication date |
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| CN106020769A (en) | 2016-10-12 |
| TWI606391B (en) | 2017-11-21 |
| TW201810019A (en) | 2018-03-16 |
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