CN105990430A - Semiconductor device and preparation method thereof, and electronic device - Google Patents
Semiconductor device and preparation method thereof, and electronic device Download PDFInfo
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- CN105990430A CN105990430A CN201510090263.0A CN201510090263A CN105990430A CN 105990430 A CN105990430 A CN 105990430A CN 201510090263 A CN201510090263 A CN 201510090263A CN 105990430 A CN105990430 A CN 105990430A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 30
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 116
- 238000000034 method Methods 0.000 claims description 33
- 238000002955 isolation Methods 0.000 claims description 29
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000009434 installation Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to a semiconductor device and a preparation method thereof, and an electronic device. The semiconductor device comprises: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate; a break-through stop layer located in channel regions in the fin structures; and a diffusion stop layer located in the fin structures and breaking through the top of the break-through stop layer. A carbon diffusion stop layer is introduced to prevent a channel stop layer from ion injecting and diffusing to a channel so as to avoid the decreasing of the mismatch performance of the semiconductor device caused by random doping fluctuation (RDF); and moreover, the carbon diffusion stop layer is helpful for reducing the loss of the ion injection B doping of the NMOS break-through stop layer.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor device and preparation thereof
Method, electronic installation.
Background technology
Along with the development of semiconductor technology, in order to improve the performance of device, need constantly to reduce integrated
The size of circuit devcie, along with constantly reducing of cmos device size, promotes three dimensional design such as fin
The development of field-effect transistor (FinFET).
Relative to existing planar transistor, described FinFET is in raceway groove control and reduces short channel
The aspects such as effect have more superior performance；Planar gate is arranged at above described raceway groove, and
Grid described in FinFET is arranged around described fin, therefore can control electrostatic, at electrostatic from three faces
Performance in terms of control is the most prominent.
Prior art generally uses following processing step to form the fin of FinFET: first, shape on substrate
Become hard mask layer；Then, pattern described hard mask layer, formed and be used for etching substrate to be formed on
Multiple masks being isolated from each other of fin；Then, etching substrate is to be formed on multiple fin；Then,
Isolation structure between the multiple fin of formation of deposits；Finally, described hard mask layer is removed in etching.
FINFET device has superior channel controllability and short-channel effect, but at Bulk FINFET
In due to break-through easy bottom it, thus its short-channel effect strengthen, electric leakage increase.Prior art has
A lot of methods improve the performance of semiconductor device, such as, perform multiple in semiconductor device preparation process
Ion implanting step, stop ion implanting generally to exist including by ion implanting formation well region and raceway groove
NMOS trap performs B or BF2Ion implanting, but B ion is easy to diffuse to shallow trench isolation from oxygen
In compound, the loss of B doping and the decline of mismatch performance are because break-through ion implantation doping (punch
Through imp doping) raceway groove of FINFET device will be diffused to, reduction is risen by it by random doping
Fall the mismatch performance that (Random Doping Fluctuation, RDF) cause；Additionally, form FinFET
Fin after, need implement channel stop inject with control be positioned at the bottom of fin by what part depletion caused
The source/drain break-through in portion.If the injection ion implementing channel stop injection is boron ion or fluorine boron ion,
During subsequent implementation heat treatment, boron ion or fluorine boron ion have the advantages that to be prone to isolation structure diffusion, lead
Cause to be positioned at boron ion or the dose losses of fluorine boron ion of channel region, do not have the work controlling source/drain break-through
With.
In order to improve performance and the yield of semiconductor device, the preparation method to device is needed to make further
Improve, in order to eliminate the problems referred to above.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be in detailed description of the invention
Part further describes.The Summary of the present invention is not meant to attempt to limit institute
The key feature of claimed technical scheme and essential features, more do not mean that and attempt to determine and wanted
Seek the protection domain of the technical scheme of protection.
The present invention is to solve problems of the prior art, it is provided that a kind of semiconductor device, including:
Semiconductor substrate；
Some fin structures, are positioned in described Semiconductor substrate；
Break-through stop-layer, is positioned at the channel region in described fin structure；
Diffusion stop layer, is positioned at the top of break-through stop-layer described in described fin structure.
Alternatively, described diffusion stop layer is carbon diffusion stop layer.
Alternatively, described semiconductor device still further comprises layer of isolation oxide, described isolation oxide
Between layer two fin structure adjacent one another are in described Semiconductor substrate and cover described fin knot
The middle bottom of structure.
Alternatively, the upper surface of described layer of isolation oxide is concordant with described diffusion stop layer upper surface.
Alternatively, the surface of described fin structure is also formed with protective layer.
Present invention also offers the preparation method of a kind of semiconductor device, including:
Step S1: provide Semiconductor substrate and perform diffusion stopping injection, with at the fin knot being subsequently formed
Diffusion stop layer is formed in the channel region of structure；
Step S2: pattern described Semiconductor substrate, to form the described fin comprising described diffusion stop layer
Chip architecture；
Step S3: perform channel stop and inject, with under diffusion stop layer described in described fin structure
Square one-tenth break-through stop-layer.
Alternatively, carbon ion implatation step is performed, to form carbon diffusion stop layer.
Alternatively, described step S1 includes:
Step S11: Semiconductor substrate is provided and forms pad oxide skin(coating) on the semiconductor substrate；
Step S12: perform ion implanting step, to form trap in described Semiconductor substrate；
Step S13: perform described diffusion and stop injecting, to form described diffusion stop layer.
Alternatively, described step S2 includes:
Step S21: form the hard mask layer of patterning on the semiconductor substrate；
Step S22: Semiconductor substrate described in described hard mask layer as mask etch, to form described fin
Chip architecture.
Alternatively, described step S2 may further include the surface formation liner oxidation of described fin structure
Nitride layer and the step of protective layer.
Alternatively, in described step S3, may further comprise: before described channel stop injects
Step S31: deposition layer of isolation oxide, to cover described fin structure；
Step S32: layer of isolation oxide described in etch-back, with fin structure described in exposed portion, is formed
There is the fin structure of object height.
Alternatively, in described step S32, layer of isolation oxide described in etch-back to described fin structure
Described in the upper surface of diffusion stop layer.
Alternatively, after described step S32, may further include the described fin structure that exposes
Surface forms the step of protective layer again.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor device.
The present invention is to solve problems of the prior art, it is provided that a kind of semiconductor device and system thereof
Preparation Method, described method, before forming fin structure and shallow trench isolation oxide, passes through carbon ion
It is infused in described Semiconductor substrate formation Ion implantation diffusion stop-layer, to suppress break-through to stop ion note
Enter the diffusion of doping, improve isolation performance and the mismatch performance of described semiconductor device simultaneously.
It is an advantage of the current invention that and can suppress channel stop leafing by the described carbon diffusion stop layer of introducing
Son injects and diffuses to raceway groove, thus avoid due to random doping fluctuation (Random Doping Fluctuation,
The decline of the semiconductor device mismatch performance RDF) caused, additionally, described carbon diffusion stop layer also helps
Loss in the doping of NMOS break-through stop-layer ion implanting B.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Accompanying drawing shows
Go out embodiments of the invention and description thereof, be used for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1 a-1e is the preparation process schematic diagram of semiconductor device described in embodiments of the present invention；
Fig. 2 is the process chart of semiconductor device described in the embodiment of the invention.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention the most thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without one
Or multiple these details and be carried out.In other example, in order to avoid obscuring with the present invention,
Technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to this
In propose embodiment.On the contrary, it is open thoroughly with complete to provide these embodiments to make, and incite somebody to action this
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He district
Size and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " coupling
Conjunction is arrived " other element or during layer, its can directly on other element or layer, adjacent thereto, connect
Or be coupled to other element or layer, or element between two parties or layer can be there is.On the contrary, claimed when element
For " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other yuan
When part or layer, the most there is not element between two parties or layer.Although it should be understood that can use term first,
Two, the various element of third description, parts, district, floor and/or part, these elements, parts, district,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish an element, parts,
District, floor or part and another element, parts, district, floor or part.Therefore, without departing from the present invention
Under teaching, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ",
" ... on ", " above " etc., here can describe for convenience and be used thus in description figure
A shown element or feature and other element or the relation of feature.It should be understood that except shown in figure
Orientation beyond, spatial relationship term is intended to also include the different orientation of device in using and operating.Example
As, if the device upset in accompanying drawing, then, it is described as " below other element " or " its it
Under " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, example
Property term " ... below " and " ... under " upper and lower two orientations can be included.Device can additionally take
Correspondingly explained to (90-degree rotation or other orientation) and spatial description language as used herein.
The purpose of term as used herein is only that description specific embodiment and the limit not as the present invention
System.When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " forms " and/or " including ",
When using in this specification, determine described feature, integer, step, operation, element and/or parts
Existence, but be not excluded for one or more other feature, integer, step, operation, element, parts
And/or group existence or interpolation.When using at this, term "and/or" includes any of relevant Listed Items
And all combinations.
Embodiment 1
The present invention is to solve problems of the prior art, it is provided that the preparation of a kind of semiconductor device
Method, is described further described method below in conjunction with the accompanying drawings.Wherein, Fig. 1 a-1e is the present invention
Embodiment described in the preparation process schematic diagram of semiconductor device.
First, perform step 201, it is provided that Semiconductor substrate 101, described Semiconductor substrate is formed pad oxygen
Compound layer 102.
As shown in Figure 1a, the most described Semiconductor substrate 101 can be the following material being previously mentioned
At least one in material: stacking silicon (SSOI) on silicon, silicon-on-insulator (SOI), insulator, absolutely
On edge body on stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and insulator
Germanium (GeOI) etc..
Then in described Semiconductor substrate 101, form pad oxide skin(coating) (Pad oxide) 102, Qi Zhongsuo
The forming method stating pad oxide skin(coating) (Pad oxide) can be formed by the method for deposition, such as chemistry
The method such as vapour deposition, ald, it is also possible to by the surface shape of Semiconductor substrate described in thermal oxide
Become, do not repeat them here.
Further, the step performing ion implanting can also be comprised in this step further, with described
Forming trap in Semiconductor substrate, the ionic species wherein injected and method for implanting can be normal in this area
Method, repeat the most one by one at this.
Perform step 202, perform carbon ion implatation step, to form carbon in the channel region being subsequently formed
Diffusion stop layer 103.
Specifically, as shown in Figure 1a, ion implanting step is performed in this step, with at fin to be formed
Described carbon diffusion stop layer 103 is formed in the channel region of structure.
The position of the most described carbon ion implatation is positioned at the position of the channel region of fin structure to be formed
Putting, and be positioned at the lower section of described fin structure object height, the height of the most described fin structure is
1um, the degree of depth of the most described carbon ion implatation is then at below 1um, to ensure the described carbon diffusion resistance formed
Only layer is positioned at the lower section of described target fin structure.Specifically, wherein said carbon diffusion stop layer is positioned at institute
State in the channel region in fin.
In this step, described ion implantation energy needs sufficiently large, and the carbon atom enable reaches predetermined
The position of the degree of depth, alternatively, the energy of the most described ion implanting is 20～30KeV.
Perform step 203, pattern described Semiconductor substrate, to form described fin structure.
Specifically, as shown in Figure 1 b, in Semiconductor substrate 101, multiple fin is formed in this step,
The width of fin is the most identical, or fin is divided into multiple fins group with different in width.
Concrete forming method includes: form hard mask layer (not shown) in Semiconductor substrate 101,
Form the various suitable technique that described hard mask layer can use those skilled in the art to be familiar with, such as
Chemical vapor deposition method, described hard mask layer can be oxide skin(coating) and the silicon nitride of stacking from bottom to top
Layer；Pattern described hard mask layer, formed and be used for etching Semiconductor substrate 101 to be formed on fin
Multiple masks being isolated from each other, in one embodiment, use self-aligned double patterning case (SADP) technique
Implement described patterning process；Etching Semiconductor substrate 101 is to be formed on fin structure.
Perform step 204, formed pad oxide layer 104, with cover Semiconductor substrate 101 surface,
The sidewall of fin structure and the sidewall of described hard mask layer and top.In one embodiment, use now
Field steam generates technique (ISSG) and forms pad oxide layer 104.
Alternatively, covering pad oxide layer 104 protective layer can also be formed in this step, with follow-up
Height and the characteristic size of fin structure are caused damage by the technique implemented.In one embodiment, use
The chemical vapor deposition method (FCVD) with flowable forms protective layer, and the material of protective layer is permissible
For silicon nitride.
Perform step 205, deposit layer of isolation oxide 105, to cover described fin structure.
Specifically, as illustrated in figure 1 c, deposit layer of isolation oxide 105, be filled up completely with fin structure it
Between gap.In one embodiment, the chemical vapor deposition method with flowable is used to implement institute
State deposition.The material of layer of isolation oxide 105 can be with selective oxidation thing, such as HARP.
Perform step 206, layer of isolation oxide 105 described in etch-back is high to the target of described fin structure
Degree.
Specifically, as shown in Figure 1 d, layer of isolation oxide 105 described in etch-back, described in exposed portion
Fin structure, and then form the fin structure with certain height.As example, implement high annealing,
So that layer of isolation oxide 105 densification, the temperature of described high annealing can be 700 DEG C-1000 DEG C；
Perform cmp, until exposing the top of described hard mask layer；Remove in described hard mask layer
Silicon nitride layer, in one embodiment, uses wet etching to remove silicon nitride layer, described wet etching
Corrosive liquid is the Fluohydric acid. of dilution；Remove the oxide skin(coating) in described hard mask layer and part isolation oxide
Layer 105, to expose the part of fin structure, and then forms the fin structure with certain height, one
In individual embodiment, SiCoNi etching is used to implement this removal, the etching gas master of described SiCoNi etching
NH to be had3And NF3。
Alternatively, oxide thin layer thing 102 can also be formed in this step on the surface of the fin structure exposed
, it is beneficial to subsequent implementation well region and injects and channel stop injection.In one embodiment, scene is used
Steam generates technique and forms this oxide thin layer thing 102.
Perform step 207, perform channel stop and inject, stop with diffusion described in described fin structure
The break-through stop-layer formed below of layer.
Specifically, as shown in fig. le, implement channel stop in this step to inject, to form described break-through
Stop-layer 106, controls to be positioned at the source/drain break-through bottom fin structure.The injection that described channel stop injects
Ion is carbon ion, Nitrogen ion or combination, injects ion relative to being perpendicular to Semiconductor substrate
The incident angle in the direction of 101 is 10 °-20 °.
Wherein, described break-through stop-layer is positioned at the underface of described carbon diffusion stop layer, as shown in fig. le,
By introduce described carbon diffusion stop layer can suppress channel stop layer Ion implantation diffusion to raceway groove, thus
Avoid the semiconductor device caused due to random doping fluctuation (Random Doping Fluctuation, RDF)
The decline of part mismatch performance, additionally, described carbon diffusion stop layer additionally aids NMOS break-through stops leafing
Son injects the loss of B doping.
So far, the introduction of the preparation process of the semiconductor device of the embodiment of the present invention is completed.In above-mentioned step
After Zhou, it is also possible to include other correlation step, such as form grid structure on described fin structure,
Here is omitted.Further, in addition to the foregoing steps, the preparation method of the present embodiment can also be upper
Stating among each step or include other steps between different steps, these steps all can be by existing
Various techniques in technology realize, and here is omitted.
The present invention is to solve problems of the prior art, it is provided that a kind of semiconductor device and system thereof
Preparation Method, described method, before forming fin structure and shallow trench isolation oxide, passes through carbon ion
It is infused in described Semiconductor substrate formation Ion implantation diffusion stop-layer, to suppress break-through to stop ion note
Enter the diffusion of doping, improve isolation and the mismatch performance of described semiconductor device simultaneously.
It is an advantage of the current invention that and can suppress channel stop leafing by the described carbon diffusion stop layer of introducing
Son injects and diffuses to raceway groove, thus avoid due to random doping fluctuation (Random Doping Fluctuation,
The decline of the semiconductor device mismatch performance RDF) caused, additionally, described carbon diffusion stop layer also helps
Loss in the doping of NMOS break-through stop-layer ion implanting B.
Fig. 2 is the process chart of semiconductor device described in the embodiment of the invention, including with
Lower step:
Step S1: provide Semiconductor substrate and perform diffusion stopping injection, with at the fin knot being subsequently formed
Diffusion stop layer is formed in the channel region of structure；
Step S2: pattern described Semiconductor substrate, to form the described fin comprising described diffusion stop layer
Chip architecture；
Step S3: perform channel stop and inject, with under diffusion stop layer described in described fin structure
Square one-tenth break-through stop-layer.
Embodiment 2
Present invention also offers a kind of semiconductor device, described semiconductor device is selected described in embodiment 1
Prepared by method.
Described semiconductor device includes:
Semiconductor substrate 101；
Some fin structures, are positioned in described Semiconductor substrate；
Break-through stop-layer, is positioned at the channel region in described fin structure；
Diffusion stop layer 106, is positioned at the top of break-through stop-layer described in described fin structure.
Wherein, described diffusion stop layer is carbon diffusion stop layer, and it is formed by the method for carbon ion implatation,
It is positioned in described fin structure.
Alternatively, described semiconductor device still further comprises layer of isolation oxide, described isolation oxide
Layer is positioned in described Semiconductor substrate and covers the middle bottom of described fin structure.
Alternatively, the upper surface of described layer of isolation oxide is concordant with described diffusion stop layer upper surface.
Alternatively, the surface of described fin structure is also formed with laying.
Semiconductor device of the present invention can suppress channel stop layer by introducing described carbon diffusion stop layer
Ion implantation diffusion is to raceway groove, thus avoids due to random doping fluctuation (Random Doping
Fluctuation, RDF) decline of semiconductor device mismatch performance that causes, additionally, the diffusion of described carbon stops
Only layer additionally aids the loss of NMOS break-through stop-layer ion implanting B doping.
Embodiment 3
Present invention also offers a kind of electronic installation, including the semiconductor device described in embodiment 2.Wherein,
Semiconductor device is the semiconductor device described in embodiment 2, or according to the preparation method described in embodiment 1
The semiconductor device obtained.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book,
Game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, MP3,
Any electronic product such as MP4, PSP or equipment, it is possible to for any centre including described semiconductor device
Product.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has
Better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
It is only intended to citing and descriptive purpose, and is not intended to limit the invention to described scope of embodiments
In.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, root
Can also make more kinds of variants and modifications according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention by the appended claims and etc.
Effect scope is defined.
Claims (14)
1. a semiconductor device, including:
Semiconductor substrate；
Some fin structures, are positioned in described Semiconductor substrate；
Break-through stop-layer, is positioned at the channel region in described fin structure；
Diffusion stop layer, is positioned at the top of break-through stop-layer described in described fin structure.
Semiconductor device the most according to claim 1, it is characterised in that described diffusion stop layer is
Carbon diffusion stop layer.
Semiconductor device the most according to claim 1, it is characterised in that described semiconductor device is also
Farther including layer of isolation oxide, described layer of isolation oxide is positioned in described Semiconductor substrate phase each other
Between two adjacent fin structures and cover the middle bottom of described fin structure.
Semiconductor device the most according to claim 3, it is characterised in that described layer of isolation oxide
Upper surface concordant with described diffusion stop layer upper surface.
Semiconductor device the most according to claim 1, it is characterised in that the table of described fin structure
Face is also formed with protective layer.
6. a preparation method for semiconductor device, including:
Step S1: provide Semiconductor substrate and perform diffusion stopping injection, with at the fin knot being subsequently formed
Diffusion stop layer is formed in the channel region of structure；
Step S2: pattern described Semiconductor substrate, to form the described fin comprising described diffusion stop layer
Chip architecture；
Step S3: perform channel stop and inject, with under diffusion stop layer described in described fin structure
Square one-tenth break-through stop-layer.
Method the most according to claim 6, it is characterised in that in described step S1, performs
Carbon ion implatation step, to form carbon diffusion stop layer.
Method the most according to claim 6, it is characterised in that described step S1 includes:
Step S11: Semiconductor substrate is provided and forms pad oxide skin(coating) on the semiconductor substrate；
Step S12: perform ion implanting step, to form trap in described Semiconductor substrate；
Step S13: perform described diffusion and stop injecting, to form described diffusion stop layer.
9. according to the method described in claim 6 or 8, it is characterised in that described step S2 includes:
Step S21: form the hard mask layer of patterning on the semiconductor substrate；
Step S22: Semiconductor substrate described in described hard mask layer as mask etch, to form described fin
Chip architecture.
Method the most according to claim 6, it is characterised in that described step S2 is wrapped the most further
Include and form pad oxide layer and the step of protective layer on the surface of described fin structure.
11. methods according to claim 6, it is characterised in that in described step S3, described
Channel stop may further comprise: before injecting
Step S31: deposition layer of isolation oxide, to cover described fin structure；
Step S32: layer of isolation oxide described in etch-back, with fin structure described in exposed portion, is formed
There is the fin structure of object height.
12. methods according to claim 11, it is characterised in that in described step S32, return
Etch the described layer of isolation oxide extremely upper surface of diffusion stop layer described in described fin structure.
13. methods according to claim 11, it is characterised in that after described step S32,
The surface that may further include the described fin structure exposed forms the step of protective layer again.
14. 1 kinds of electronic installations, including the semiconductor device one of claim 1 to 6 Suo Shu.
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| CN112582472A (en) * | 2019-09-29 | 2021-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method |
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