CN105990315A - Metal interconnection structure and manufacturing method thereof - Google Patents
Metal interconnection structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN105990315A CN105990315A CN201510041947.1A CN201510041947A CN105990315A CN 105990315 A CN105990315 A CN 105990315A CN 201510041947 A CN201510041947 A CN 201510041947A CN 105990315 A CN105990315 A CN 105990315A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric
- hole
- medium
- buffer medium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a metal interconnection structure and a manufacturing method thereof. The metal interconnection structure comprises an internal interconnection layer, and a top interconnection layer. The internal interconnection layer comprises a first dielectric layer with a first through hole, and an internal metal layer filled in the first through hole. The top interconnection layer comprises a diffusion barrier layer, a buffer dielectric layer, a second dielectric layer, a second through hole and a top metal layer. The diffusion barrier layer, the buffer dielectric layer and the second dielectric layer are sequentially arranged on the internal interconnection layer. The second through hole sequentially penetrates through the second dielectric layer, and the buffer dielectric layer and the diffusion barrier layer and is communicated with the first through hole. The top metal layer is filled inside the second through hole. The mechanical strength of the buffer dielectric layer is larger than the mechanical strength of the first dielectric layer. The buffer dielectric layer, which is larger in mechanical strength, can withstand a large compressive stress from the top metal layer. Therefore, the damage of the large compressive stress of the top metal layer onto the internal structure of the dielectric layer below the top metal layer is reduced, so that the breakdown probability of the dielectric layer is lowered.
Description
Technical field
The application relates to the technical field of semiconductor integrated circuit, in particular to a kind of metal interconnection structure and making side thereof
Method.
Background technology
In existing semiconductor applications, semiconductor circuit have developed into have multilayer interconnection integrated circuit (integrated circuit,
IC).In the IC of multilayer interconnection, the process forming metal interconnection structure includes: by etch media layer to form groove or through hole,
Then in groove or through hole, fill conductive material.Wherein, much new material and the technique of application can improve device further
Performance.The such as dielectric of ultralow dielectric (Ultra low K, ULK, wherein K is dielectric constant and is less than or equal to 2.5)
Material can effectively reduce the RC of integrated circuit (resistance and electric capacity) as dielectric layer and postpone.
Existing metal interconnection structure generally includes the first medium layer 10 ' (usually low dielectric material layer) with the first through hole, and
The diffusion impervious layer 20 ' and second dielectric layer 30 ' (usually SiO sequentially forming on first medium layer2Layer), wherein, second is situated between
Matter layer 30 ' with diffusion impervious layer 20 ' has the second through hole connecting with the first through hole in first medium layer 10 ', and first lead to
Being filled with inner metal layer 410 ' in hole, being filled with top layer metallic layer 420 ' in the second through hole, its structure is as shown in Figure 1.
But, above-mentioned top layer metallic layer 420 ' has bigger compression, can destroy first medium layer 10 ' and second dielectric layer 30 '
Internal structure, make first medium layer 10 ' and second dielectric layer 30 ' be difficult to bear the relatively huge pressing stress from top layer metallic layer 420 ',
So that first medium layer 10 ' and second dielectric layer 30 ' are easy to puncture, and due to first medium layer 10 ' and second medium
Layer 30 ' has very big density contrast, so that first medium layer 10 ' and second dielectric layer 30 ' are more susceptible to damage, Jin Erti
There is breakdown probability in high first medium layer 10 ' and second dielectric layer 30 '.
Content of the invention
The application aims to provide a kind of metal interconnection structure and preparation method thereof, to reduce the top layer metallic layer pair of metal interconnection structure
The damage of the dielectric layer being disposed below, and reduce dielectric layer generation breakdown probability.
To achieve these goals, an aspect according to the application, provides a kind of metal interconnection structure, and this metal links mutually
Structure includes: intraconnection layer, including have the first medium layer of the first through hole, and is filled in the interior metal in the first through hole
Layer；Top interconnection layer, including the diffusion impervious layer being set in turn on intraconnection layer, buffer medium layer and second dielectric layer,
Sequentially pass through second dielectric layer, buffer medium layer and diffusion impervious layer the second through hole connecting with the first through hole, and be filled in
Top layer metallic layer in second through hole, and the mechanical strength of buffer medium layer is more than the mechanical strength of first medium layer.
Further, buffer medium layer includes SiN layer and the 3rd dielectric layer being set in turn on diffusion impervious layer.
Further, the material of first medium layer and the 3rd dielectric layer is dielectric materials, and the density of the 3rd dielectric layer is more than
The density of first medium layer.
Further, the thickness of SiN layer is
Further, the thickness of the 3rd dielectric layer is
Further, the material of diffusion impervious layer is SiN or TiN, and the material of second dielectric layer is SiO2。
Further, the material of inner metal layer and top layer metallic layer is copper or aluminium.
According to the another aspect of the application, providing the preparation method of a kind of metal interconnection structure, this preparation method includes following step
Rapid: forming intraconnection layer, intraconnection layer includes the first medium layer with the first through hole, and is filled in the first through hole
Inner metal layer；And formation top interconnection layer, top interconnection layer includes the diffusion barrier being set in turn on intraconnection layer
Layer, buffer medium layer and second dielectric layer, sequentially pass through second dielectric layer, buffer medium layer and diffusion impervious layer and lead to first
Second through hole of hole connection, and it is filled in the top layer metallic layer in the second through hole, wherein the mechanical strength of buffer medium layer is more than
The mechanical strength of first medium layer.
Further, the step forming top interconnection layer includes: sequentially forms diffusion barrier material layer on intraconnection layer, delay
Rush layer of dielectric material and second medium material layer；It is sequentially etched and run through second medium material layer, buffer medium material layer and diffusion resistance
Obstructing material layer is forming the second through hole, thus forms second dielectric layer, buffer medium layer and diffusion impervious layer；And lead to second
Hole is filled metal material to form described top layer metallic layer.
Further, formed the step of buffer medium material layer include sequentially forming on diffusion barrier material layer SiN material layer and
3rd layer of dielectric material, and the density of the 3rd layer of dielectric material is more than the density of first medium layer；At etching buffer medium material
It in the step of layer, is sequentially etched and runs through the 3rd layer of dielectric material and SiN material layer, include SiN layer and the 3rd dielectric layer to be formed
Buffer medium layer.
Further, in the step forming SiN material layer, the surface of SiN material layer forms ultraviolet resistant.
Further, the step forming the 3rd layer of dielectric material includes: form low dielectric material layer on SiN material layer；To low
Dielectric materials layer carries out UV cured process to form the 3rd layer of dielectric material.
Further, the thickness of SiN material layer isThe thickness of the 3rd layer of dielectric material is
The technical scheme of application the application, is provided with buffer medium layer in the top interconnection layer of metal interconnection structure, and buffering is situated between
Matter layer is arranged at the lower section of top layer metallic layer in top interconnection layer and the top of first medium layer, and the machinery of buffer medium layer
Intensity is more than the mechanical strength of first medium layer.Owing to buffer medium layer has bigger mechanical strength, and it is mutual to be arranged at top layer
Even below layer, therefore, it is possible to bear the relatively huge pressing stress from top layer metallic layer；Simultaneously because buffer medium layer is also located at first Jie
Above matter layer, thus the relatively huge pressing stress decreasing top layer metallic layer is pointed to the damage of dielectric layer internal structure below, enters
And reduce dielectric layer generation breakdown probability.
Brief description
A part of Figure of description constituting the application is used for providing further understanding of the present application, and the application's is schematic real
Execute example and illustrate for explaining the application, being not intended that the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the cross-sectional view of existing metal interconnection structure；
Fig. 2 shows the cross-sectional view of the metal interconnection structure that the application embodiment provided；
Fig. 3 shows the schematic flow sheet of the preparation method of the metal interconnection structure that the application embodiment provided；
Fig. 4 shows in the preparation method of the metal interconnection structure that the application embodiment is provided, and is formed and includes having first
Matrix cross-section structure after the first medium layer of through hole, and the intraconnection layer of the inner metal layer being filled in the first through hole shows
It is intended to；
Fig. 5 shows and sequentially forms diffusion barrier material layer, buffer medium material layer and on the intraconnection layer shown in Fig. 4
Matrix cross-sectional view after second medium material layer；
Fig. 5-1 shows and sequentially forms SiN material layer and the 3rd layer of dielectric material on the diffusion barrier material layer shown in Fig. 5 with shape
Become the matrix cross-sectional view after buffer medium material layer；
Fig. 6 shows to be sequentially etched and runs through the second medium material layer shown in Fig. 5, buffer medium material layer and diffusion barrier material
Layer is forming the second through hole, and forms the matrix cross-sectional view after second dielectric layer, buffer medium layer and diffusion impervious layer；
Fig. 7 shows and fills metal material in the second through hole shown in Fig. 6 with the matrix cross-section structure after forming top layer metallic layer
Schematic diagram.
Detailed description of the invention
It should be noted that in the case of not conflicting, the embodiment in the application and the feature in embodiment can be mutually combined.
Describe the application below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
It should be noted that term used herein above merely to describe detailed description of the invention, and be not intended to restricted root according to this Shen
Illustrative embodiments please.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to
Including plural form, additionally, it should be understood that, when using term "comprising" and/or " including " in this manual, its
Indicate existing characteristics, step, operation, device, assembly and/or combinations thereof.
For the ease of describing, space relative terms here can be used, as " ... on ", " ... top ", " ...
Upper surface ", " above " etc., be used for describing such as the space bit of a device shown in the figure or feature and other devices or feature
Put relation.It should be appreciated that space relative terms is intended to comprise using in addition to device orientation described in the drawings
Or the different azimuth in operation.For example, it if the device in accompanying drawing is squeezed, then is described as " above other devices or construction "
Or will be positioned as after the device of " on other devices or construction " " at other devices or construct below " or " at other devices or
Under construction ".Thus, exemplary term " in ... top " can include " in ... top " and " in ... lower section " two kinds of orientation.
This device also can be with other different modes positioning (90-degree rotation or be in other orientation), and to space used herein above phase
Respective explanations is made to description.
As described in background technology, the top layer metallic layer 420 ' of existing metal interconnection structure has stronger compression, and
First medium layer 10 ' and second dielectric layer 30 ' have very big density contrast, so that first medium layer 10 ' and second dielectric layer 30 '
It is easy to puncture.Present inventor studies for the problems referred to above, it is proposed that a kind of metal interconnection structure and system thereof
Make method.As in figure 2 it is shown, this metal interconnection structure includes: intraconnection layer, including have the first medium layer of the first through hole
10, and the inner metal layer 410 being filled in the first through hole；Top interconnection layer, including be set in turn on intraconnection layer
Diffusion impervious layer the 20th, buffer medium layer 30 and second dielectric layer 50, sequentially pass through second dielectric layer the 50th, buffer medium layer 30 and
Diffusion impervious layer 20 the second through hole connecting with the first through hole, and the top layer metallic layer 420 being filled in the second through hole, and
The mechanical strength of buffer medium layer 30 is more than the mechanical strength of first medium layer 10.
Above-mentioned metal interconnection structure is had the buffer medium layer 30 of bigger mechanical strength by arranging, and buffer medium layer 30 is arranged
Below top interconnection layer, make buffer medium layer 30 can bear the relatively huge pressing stress from top layer metallic layer 420；Simultaneously because
Buffer medium layer 30 is also located above first medium layer 10, thus the relatively huge pressing stress decreasing top layer metallic layer 420 is pointed to
The damage of the internal structure of first medium layer 10 below, and then reduce dielectric layer generation breakdown probability.
In the above-mentioned metal interconnection structure of the application, those skilled in the art can set buffering according to teachings of the present application and be situated between
The structure composition of matter layer 30.Preferably, buffer medium layer 30 includes the SiN layer 310 being set in turn on diffusion impervious layer 20
With the 3rd dielectric layer 320.Further, the material of first medium layer 10 and the 3rd dielectric layer 320 can be dielectric materials,
And the density of the 3rd dielectric layer 320 is more than the density of first medium layer 10.In above-mentioned buffer medium layer 30, there is density
The 3rd bigger dielectric layer 320, so that buffer medium layer 30 has bigger mechanical strength, and then can bear from top layer
The relatively huge pressing stress of metal level 420.
In the above-mentioned metal interconnection structure of the application, the thickness of SiN layer 310 and the 3rd dielectric layer 320 can be according to the actual requirements
It is set, it is preferable that the thickness of SiN layer 310 isThe thickness of the 3rd dielectric layer 320 is?
In above-mentioned preferred thickness range, SiN layer 310 and the 3rd dielectric layer 320 can have bigger mechanical strength, bear further
Relatively huge pressing stress from top layer metallic layer 420.
In the above-mentioned metal interconnection structure of the application, diffusion impervious layer the 20th, second dielectric layer the 50th, inner metal layer 410 and top
Layer metal level 420 material also can be set according to the actual requirements, it is preferable that the material of diffusion impervious layer 20 be SiN or
TiN, the material of second dielectric layer 50 is SiO2；The material of inner metal layer 410 and top layer metallic layer 420 is copper or aluminium.More
For preferably, the material of inner metal layer 410 and top layer metallic layer 420 can be the copper product with more high conductivity.Wherein,
Diffusion impervious layer 20 can also include BD (Black Diamond, black diamond mainly comprise SiCOH) layer and be positioned at BD layer
On silicon dioxide layer (being prepared by TEOS), above-mentioned diffusion impervious layer 20 is mainly used to stop that impurity enters it and covered
Dielectric layer, thus improve the reliability of device architecture.
Meanwhile, present invention also provides the preparation method of a kind of metal interconnection structure.As it is shown on figure 3, this preparation method include with
Lower step: form intraconnection layer, intraconnection layer includes the first medium layer with the first through hole, and it is logical to be filled in first
Inner metal layer in hole；And formation top interconnection layer, top interconnection layer includes the diffusion being set in turn on intraconnection layer
Barrier layer, buffer medium layer and second dielectric layer, sequentially pass through second dielectric layer, buffer medium layer and diffusion impervious layer and with
Second through hole of one through hole connection, and it is filled in the top layer metallic layer in the second through hole, the wherein mechanical strength of buffer medium layer
Mechanical strength more than first medium layer.
In above-mentioned preparation method, the buffer medium layer owing to being formed at below top layer metallic layer has bigger mechanical strength, therefore
The relatively huge pressing stress from top layer metallic layer can be born, simultaneously because buffer medium layer is also located above first medium layer, thus
The relatively huge pressing stress decreasing top layer metallic layer is pointed to the damage of dielectric layer internal structure below, and then reduces dielectric layer
There is breakdown probability.
The illustrative embodiments of preparation method of the metal interconnection structure providing according to the application is provided.So
And, these illustrative embodiments can be implemented by multiple different forms, and should not be construed to be limited solely to institute here
The embodiment illustrating.It should be appreciated that these embodiments are provided so that disclosure herein is thorough and complete,
And the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, in order to understand
See, expand the thickness in layer and region, and make to be presented with like reference characters identical device, thus by omission to them
Description.
Fig. 4 to Fig. 7 shows in the preparation method of the metal interconnection structure that the application provides, the base obtaining after each step
The cross-sectional view of body.Below in conjunction with Fig. 4 to Fig. 7, further illustrate the system of metal interconnection structure provided herein
Make method.
First, the first medium layer 10 including there is the first through hole is formed, and the inner metal layer 410 being filled in the first through hole
Intraconnection layer, and then form basal body structure as shown in Figure 4.The method forming this first through hole has a variety of, in one
In preferred embodiment, the step forming the first through hole in first medium layer 10 includes: is formed and is covered in first medium successively
Groove masking layer on layer 10 surface and graphical photoresist, along graphical photoresist etching groove masking layer and first medium layer 10
To form the first through hole.The process conditions of photoetching can be set according to actual process demand, does not repeats them here.Wherein,
The material of first medium layer 10 can be dielectric materials, and the material of inner metal layer 410 can be copper or aluminium, it is further preferable that
The material of inner metal layer 410 can be the copper product with more high conductivity.
Complete to be formed the first medium layer 10 including that there is the first through hole, and the inner metal layer 410 being filled in the first through hole
Intraconnection layer step after, formed and include diffusion impervious layer the 20th, the buffer medium layer that is set in turn on intraconnection layer
30 and second dielectric layer 50, sequentially pass through second dielectric layer the 50th, buffer medium layer 30 and diffusion impervious layer 20 and with the first through hole
Second through hole of connection, and the top interconnection layer of the top layer metallic layer 420 being filled in the second through hole, wherein buffer medium layer
The mechanical strength of 30 is more than the mechanical strength of first medium layer 10.Further, above-mentioned diffusion impervious layer 20 can also include
BD (Black Diamond, black diamond mainly comprise SiCOH) layer and the silicon dioxide layer that is positioned on BD layer are (by TEOS
Prepare), above-mentioned diffusion impervious layer 20 is mainly used to stop that impurity enters its dielectric layer being covered, thus improves device junction
The reliability of structure.
In a preferred embodiment, the step of formation top interconnection layer may include that and sequentially forms on intraconnection layer
Diffusion barrier material layer the 21st, buffer medium material layer 31 and second medium material layer 51, and then form matrix as shown in Figure 5
Structure；It is sequentially etched and run through second medium material layer the 51st, buffer medium material layer 31 and diffusion barrier material layer 21 to form
Two through holes, thus form second dielectric layer the 50th, buffer medium layer 30 and diffusion impervious layer 20, and then formed as shown in Figure 6
Basal body structure；And in the second through hole, fill metal material forming top layer metallic layer 420, and then form base as shown in Figure 7
Body structure.Above-mentioned second through hole can be formed by photoetching process, and the process conditions of photoetching can be carried out according to actual process demand
Set, do not repeat them here.Preferably, the material of second dielectric layer 50 is SiO2, the material of inner metal layer 410 be copper or
Aluminium, further, the material of inner metal layer 410 can be the copper product with more high conductivity.
In the step forming above-mentioned buffer medium layer 30, one is preferred embodiment: on diffusion barrier material layer 21
Sequentially form SiN material layer 311 and the 3rd layer of dielectric material 321, and the density of the 3rd layer of dielectric material 321 is more than first Jie
The density of matter layer 10, and then form basal body structure as shown in fig. 5-1；In the step of etching buffer medium material layer 31, depend on
Secondary etching runs through the 3rd layer of dielectric material 321 and SiN material layer 311, includes SiN layer 310 and the 3rd dielectric layer 320 to be formed
Buffer medium layer 30.Due in above-mentioned buffer medium material layer 31, there is the 3rd bigger dielectric layer 320 of density, so that after
The continuous buffer medium layer 30 being formed has bigger mechanical strength, and then the bigger pressure can born from top layer metallic layer 420 should
Power.
The method forming the 3rd layer of dielectric material 321 has a variety of, in a preferred embodiment, at SiN material layer
The step forming the 3rd layer of dielectric material 321 on 311 includes: form low dielectric material layer on SiN material layer 311；To low Jie
Material layer carries out UV cured process to form the 3rd layer of dielectric material 321.Meanwhile, in the step forming SiN material layer 311
In Zhou, it is preferable that form ultraviolet resistant on the surface of SiN material layer 311.Above-mentioned UV cured process can carry
The mechanical strength of high 3rd layer of dielectric material 321, so that the buffer medium layer 30 being subsequently formed has bigger mechanical strength,
And then relatively huge pressing stress from top layer metallic layer 420 can be born.Meanwhile, above-mentioned ultraviolet resistant can reduce SiN material
The ultraviolet that the bed of material 311 is subject in the step of UV cured process irradiates.
Above-mentioned preferred embodiment in, the thickness of SiN layer 310 and the 3rd dielectric layer 320 can set according to the actual requirements
Fixed, it is preferable that the thickness of SiN layer 310 isThe thickness of the 3rd dielectric layer 320 isAbove-mentioned excellent
In the thickness range of choosing, SiN layer 310 and the 3rd dielectric layer 320 can have bigger mechanical strength, bear from top further
The relatively huge pressing stress of layer metal level 420.
As can be seen from the above description, the application the above embodiments achieve following technique effect: this application provides
A kind of metal interconnection structure being provided with buffer medium layer in top interconnection layer, buffer medium layer is arranged under top interconnection layer
Side and the top of first medium layer, and the mechanical strength of buffer medium layer is more than the mechanical strength of first medium layer.Owing to delaying
Rush dielectric layer and there is bigger mechanical strength, and be arranged at below top interconnection layer, therefore, it is possible to bear from top layer metallic layer
Relatively huge pressing stress；Simultaneously because buffer medium layer is also located above first medium layer, thus decrease the bigger of top layer metallic layer
Compression is pointed to the damage of dielectric layer internal structure below, and then reduces dielectric layer generation breakdown probability.
These are only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art,
The application can have various modifications and variations.All within spirit herein and principle, any modification of being made, equivalent,
Improve, should be included within the protection domain of the application.
Claims (13)
1. a metal interconnection structure, it is characterised in that described metal interconnection structure includes:
Intraconnection layer, including have the first medium layer of the first through hole, and is filled in the inside in described first through hole
Metal level；
Top interconnection layer, including the diffusion impervious layer being set in turn on described intraconnection layer, buffer medium layer and second
Dielectric layer, sequentially passes through described second dielectric layer, described buffer medium layer and described diffusion impervious layer and leads to described first
Second through hole of hole connection, and it is filled in the top layer metallic layer in described second through hole, and the machine of described buffer medium layer
Tool intensity is more than the mechanical strength of described first medium layer.
2. metal interconnection structure according to claim 1, it is characterised in that described buffer medium layer includes being set in turn in institute
State the SiN layer on diffusion impervious layer and the 3rd dielectric layer.
3. metal interconnection structure according to claim 2, it is characterised in that described first medium layer and described 3rd dielectric layer
Material be dielectric materials, and the density of described 3rd dielectric layer is more than the density of described first medium layer.
4. metal interconnection structure according to claim 2, it is characterised in that the thickness of described SiN layer is
5. metal interconnection structure according to claim 3, it is characterised in that the thickness of described 3rd dielectric layer is
6. metal interconnection structure according to claim 1, it is characterised in that the material of described diffusion impervious layer is SiN or TiN,
The material of described second dielectric layer is SiO2。
7. metal interconnection structure according to claim 1, it is characterised in that described inner metal layer and described top layer metallic layer
Material be copper or aluminium.
8. the preparation method of a metal interconnection structure, it is characterised in that described preparation method comprises the following steps:
Forming intraconnection layer, described intraconnection layer includes the first medium layer with the first through hole, and is filled in institute
State the inner metal layer in the first through hole；And
Form top interconnection layer, diffusion impervious layer that described top interconnection layer includes being set in turn on described intraconnection layer,
Buffer medium layer and second dielectric layer, sequentially pass through described second dielectric layer, described buffer medium layer and described diffusion barrier
Layer the second through hole connecting with described first through hole, and it is filled in the top layer metallic layer in described second through hole, wherein
The mechanical strength of described buffer medium layer is more than the mechanical strength of described first medium layer.
9. preparation method according to claim 8, it is characterised in that the step forming described top interconnection layer includes:
Described intraconnection layer sequentially forms diffusion barrier material layer, buffer medium material layer and second medium material layer；
Be sequentially etched run through described second medium material layer, described buffer medium material layer and described diffusion barrier material layer with
Form described second through hole, thus form described second dielectric layer, described buffer medium layer and described diffusion impervious layer；With
And
Fill metal material to form described top layer metallic layer in described second through hole.
10. preparation method according to claim 9, it is characterised in that
The step forming described buffer medium material layer includes sequentially forming SiN material layer and on diffusion barrier material layer
Three layer of dielectric material, and the density of described 3rd layer of dielectric material is more than the density of described first medium layer；
It in the step of the described buffer medium material layer of etching, is sequentially etched and runs through described 3rd layer of dielectric material and described SiN
Material layer, to form the described buffer medium layer including SiN layer and the 3rd dielectric layer.
11. preparation methods according to claim 10, it is characterised in that in the step forming described SiN material layer, in institute
State formation ultraviolet resistant on the surface of SiN material layer.
12. preparation methods according to claim 10, it is characterised in that the step forming described 3rd layer of dielectric material includes:
Described SiN material layer forms low dielectric material layer；
Carry out UV cured process to form described 3rd layer of dielectric material to described low dielectric material layer.
13. preparation methods according to according to any one of claim 10 to 12, it is characterised in that the thickness of described SiN material layer
ForThe thickness of described 3rd layer of dielectric material is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510041947.1A CN105990315B (en) | 2015-01-27 | 2015-01-27 | Metal interconnection structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510041947.1A CN105990315B (en) | 2015-01-27 | 2015-01-27 | Metal interconnection structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990315A true CN105990315A (en) | 2016-10-05 |
| CN105990315B CN105990315B (en) | 2019-01-29 |
Family
ID=57036376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510041947.1A Active CN105990315B (en) | 2015-01-27 | 2015-01-27 | Metal interconnection structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990315B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166840A (en) * | 2018-08-28 | 2019-01-08 | 武汉新芯集成电路制造有限公司 | Polycrystalline circle stacked structure and forming method thereof |
| CN109309057A (en) * | 2017-07-26 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030020168A1 (en) * | 2001-07-30 | 2003-01-30 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US20030134505A1 (en) * | 2002-01-17 | 2003-07-17 | International Business Machines Corporation | Fine-pitch device lithography using a sacrificial hardmask |
| CN101030566A (en) * | 2006-03-01 | 2007-09-05 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| CN101689412A (en) * | 2007-07-06 | 2010-03-31 | 富士通株式会社 | Insulating film material, multilayer wiring board and process for producing the multilayer wiring board, and semiconductor apparatus and process for producing the semiconductor device |
-
2015
- 2015-01-27 CN CN201510041947.1A patent/CN105990315B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030020168A1 (en) * | 2001-07-30 | 2003-01-30 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US20030134505A1 (en) * | 2002-01-17 | 2003-07-17 | International Business Machines Corporation | Fine-pitch device lithography using a sacrificial hardmask |
| CN101030566A (en) * | 2006-03-01 | 2007-09-05 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| CN101689412A (en) * | 2007-07-06 | 2010-03-31 | 富士通株式会社 | Insulating film material, multilayer wiring board and process for producing the multilayer wiring board, and semiconductor apparatus and process for producing the semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309057A (en) * | 2017-07-26 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109166840A (en) * | 2018-08-28 | 2019-01-08 | 武汉新芯集成电路制造有限公司 | Polycrystalline circle stacked structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990315B (en) | 2019-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106033741B (en) | Metal internal connection structure and its making method | |
| US8064224B2 (en) | Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same | |
| US7999388B2 (en) | Preventing breakage of long metal signal conductors on semiconductor substrates | |
| WO2015021265A3 (en) | Embedded packaging with preformed vias | |
| US10923455B2 (en) | Semiconductor apparatus and method for preparing the same | |
| US8987859B2 (en) | Techniques for enhancing dielectric breakdown performance | |
| US20080174020A1 (en) | Electronic device having metal pad structure and method of fabricating the same | |
| CN105990315A (en) | Metal interconnection structure and manufacturing method thereof | |
| JP2004172620A (en) | Integrated circuit with air gaps and its manufacturing method | |
| CN104425440B (en) | A kind of semiconductor devices and forming method thereof | |
| CN109545735B (en) | Metal internal connection structure and its making method | |
| CN104701271A (en) | Semiconductor structure and forming method thereof | |
| CN104465728A (en) | Gate structure of separation gate power device and process method | |
| CN105489581B (en) | Semiconductor structure and preparation method thereof | |
| CN102543854A (en) | Method for overcoming defect of copper bumps in copper interconnecting structure | |
| CN110707068A (en) | Semiconductor interconnection structure and preparation method thereof | |
| US8629536B2 (en) | High performance on-chip vertical coaxial cable, method of manufacture and design structure | |
| US20140054790A1 (en) | Three-dimensional integrted circuit structure and method of aluminum nitride interposer substrate | |
| CN104752405A (en) | Semiconductor device test structure and forming method thereof | |
| CN105206600B (en) | Semi-conductor test structure | |
| CN103165436B (en) | Make the method for semiconductor device | |
| CN105280617A (en) | Heavily doped silicon shielding silicon through hole structure and manufacturing method thereof | |
| KR101016340B1 (en) | Method of manufacturing inductor in RF semiconductor device | |
| US9412657B2 (en) | Method for manufacturing semiconductor device | |
| CN102709233A (en) | Formation method for copper double-Damask structure and manufacturing method for semi-conductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |