CN105990238B - Metal gate preparation method - Google Patents
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- CN105990238B CN105990238B CN201510061913.9A CN201510061913A CN105990238B CN 105990238 B CN105990238 B CN 105990238B CN 201510061913 A CN201510061913 A CN 201510061913A CN 105990238 B CN105990238 B CN 105990238B
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Abstract
The present invention relates to technical field of semiconductor preparation; specifically provide a kind of metal gate preparation method; the present invention is a kind of HKMG preparation process based on gate last; hard mask layer is prepared by the thinned wherein sample grid of a device region and at the top of it; later when other device regions prepare metal gate and ground; hard mask layer can effectively play the uniformity protected sample grid below from damage, and then improve device surface after grinding.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, specifically, are related to after metal in the technique of grid, specific to provide
A kind of metal gate preparation method.
Background technique
With the continuous development of technology, semiconductor technology has infiltrated into the every field in life, such as space flight, medical treatment
Device is guarded against, mobile communication all be unable to do without chip prepared by semiconductor.
Many chips were all using silica as gate dielectric in the past, but since 65nm, due to technology section
Point very little, can not allow gate dielectric continue to shorten it is thinning, while with the continuous diminution of transistor size, source electrode and leakage
The distance between pole is also smaller and smaller, and then be easy to cause short-channel effect.Therefore, in view of the above-mentioned problems, those skilled in the art
Through unremitting research, HKMG (High-K Metal Gate, Gao Jie electricity metal gate) technique is developed member.It is using one kind
Gate dielectric with high dielectric constant (or high K), and prepared as grid using HKMG technique using metal material
Device compare for traditional devices, be greatly reduced leakage current, while effectively improving driving current, thus HKMG at
Mainstream technology used by current high-performance transistor.
Meanwhile in HKMG to be applied to gate last (rear grid) technique, preparation flow can refer to Fig. 1 a~1h institute
Show: a substrate 100 is provided comprising there are the region (i.e. diagram NFET) N-MOSFET and the region P-MOSFET (i.e. diagram PFET),
The region N-MOSFET and the region P-MOSFET are isolated by shallow trench 102.In the region N-MOSFET and the region P-MOSFET
Substrate 100 on be prepared with first sample grid 101A and the second sample grid 101B respectively, be deposited with dielectric layer in device surface
(i.e. interlayer dielectric layer, Interlayer dielectric layer, ILD) 108, as shown in Figure 1a.First with photoetching work
Skill removes the second sample grid 101B and fills the first metal gate material layer 103, is ground later, such as Fig. 1 b~1e
It is shown；Primary row photoetching process is recycled later, to remove first sample grid 101A and fill second grid material layer 104, and
It carries out back-end process (Back End Of Line, BEOL).
But those skilled in the art have found, in deposition first grid material layer 103 and to the first grid material layer 103
It is sample grid as present at this time in the region N-MOSFET during being ground, and in the region P-MOSFET
It is existing, it is the gate material layers of subsequent filling, and simultaneously, 108 three of metal gate material, sample grid material and dielectric layer
Material be all different, sample grid are generally polysilicon, and dielectric layer is generally oxide, and the grid material of subsequent deposition is then
Metallic aluminium, above-mentioned material grinding rate can refer to shown in Fig. 2 there are relatively big difference, wherein diagram abscissa is the straight of wafer
Diameter, ordinate are grinding rate.In general, metal (Al) grinding rate > polysilicon (Poly) grinding rate > oxide
(OX) grinding rate.Therefore when being ground, the grinding rate of each abrasive areas is simultaneously different, it is easy to lead to over
Polish (cross polish) and the phenomenon that bridge (bridge joint), generate, while being also easy recessed in sample grid near zone formation butterfly
It falls into, this is that those skilled in the art are not wanted to see that.
Summary of the invention
Deficiency provides a kind of grid preparation method to the present invention according to prior art, can effectively avoid to grid material
During layer is deposited, the grinding damage caused by sample grid.
The technical solution adopted by the present invention are as follows:
A kind of metal gate preparation method, wherein include the following steps:
Step S1, a substrate is provided, the substrate surface is covered with a dielectric layer, is formed with the first grid in the dielectric layer
Slot and second gate slot are provided with first sample grid in the first grid slot, the second sample grid are provided in the second gate slot；
The height of first sample grid is less than the thickness of dielectric layer, and the height of the second sample grid is equal to the thickness of dielectric layer；
Step S2, it prepares one layer of hard mask layer to be covered at the top of the first sample grid and the second sample grid, and will be described
Clearance space in first grid slot on first sample grid is filled completely；
Step S3, the hard mask layer on the second sample grid is removed completely, while being removed on first sample grid
A part of hard mask layer simultaneously retains the part hard mask layer on first sample grid；
Step S4, the dielectric layer is ground, removes part the second sample grid and will be more than on first sample grid
Under hard mask layer carry out part removal；
Step S5, etching is to remove completely remaining second sample grid in second gate slot；
Step S6, it fills in metal to second gate slot and is ground, nationality is covered firmly by remaining on first sample grid
Film layer ensures first sample grid during the grinding process from damage.
Above-mentioned method, wherein the first sample grid are located at the dielectric layer in substrate on a region N-MOSFET
In, the second sample grid are located in the dielectric layer in substrate on a region P-MOSFET.
Above-mentioned method, wherein the first sample grid are located at the dielectric layer in substrate on a region P-MOSFET
In, the second sample grid are located in the dielectric layer in substrate on a region N-MOSFET.
Above-mentioned method, wherein pass through shallow trench between the region N-MOSFET in the substrate and the region P-MOSFET
Isolation structure is isolated.
Above-mentioned method, wherein the first sample grid are performed etching using lithography and etching technique, remove part institute
First sample grid are stated, so that the height of the first sample grid is less than the thickness of dielectric layer.
Above-mentioned method, wherein the hard mask layer is SiN.
Above-mentioned method, wherein the dielectric layer is oxide layer.
Above-mentioned method, wherein in step S4 and step S6, the grinding is chemical mechanical grinding.
Above-mentioned method, wherein after removing the second sample grid, and before filling metal, first prepare K one layer high and be situated between
Electric layer is covered on the surface of second gate slot exposure.
Above-mentioned method, wherein the sample grid are polysilicon or amorphous carbon.
The present invention is improved based on one of gate last technique, by the way that a wherein device region (N-type device region is thinned
Or P-type device area) sample grid and prepare hard mask layer at the top of it, prepare metal gate in other device regions later and ground
When mill, hard mask layer, which can effectively play, protects the sample grid below hard mask layer from damage, and then improves device after grinding
The uniformity on surface.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in all the attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is show the gist of the present invention.
Fig. 1 a~1h is the broad flow diagram of gate last technique in the prior art；
Fig. 2 is the grinding rate comparison diagram of aluminium, polysilicon and oxide；
Fig. 3 a~3e is the substantially flow chart that the present invention prepares metal gate；
Fig. 4 a~4g is the method flow diagram that the present invention prepares metal gate in one embodiment.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
A kind of metal gate preparation method includes the following steps: referring to shown in Fig. 3 a-3e
Step S1, a substrate is provided, substrate surface is covered with a dielectric layer (not indicating in figure), and the is formed in dielectric layer
One grid slot and second gate slot are provided with first sample grid 101A in first grid slot, the second sample grid are provided in second gate slot
101B；The height of first sample grid is less than the thickness of dielectric layer, and the height of the second sample grid is equal to the thickness of dielectric layer.
Wherein, the region N-MOSFET (such as P-well) and the region P-MOSFET (such as N- are provided in the substrate
Well), and between the region N-MOSFET and the region P-MOSFET it is isolated by fleet plough groove isolation structure.Shallow trench isolation knot
Structure is the insulating materials that such as oxide etc is filled in groove, can be by the N- in substrate using fleet plough groove isolation structure
MOSFET region and the region P-MOSFET are spaced apart.It is optional but that is not intended as in the embodiment of limitation one, above-mentioned the
One sample grid 101A is located in the dielectric layer on a region N-MOSFET in substrate, and the second sample grid 101B is located at lining
In the dielectric layer on a region P-MOSFET in bottom.Can also have other embodiments in the present invention simultaneously, such as the
One sample grid 101A is located in the dielectric layer on a region P-MOSFET in substrate, then the second sample grid 101B is located at
In the dielectric layer on a region N-MOSFET in substrate.Those skilled in the art can select in P- according to actual needs
Hard mask layer is formed at the top of the sample grid in the region MOSFET and/or N-MOSFET.
One is optional but simultaneously embodiment is without limiting, by lithography and etching technique come to first sample grid 101A into
Row etching, makes its height be less than the thickness of dielectric layer.Specifically, one layer photoresist of spin coating is covered in dielectric layer and first, second
The upper surface of sample grid is exposed developing process by a mask plate with exposing patterns later, with shape in the photoresist
It is later etch mask to first sample grid 101A to have the photoresist of opening at the opening for exposing first sample grid 101A
It performs etching, removes part first sample grid 101A to reduce its height, so that the height of first sample grid 101A is low
In the thickness of dielectric layer, and the second sample grid 101B height is identical as the thickness of dielectric layer, therefore first sample grid 101A
Height is less than the second sample grid 101B height；Simultaneously because first sample grid 101A is to be located in first grid slot, therefore dropping
After low first sample grid 101A height, a clearance space can be reserved at the top of the first sample grid 101A in first grid slot.
In the present invention, it is preferred to which polysilicon (poly-silicon) can be used as above-mentioned first sample grid and the second sample
This grid, but it is not limited only to aforesaid way in practical applications, for example, by using amorphous carbon (A-C) as sample grid
It is equally applicable in the present invention.It should be appreciated to those skilled in the art that generally being adopted when using polysilicon as sample grid
When removing polysilicon sample grid with the mode of etching, and using amorphous carbon as sample grid, then it can lead under the high temperature conditions
Enter O2, O2It is reacted with amorphous carbon generation and generates CO2Gas is simultaneously discharged, and prepares for subsequent deposition grid.In the present invention to use
Polysilicon is illustrated as sample grid.
Step S2, one layer of hard mask layer 105 is prepared to be covered at the top of first sample grid 101A and the second sample grid 101B, and
The clearance space being located on first sample grid 101A in first grid slot is filled completely.As shown in Figure 3a.
In the present invention, it is preferred to depositional mode can be used to form layer of sin layer as above-mentioned hard mask layer 105.
It since the SiN layer compactness of deposition is stronger, and is easier to be completely removed in the follow-up process, while SiN is also semiconductor neck
A kind of thin-film material commonly used by domain, therefore process variations are small, cost of implementation is relatively low.After depositing hard mask layer 105, also need
Planarization process is carried out to hard mask layer 105, so that the top surface of hard mask layer 105 flushes, such as eatch-back can be used
(each back) or CMP (chemical mechanical grinding) to carry out planarization process to hard mask layer.
Step S3, the hard mask layer 105 on the second sample grid 101B is removed completely, while removing first sample grid
A part of hard mask layer 105 on 101A and the reservation part hard mask layer 105 on first sample grid 101A.Such as Fig. 3 b institute
Show.
In the process, come using the technique of SPT (stress proximity technology, pressure close to technology)
The hard mask layer on the second sample grid is removed completely, and removes the part hard mask layer on first sample grid.
Step S4, dielectric layer is ground, removal part the second sample grid 101B simultaneously will be on first sample grid 101A
Remaining hard mask layer carry out part removal.As shown in Figure 3c.
An optional embodiment is to be ground using CMP process to dielectric layer, while being ground, also can
The hard mask layer at the top of top and first sample grid to the second sample grid removes so that the top surface of hard mask layer 105 with
The top surface of second sample grid 101B flushes.
Step S5, etching is to remove completely remaining second sample grid 101B in second gate slot.As shown in Figure 3d.
One optional but simultaneously embodiment without limiting is to be removed completely remaining in second gate slot using etching technics
Two sample grid 101B.In the process, the etching to the second sample grid 101B, substantially step can be realized by photoetching process
Are as follows: one layer photoresist of spin coating is covered on the upper surface of device, is exposed later by a mask plate with exposing patterns aobvious
Shadow technique, to form the opening for exposing second gate slot in the photoresist, later to have the photoresist of opening as etch mask
Second sample grid 101B is performed etching, until the second sample grid 101B in second gate slot is removed completely, is finally removed surplus
Remaining photoresist.Meanwhile in order to further ensure the precision of photoetching and inhibiting reflection, one layer of bottom anti-reflective can be also coated in advance
Layer (BARC) is covered on device surface, later spin coating photoresist again, so reduce in exposure process due to the reflection of light from
And the phenomenon that causing to photoresist overexposure, it should be appreciated to those skilled in the art that the step of coating bottom anti-reflection layer
Suddenly it is optional way, directly spin coating photoresist and photoetching process can also be carried out in practical applications, the present invention is had no effect on.
Step S6, fill in metal 103 to second gate slot and carry out CMP milled processed, nationality by first sample grid 101A it
On remaining hard mask layer 105 ensure first sample grid 101A during the grinding process from damage.As shown in Figure 3 e.
In this step, it deposits one layer of metal 103 to be filled second gate slot, carries out grinding technics later with by medium
The metal that layer and first grid groove top portion are covered is removed, and only retains the metal being located in second gate slot as metal gate, and
Simultaneously because the top first sample grid 101A in first grid slot also remains with hard mask layer 105, and hard mask layer 105 is selected
The lesser SiN of grinding rate, therefore when the metal 103 to deposition is ground, it will not be to the first sample in first grid slot
Grid 101A causes grinding damage, while the butterfly groove for also avoiding being easy to produce in first grid slot and dielectric layer intersection lacks
It falls into.
Further, it after removing the second sample grid 101B, and before filling metal 103, first prepares K one layer high and is situated between
Electric layer is covered on the surface of second gate slot exposure, is isolated for metal gate and dielectric layer, substrate.
One is provided below based on the specific embodiment of gate last and in conjunction with attached drawing further to be explained the present invention
It states, it should be noted that associated description hereafter is to form hard mask layer at the top of the sample grid in the region N-MOSFET
Grinding damage is avoided, but in other embodiments of the present invention, also it can be formed at the top of the sample grid in the region P-MOSFET
The protection of hard mask layer shape paired samples grid, step with it is hereafter essentially identical, although herein it is detailed description in P-
Hard mask layer and subsequent correlation step are formed at the top of sample grid in MOSFET region, but those skilled in the art being capable of root
According to the present invention can be beyond all doubt obtain other embodiments, therefore no longer detailed description.
Referring to shown in Fig. 4 a-4g, include the following steps:
A semiconductor substrate 100 with the region N-MOSFET and the region P-MOSFET is provided first, on substrate 100
It is deposited with dielectric layer 108,108 form first grid slot in the dielectric layer on N-MOSFET, are provided with first in first grid slot
Sample grid 101A；Likewise, 108 form second gate slot in the dielectric layer being located on P-MOSFET, the is provided in second gate slot
Two sample grid 101B.
Wherein, it is isolated by shallow trench (STI) 102 between N-MOSFET and P-MOSFET, is filled out in shallow trench 102
Insulating materials filled with such as oxide etc.In addition, the surface of the device is also covered with dielectric layer 108, and above-mentioned first,
Second gate groove top facial planes is flushed with the top planes of dielectric layer 108.The present invention is changed based on what gate last technique was made
Into, being specifically based on gate last technique and preparing above-mentioned device can be used the usual technological means of those skilled in the art,
It will not go into details for this.
Later, part first sample grid 101A is removed, one layer of hard mask layer 105 is prepared and is covered on remaining first sample grid top
Portion 101A is simultaneously filled first grid slot completely.
Specifically, one layer photoresist of spin coating covers device surface completely first, it is exposed developing process later,
The photoresist of covering in the first region is removed, and then first sample grid 101A is exposed；Using etching technics (such as dry method
Etching, dry etch) part first sample grid 101A is removed, to reduce its height.One layer of hard mask layer 105 is deposited by the first grid
Slot is filled and is covered in the surface of device, removes completely the hard mask layer on the second sample grid 101B later, together
When remove first sample grid 101A on a part of hard mask layer 105 and on first sample grid 101A retain part cover firmly
Film layer；Dielectric layer 108 is ground later, removes part the second sample grid 101B and will be more than on first sample grid 101A
Under hard mask layer 105 carry out part removal.Structure shown in Fig. 4 a is formed after the completion of above-mentioned steps.
The second sample grid 101B in second gate slot is removed, and prepares one layer of high k dielectric layer 106 for the exposure of second gate slot
Surface is covered, and second gate slot is filled by deposited metal 103 completely, and is ground, as shown in Fig. 3 b-3c.?
During being ground to metal 103, due to remaining with hard mask layer at the top of first sample grid 101A, to the first sample of lower section
This grid 101A forms protective effect, and first sample grid 101A is avoided to be formed by damage during the grinding process.Such as Fig. 4 b-4d institute
Show.
After the completion of grinding, 105 He of hard mask layer being located in first grid slot can be removed by lithography and etching technique
First sample grid 101A, and fill metal and prepare metal gate in first grid slot.Likewise, in the first grid slot deposited metal it
Before, it first prepares high k dielectric layer 107 and covers the surface of first grid slot exposure.As shown in Fig. 4 e-4g.
It should be noted that do not limited the invention in above-described embodiment, it in practical applications, can be to P-
Sample grid on MOSFET region carry out thinned and prepare hard mask layer at the top of it while being applicable in, in related embodiment herein
It will not go into details.
In conclusion since present invention employs above technical schemes, by removing part sample grid and being made at the top of it
After standby one layer of hard mask layer, subsequent HKMG technique is carried out again later, when the metal to deposition is ground, hard mask layer can
The effect of protection lower section sample grid is effectively played, while also effectively preventing sample grid near zone during the grinding process and being easy
Existing recess ensure that the uniformity of lapped face, and provide foundation to promote device performance.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (10)
1. a kind of metal gate preparation method, which comprises the steps of:
Step S1, a substrate is provided, the substrate surface is covered with dielectric layer, and first grid slot and the are formed in the dielectric layer
Two grid slots are provided with first sample grid in the first grid slot, the second sample grid are provided in the second gate slot；
The height of first sample grid is less than the thickness of dielectric layer, and the height of the second sample grid is equal to the thickness of dielectric layer；
Step S2, the top that one layer of hard mask layer is covered on first sample grid and the second sample grid is prepared, and will be in first grid slot
Clearance space on first sample grid is filled completely；
Step S3, the hard mask layer on the second sample grid is removed completely, while removing one on first sample grid
Divide hard mask layer and retains part hard mask layer on first sample grid；
Step S4, the dielectric layer is ground, removal part the second sample grid simultaneously will be remaining on first sample grid
Hard mask layer carries out part removal；
Step S5, etching is to remove completely remaining second sample grid in second gate slot；
Step S6, it fills in metal to second gate slot and is ground, nationality is by the remaining hard mask layer on first sample grid
Ensure first sample grid during the grinding process from damage.
2. the method as described in claim 1, which is characterized in that the first sample grid are located at an area N-MOSFET in substrate
In dielectric layer on domain, the second sample grid are located in the dielectric layer in substrate on a region P-MOSFET.
3. the method as described in claim 1, which is characterized in that the first sample grid are located at an area P-MOSFET in substrate
In dielectric layer on domain, the second sample grid are located in the dielectric layer in substrate on a region N-MOSFET.
4. method as claimed in claim 2 or claim 3, which is characterized in that the region N-MOSFET and P-MOSFET in the substrate
It is isolated between region by fleet plough groove isolation structure.
5. the method as described in claim 1, which is characterized in that carried out using lithography and etching technique to the first sample grid
Etching removes the part first sample grid, so that the height of the first sample grid is less than the thickness of the dielectric layer.
6. the method as described in claim 1, which is characterized in that the hard mask layer is SiN.
7. the method as described in claim 1, which is characterized in that the dielectric layer is oxide layer.
8. the method as described in claim 1, which is characterized in that in step S4 and step S6, the grinding is chemical machine
Tool grinding.
9. the method as described in claim 1, which is characterized in that after removing the second sample grid, and before filling metal,
First prepare the surface that one layer of high k dielectric layer is covered on the exposure of second gate slot.
10. the method as described in claim 1, which is characterized in that the sample grid are polysilicon or amorphous carbon.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714526A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
| CN101714527A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor element |
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| US8354313B2 (en) * | 2010-04-30 | 2013-01-15 | International Business Machines Corporation | Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101714526A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for fabricating semiconductor device |
| CN101714527A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor element |
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