CN105990119A - Semiconductor device fabrication method, semiconductor device and electronic device - Google Patents
Semiconductor device fabrication method, semiconductor device and electronic device Download PDFInfo
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- CN105990119A CN105990119A CN201510086502.5A CN201510086502A CN105990119A CN 105990119 A CN105990119 A CN 105990119A CN 201510086502 A CN201510086502 A CN 201510086502A CN 105990119 A CN105990119 A CN 105990119A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000005389 semiconductor device fabrication Methods 0.000 title abstract 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000007769 metal material Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 238000009434 installation Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910004129 HfSiO Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 3
- 238000005468 ion implantation Methods 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000004567 concrete Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 239000011513 prestressed concrete Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 nitrogen ion Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device fabrication method. The method includes the following steps that: a, a semiconductor substrate is provided, a dummy gate oxide layer and a dummy gate are formed on the semiconductor substrate, and a dielectric layer is formed at two sides of the dummy gate oxide layer and the dummy gate, and the dummy gate oxide layer and the dummy gate are removed, so that a groove can be formed; a gate dielectric layer is formed at the bottom and side wall of the groove; and c, the groove is filled with a metal material, so that a metal gate can be formed, and the dielectric constant of the gate dielectric layer located at the bottom of the groove is higher than the dielectric constant of the gate dielectric layer located at the side wall of the groove. According to the semiconductor device fabrication method provided by the invention, on the one hand, the dielectric constant of the gate dielectric layer covering the side wall of the gate is small, parasitic capacitance between a drain or source and the metal gate can be decreased, and on the other hand, the dielectric constant of the gate dielectric layer located below the gate is relatively high, so that leakage current can be reduced effectively.
Description
Technical field
The present invention relates to technical field of semiconductors, make in particular to a kind of semiconductor device
Method, semiconductor device and electronic installation.
Background technology
Along with the development of semiconductor technology, in integrated circuit especially super large-scale integration
The geometry of main devices metal-oxide semiconductor fieldeffect transistor (being called for short MOSFET)
Size is constantly reducing always, and device critical dimensions has narrowed down to below the characteristic size of 0.1 μm,
Gate medium equivalent oxide thickness is the least to nanometer scale, uses silicon dioxide (SiO2) layer to make
Technique for gate dielectric has reached the limit of its physical electrical characteristic, in 65nm technique
Silicon dioxide layer in transistor has narrowed down to the thickness of 5 oxygen atoms.As spacer gates
With the insulator of lower floor, silicon dioxide layer can not further reduce, otherwise produce
Leakage current can allow transistor normally work.To this end, the solution that prior art has pointed out
It is to use metal gate and high-k (K) gate medium to substitute traditional heavily doped polysilicon
Grid and SiO2 (or SiON) gate medium.
The forming method of metal gate and high K dielectric is divided into a variety of, is broadly divided into first grid
(gate first) and post tensioned unbonded prestressed concrete (gate last), wherein post tensioned unbonded prestressed concrete is divided into again first high K (high K
And rear high K (high K last) first).The feature of front grid technique is that silicon chip is leaking/source
District's ion implanting operation and high-temperature annealing process subsequently form metal gates after completing again；
After on the other hand the feature of grid technique be silicon chip is carried out drain source ion implanting operation with
And annealing process subsequently complete before just generate metal gates.
At present, high K and post tensioned unbonded prestressed concrete technique are widely used in 32/28nm and techniques below node,
But, although use metal gate and high K dielectric to substitute traditional heavily doped polysilicon grid and SiO2
(or SiON) gate medium can solve electrical leakage problems, but it is found that and cover grid curb wall
High K dielectric can increase the parasitic capacitance between source/drain and metal gates, and then affects device
ON/OFF speed and performance.
Therefore, it is necessary to propose a kind of new manufacture method, with the problem solving above-mentioned existence.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be concrete real
Execute in mode part and further describe.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, one aspect of the present invention provides a kind of semiconductor device
Manufacture method, comprising: a: Semiconductor substrate is provided, is formed on the semiconductor substrate
Dummy gate oxide layer and dummy gate, and at described dummy gate oxide layer and dummy gate
The dielectric layer that both sides are formed, removes described dummy gate oxide layer and dummy gate to form groove；
B: form gate dielectric on described channel bottom and sidewall；C: to described trench fill gold
Belonging to material, form metal gates, wherein, the dielectric of the gate dielectric being positioned at channel bottom is normal
Number is higher than the dielectric constant of the gate dielectric being positioned at described trenched side-wall.
The manufacture method of the semiconductor device that the present invention proposes, owing to covering the grid of grid curb wall
Dielectric layer constant is relatively small, and is positioned at the gate dielectric dielectric constant phase below grid
It is to higher, so on the one hand less owing to covering the gate dielectric dielectric constant of grid curb wall,
The parasitic capacitance between source/drain and metal gates can be reduced, on the other hand, owing to being positioned at grid
Gate dielectric dielectric constant below pole is of a relatively high still can effectively reduce leakage current.
Another aspect of the present invention provides a kind of semiconductor device, comprising: Semiconductor substrate, position
The fluted dielectric layer of tool in described Semiconductor substrate, is positioned at described trenched side-wall and bottom
Gate dielectric and be positioned at the metal gates on described gate dielectric, wherein, be positioned at ditch
The dielectric constant of the gate dielectric of trench bottom is higher than the gate dielectric being positioned at described trenched side-wall
The dielectric constant of layer.
The semiconductor device that the present invention proposes is owing to covering the gate dielectric dielectric of grid curb wall
Constant is relatively small, and it is of a relatively high to be positioned at the gate dielectric dielectric constant below grid, this
Sample is on the one hand less owing to covering the gate dielectric dielectric constant of grid curb wall, can reduce source
Parasitic capacitance between/leakage and metal gates, on the other hand, owing to being positioned at the grid below grid
Pole dielectric layer constant is of a relatively high still can effectively reduce leakage current.
Further aspect of the present invention provides a kind of electronic installation, it include that the present invention provides above-mentioned half
Conductor device.
The electronic installation that the present invention proposes, owing to having above-mentioned semiconductor device, thus has class
As advantage.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Fig. 1 shows the process chart of manufacture method according to an embodiment of the present invention；
Fig. 2 A～Fig. 2 J shows that the manufacture method of an embodiment of the present invention implements each step successively
The generalized section of rapid obtained device；
Fig. 3 shows semiconductor device structure schematic diagram according to an embodiment of the present invention；
Fig. 4 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to "
Or when " being coupled to " other element or layer, its can directly on other element or layer and
Adjacent, be connected or coupled to other element or layer, or element between two parties or layer can be there is.
On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other element or layer, the most there is not element between two parties or layer.Should
Understand, although can use term first, second, third, etc. describe various element, parts,
District, floor and/or part, these elements, parts, district, floor and/or part should be by these
Term limits.These terms be used merely to distinguish an element, parts, district, floor or part with
Another element, parts, district, floor or part.Therefore, under without departing from present invention teach that,
First element discussed below, parts, district, floor or part be represented by the second element, parts,
District, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... it
Under ", " ... on ", " above " etc., here can describe for convenience and used from
And shown in figure a element or feature and other element or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operating
In the different orientation of device.Such as, if the device upset in accompanying drawing, then, it is described as
" below other element " or " under it " or " under it " element or feature will orientations
For other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
The present invention provides a kind of manufacturing method of semiconductor device, is used for forming high K gate dielectric layer
And metal gates, specifically step includes: provide Semiconductor substrate, in described Semiconductor substrate
Formed and have fluted dielectric layer；Described channel bottom and sidewall are formed gate dielectric；:
To described trench fill metal material, form metal gates, and be positioned at the grid of channel bottom
The dielectric constant of dielectric layer is higher than the dielectric constant of the gate dielectric being positioned at described trenched side-wall,
So relatively small owing to covering the gate dielectric dielectric constant of grid curb wall, and it is positioned at grid
The gate dielectric dielectric constant of lower section is of a relatively high, so on the one hand owing to covering grid curb wall
Gate dielectric dielectric constant less, the parasitism between source/drain and metal gates can be reduced
Electric capacity, on the other hand, of a relatively high owing to being positioned at the gate dielectric dielectric constant below grid
Still leakage current can be effectively reduced.
It is understood that for the ease of forming metal gates, can before forming metal gates
Form dummy gate one step ahead, just can be by the figure of dummy gate after removing dummy gate
Filler metal material forms required metal gates.Therefore, the semiconductor device that the present invention provides
The manufacture method of part, also includes the step forming and removing dummy gate, and it uses this area normal
By method, it is briefly described at this, is such as formed and remove dummy gate by following step:
Semiconductor substrate is provided；Described quasiconductor is formed dummy gate oxide layer and dummy gate；
Dielectric layer is formed in described dummy gate oxide layer and dummy gate both sides；Remove described virtual grid
Pole oxide layer and dummy gate form groove.
Further, in the manufacture method of the semiconductor device provided in the present invention, it is preferred to use
HfO2 is as high K dielectric material, and HfO2 dielectric material has simple CaF2 cubic crystal
Structure, high dielectric constant (～25), bigger energy gap (～5.8eV), higher potential barrier are high
Spend (～1.5eV), stable chemical property and have the advantageous properties such as good Lattice Matching with silicon,
And mix appropriate Al, Si or N element can have more preferable heat stability, higher crystalline substance
Change temperature, reduce boron infiltration and make mobility increase.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description,
So as the technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention is described in detail as follows,
But in addition to these describe in detail, the present invention can also have other embodiments.
Embodiment one
The making side to the semiconductor device of the present invention below in conjunction with Fig. 1 and Fig. 2 A～Fig. 2 J
Method is described in detail.
First, performing step S101, it is provided that Semiconductor substrate, described Semiconductor substrate is formed
Dielectric layer, forms dummy gate oxide layer and dummy gate in described dielectric layer, removes described
Dummy gate oxide layer and dummy gate are to form groove.As formed and remove dummy gate oxidation
Layer and dummy gate use method commonly used in the art, do not repeat them here.
As shown in Figure 2 A, it is provided that Semiconductor substrate 200, this Semiconductor substrate 200 forms tool
There is the dielectric layer 202 of groove 201.As it was previously stated, also include forming dummy gate in this step
Oxide layer and dummy gate, remove dummy gate oxide layer and the step of dummy gate, for simplifying
Describing, Fig. 2 A is for have removed gained semiconductor device after dummy gate oxide layer and dummy gate
The sectional view of part.
Semiconductor substrate 200 can be at least one in the following material being previously mentioned: silicon, germanium.
Additionally, could be formed with other device in Semiconductor substrate, such as PMOS and NMOS is brilliant
Body pipe.Could be formed with isolation structure in the semiconductor substrate, described isolation structure is shallow trench
Isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Semiconductor substrate
In can also be formed with cmos device, cmos device e.g. transistor (such as, NMOS
And/or PMOS) etc..Equally, Semiconductor substrate can also be formed conductive member, lead
Electric components can be the grid of transistor, source electrode or drain electrode, it is also possible to is to electrically connect with transistor
Metal interconnection structure, etc..
As example, in the present embodiment, Semiconductor substrate 200 is formed shallow trench isolation
(STI) structure 203, and on the sidewall of groove 201, it is formed with clearance wall 204, it is being situated between
Etching stopping layer 205 it is formed with between matter layer 202 and Semiconductor substrate 200.Wherein, medium
Layer 202 for example, silicon nitride, silicon oxide or the combination of the two, or other common used materials.
Clearance wall 204 is silicon nitride, silicon oxide or the combination of the two, and etching stopping layer 205 is nitrogen
SiClx, silicon oxide or the combination of the two.
Then, perform step S102, formed and cover described trenched side-wall, bottom and described
The gate dielectric of dielectric layer surface.
As shown in Figure 2 B, formed on groove 201 sidewall, bottom and dielectric layer 202 surface
Gate dielectric 206, gate dielectric 206 uses few hafnium HfSiO, and its forming method uses
Physical vapour deposition (PVD), chemical gaseous phase deposition or ald.
Then, perform step S103, perform Hf ion implanting to described gate dielectric.
As shown in Figure 2 C, inject Hf ion to gate dielectric 206, to improve groove 201
Hf content in the dielectric material HfSiO on bottom and dielectric layer 202 surface.
As example, in the present embodiment, the implantation dosage of Hf ion is 1E16～1E17/cm2,
Implantation Energy is 1kev～10kev.
Then, perform step S104, perform Hf ion implanting to described gate dielectric.
As shown in Figure 2 D, to gate dielectric 206 injecting nitrogen ion, to improve groove 201
Nitrogen content in the dielectric material HfSiO on bottom and dielectric layer 202 surface, makes channel bottom 201
It is changed into HfSiON with the gate dielectric material on dielectric layer 202 surface.
As example, in the present embodiment, the implantation dosage of Nitrogen ion is 1E16～1E17/cm2,
Implantation Energy is 1kev～10kev.
Then, perform step S105, formed at described channel bottom and dielectric layer surface and cover
Layer.
As shown in Figure 2 E, on the gate dielectric 206 bottom groove 201 and medium
Layer 202 areal gate dielectric layer 206 form cover layer 207.Cover layer 207 can pass through physics
Vapour deposition (PVD), chemical gaseous phase deposition (CVD), ald (ALD) are formed.
As example, in the present embodiment, cover layer 207 uses TiN material, and it passes through thing
Physical vapor deposition is formed.
Then, perform step S106, described trenched side-wall, described cover layer are formed non-
Crystal silicon layer.
As shown in Figure 2 F, groove 201 sidewall and described cover layer form amorphous silicon layer 208.
As example, in the present embodiment, amorphous silicon layer 208 uses Atomic layer deposition method to be formed,
Thickness is 5nm～10nm.
Then, perform step S107, remove described channel bottom and described cover surface
Amorphous silicon layer, retains the amorphous silicon layer on described trenched side-wall.
As shown in Figure 2 G, remove bottom groove 201 and the amorphous silicon layer on cover layer 207 surface,
Retaining the amorphous silicon layer on groove 201 sidewall, concrete minimizing technology can use without pattern etching side
Method (blanket etch), for common method, does not repeats them here.
Then, perform step S108, perform annealing process, with on described institute trenched side-wall
Gate dielectric and amorphous silicon layer reaction.
As illustrated in figure 2h, perform annealing process, make the gate dielectric 206 on groove 201 sidewall
React with amorphous silicon layer 208, make HfSiO be changed into rich SiHfSiO.In the present embodiment,
Rapid thermal anneal process can be used, specifically, at N2Rapid thermal annealing under environment, annealing temperature
Being 400～600 DEG C, the time is 5s～60s.
Then, perform step S109, to described trench fill metal material, form metal gate
Pole.
As shown in figure 2i, to groove 201 filler metal material, form metal gates.
It is understandable that to groove 201 filler metal material, when forming metal gates,
Inevitably forming metal material layer on dielectric layer surface, it can be filled at metal material
After remove the gate dielectric above dielectric layer 202 by chemical-mechanical planarization (CMP)
Layer, cover layer and metal material layer, as shown in fig. 2j.
Embodiment two
The present invention also provides for the semiconductor device that a kind of method used described in embodiment one makes
Part, Semiconductor substrate 200, the dielectric layer 202 with groove 210 in Semiconductor substrate 200,
It is positioned at the gate dielectric 206A of groove 202 sidewall and is positioned at the gate dielectric of channel bottom
206B, and the metal gates 210 being positioned on the gate dielectric 206B of channel bottom, its
In, the dielectric constant of the dielectric layer of gate dielectric 206B is higher than gate dielectric 206A's
Dielectric constant.
In the present embodiment, gate dielectric 206A is HfSiO, gate dielectric 206B
For HfSiON.
In the present embodiment, the gate dielectric 206A on groove 201 sidewall and dielectric layer
Clearance wall 204 it is formed with between 202.
In the present embodiment, it is formed between metal gates 210 and gate dielectric 206B
Cover layer 207, and cover layer 207 is the TiN layer formed by physical vapour deposition (PVD).
Embodiment three
The present invention additionally also provides for a kind of electronic installation, and it includes aforesaid semiconductor device.
Semiconductor device owing to including uses wafer-level packaging, thus has what this technique was brought
Advantage, and owing to using said method to be packaged, yields is higher, cost relative reduction,
Therefore this electronic installation has above-mentioned advantage equally.
This electronic installation, can be mobile phone, panel computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment, it is also possible to be that there is above-mentioned quasiconductor
The intermediate products of device, such as: there is the cell phone mainboard etc. of this integrated circuit.In this embodiment
Example is carried out, as shown in Figure 4 as a example by PDA.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention,
Within these variants and modifications all fall within scope of the present invention.The protection of the present invention
Scope is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. the manufacture method of a semiconductor device, it is characterised in that comprise the steps:
A: Semiconductor substrate is provided, forms dummy gate oxide layer on the semiconductor substrate
And dummy gate, and the medium formed in described dummy gate oxide layer and dummy gate both sides
Layer, removes described dummy gate oxide layer and dummy gate to form groove；
B: form gate dielectric on described channel bottom and sidewall；
C: to described trench fill metal material, forms metal gates,
Wherein, the dielectric constant of gate dielectric of channel bottom it is positioned at higher than being positioned at described groove
The dielectric constant of the gate dielectric of sidewall.
Manufacture method the most according to claim 1, it is characterised in that described step b
Including:
Formed and cover described trenched side-wall, bottom and the gate dielectric of described dielectric layer surface,
Described gate dielectric is few hafnium HfSiO；
Hf ion implanting is performed to described gate dielectric；
Perform N~+ implantation to described gate dielectric, make described channel bottom and described medium
The gate dielectric on layer surface is changed into HfSiON；
Cover layer is formed at described channel bottom and dielectric layer surface；
The amorphous silicon layer formed on described trenched side-wall and described cover layer；
Remove described channel bottom and the non-crystalline silicon of described cover surface, retain described channel side
Amorphous silicon layer on wall；
Perform annealing process, anti-with the gate dielectric on described institute trenched side-wall and amorphous silicon layer
Should, make the gate dielectric on described trenched side-wall be changed into Silicon-rich HfSiO.
Manufacture method the most according to claim 2, it is characterised in that described Hf ion
Implantation dosage be 1E16～1E17/cm2, Implantation Energy is 1kev～10kev.
Manufacture method the most according to claim 2, it is characterised in that described Nitrogen ion
Implantation dosage be 1E16～1E17/cm2, Implantation Energy is 1kev～10kev.
Manufacture method the most according to claim 2, it is characterised in that described cover layer
For the TiN layer formed by physical vapour deposition (PVD).
Manufacture method the most according to claim 2, it is characterised in that described non-crystalline silicon
Layer is formed for ald.
Manufacture method the most according to claim 2, it is characterised in that described non-crystalline silicon
Layer thickness is 5nm～10nm.
Manufacture method the most according to claim 1, it is characterised in that described channel side
Clearance wall it is formed with on wall.
Manufacture method the most according to claim 1, it is characterised in that at described medium
Etching stopping layer it is also formed with below Ceng.
10. a semiconductor device, it is characterised in that including: Semiconductor substrate, is positioned at institute
State the fluted dielectric layer of the tool in Semiconductor substrate, be positioned at the grid of described trenched side-wall and bottom
Pole dielectric layer and be positioned at the metal gates on described gate dielectric,
Wherein, the dielectric constant of gate dielectric of channel bottom it is positioned at higher than being positioned at described groove
The dielectric constant of the gate dielectric of sidewall.
11. semiconductor device according to claim 10, it is characterised in that be positioned at institute
Stating the gate dielectric Silicon-rich HfSiO of trenched side-wall, the gate dielectric being positioned at channel bottom is
HfSiON。
12. 1 kinds of electronic installations, it is characterised in that include as described in claim 10 or 11
Semiconductor device.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023102951A1 (en) * | 2021-12-06 | 2023-06-15 | 北京超弦存储器研究院 | Vertical mosfet device and manufacturing method therefor and application thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7148099B2 (en) * | 2004-06-24 | 2006-12-12 | Intel Corporation | Reducing the dielectric constant of a portion of a gate dielectric |
| US20090065876A1 (en) * | 2007-09-10 | 2009-03-12 | Leland Chang | Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same |
| CN102386083A (en) * | 2010-09-02 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer |
-
2015
- 2015-02-16 CN CN201510086502.5A patent/CN105990119B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7148099B2 (en) * | 2004-06-24 | 2006-12-12 | Intel Corporation | Reducing the dielectric constant of a portion of a gate dielectric |
| US20090065876A1 (en) * | 2007-09-10 | 2009-03-12 | Leland Chang | Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same |
| CN102386083A (en) * | 2010-09-02 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023102951A1 (en) * | 2021-12-06 | 2023-06-15 | 北京超弦存储器研究院 | Vertical mosfet device and manufacturing method therefor and application thereof |
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