CN102386083A - MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer - Google Patents
MOS (metal oxide semiconductor) transistor and manufacturing method of MOS transistor gate dielectric layer Download PDFInfo
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- CN102386083A CN102386083A CN2010102751914A CN201010275191A CN102386083A CN 102386083 A CN102386083 A CN 102386083A CN 2010102751914 A CN2010102751914 A CN 2010102751914A CN 201010275191 A CN201010275191 A CN 201010275191A CN 102386083 A CN102386083 A CN 102386083A
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Abstract
The invention relates to a manufacturing method of an MOS (metal oxide semiconductor) transistor gate dielectric layer. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein a false gate dielectric layer and a dielectric protective layer are formed on the semiconductor substrate, and a gate opening is formed in the dielectric protective layer and leads the false gate dielectric layer to be exposed; forming a sacrificial layer on the dielectric protective layer and in the gate opening, wherein the sacrificial layer covers the gate opening in a shape-maintaining manner; etching the sacrificial layer in an anisotropic manner, and only retaining the sacrificial layer on the vertical side wall of the gate opening; forming a high-K dielectric material on the dielectric protective layer and in the gate opening, wherein the high-K dielectric material covers the gate opening in a shape-maintaining manner; and carrying out annealing treatment on the semiconductor substrate and leading the sacrificial layer on the vertical side wall of the gate opening and the high-K dielectric material to react to form a mixed dielectric layer which has a dielectric constant less than that of the high-K dielectric material. In the manufacturing method, a high-K gate dielectric layer at the bottom part of the metal gate is not damaged and simultaneously the gate parasitic capacitance is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to the manufacture method of MOS transistor and gate dielectric layer thereof.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more littler.Constantly dwindle under the situation in the MOS transistor characteristic size, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, (High K Metal Gate, gate stack structure HKMG) is introduced in the MOS transistor for high K gate dielectric layer and metal gates.
For the gate metal material of avoiding metal gates to other effect on structure of transistor, the gate stack structure of said metal gates and high K gate dielectric layer adopts grid to substitute (replacement gate) technology usually and makes.In this technology, before source-drain area injects, at first form the dummy grid that constitutes by polysilicon in gate electrode position to be formed, said dummy grid is used for autoregistration and forms PROCESS FOR TREATMENT such as source-drain area.And after forming source-drain area, can remove said dummy grid and form gate openings in the position of dummy grid, afterwards, in said gate openings, fill high K gate dielectric layer and metal gates more successively.Because metal gates is made after source-drain area injects completion again, this makes that the quantity of subsequent technique is able to reduce, and has avoided the gate metal material to be inappropriate for the problem of carrying out high-temperature process.
Yet, adopt above-mentioned grid alternative techniques to make MOS transistor and still exist challenge.Along with further dwindling of grid length, this problem is more serious.In the gate stack structure that this technology forms, be coated with high K gate dielectric layer on the vertical sidewall of said gate openings equally, this causes the parasitic capacitance between source-drain area and metal gates to increase.And the unnecessary parasitic capacitance increase of metal gates can influence devices switch speed.
For solving the bigger problem of said metal gates parasitic capacitance, U.S. Pat 6864145 discloses a kind of through reduce the method for said gate dielectric layer dielectric constant at the gate dielectric layer injection silicon ion of gate openings vertical sidewall.Yet said silicon ion not only is infused in the high K gate dielectric layer of gate openings vertical sidewall, also can be injected into simultaneously in the high K gate dielectric layer of gate openings bottom, and this can destroy the dielectric property of the high K gate dielectric layer in gate openings bottom, and then influences device performance.7148099 of U.S. Pat disclose the method for another kind of reduction gate dielectric layer dielectric constant.In the method; Need in gate openings, to fill up in advance polysilicon or gate metal material; Inject silicon ion with certain angle more afterwards, owing to have polysilicon or gate metal material to do to stop in the gate openings, the dielectric property of gate openings bottom gate dielectric layer do not receive to inject to be influenced.Yet; Said polysilicon or gate metal material stop also that simultaneously silicon ion is injected in the high K gate dielectric layer of gate openings vertical sidewall; Make the high K gate dielectric layer of this position only have the dielectric constant of subregion to be minimized, the grid parasitic capacitance still is difficult to effectively reduce.
Summary of the invention
The problem that the present invention solves provides the manufacture method of a kind of MOS transistor and gate dielectric layer thereof, when not destroying the high K gate dielectric layer in metal gates bottom, has reduced the parasitic capacitance of metal gates, has improved device performance.
For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor gate dielectric layer, comprising:
Semiconductor substrate is provided, is formed with pseudo-gate dielectric layer and dielectric protection layer on the said Semiconductor substrate, be formed with gate openings in the said dielectric protection layer, said gate openings makes pseudo-gate dielectric layer expose;
On said dielectric protection layer with in the gate openings, form sacrifice layer, said sacrifice layer conformal cover gate opening;
The said sacrifice layer of anisotropic etching only keeps the sacrifice layer on the gate openings vertical sidewall;
On said dielectric protection layer with in the gate openings, form high-k dielectric material, said high-k dielectric material conformal covers said gate openings;
Said Semiconductor substrate is carried out annealing in process, make that the sacrifice layer on the gate openings vertical sidewall mixes dielectric layer with high-k dielectric material reaction formation, said mixing dielectric layer has the dielectric constant less than high-k dielectric material.
Compared with prior art, the present invention has the following advantages:
1. utilize the chemical reaction between sacrifice layer and high-k dielectric material; Has mixing dielectric layer in the formation of the both sides of metal gates than low-k; The shape of said sacrifice layer can accurately be controlled, thereby has avoided the ion injection mode to form the unsteadiness of mixing dielectric layer;
2. the mixing dielectric layer of said low-k effectively reduces the grid parasitic capacitance of MOS transistor.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of MOS transistor gate dielectric layer of the present invention.
Fig. 2 to Fig. 7 is the generalized section of each production phase of manufacture method of MOS transistor gate dielectric layer of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part, in the high K gate dielectric layer manufacture method of prior art,, need in said gate dielectric layer, inject silicon ion in order to reduce the dielectric constant of gate openings vertical sidewall gate dielectric layer.Yet the injection of said silicon ion may reduce the dielectric property of gate openings bottom gate dielectric layer, or owing to stopping of gate openings packing material makes the gate openings vertical sidewall only have the dielectric constant of the high K gate dielectric layer of part to be lowered.
To the problems referred to above, inventor of the present invention provides a kind of manufacture method of MOS transistor gate dielectric layer.In the method; Before gate openings is filled high-k dielectric material, need on the vertical sidewall of gate openings, form sacrifice layer, and after high-k dielectric material is filled in conformal; Said Semiconductor substrate is carried out annealing in process; Said annealing in process makes sacrifice layer and high-k dielectric material react, and forms to have the mixing dielectric layer than low-k, thereby has effectively reduced the parasitic capacitance of metal gates both sides.
With reference to figure 1, show the flow process of the manufacture method of MOS transistor gate dielectric layer of the present invention, comprising:
Execution in step S102 provides Semiconductor substrate, is formed with pseudo-gate dielectric layer and dielectric protection layer on the said Semiconductor substrate, is formed with gate openings in the said dielectric protection layer, and said gate openings makes pseudo-gate dielectric layer expose;
Execution in step S104 forms sacrifice layer on said dielectric protection layer with in the gate openings, said sacrifice layer conformal cover gate opening;
Execution in step S106, the said sacrifice layer of anisotropic etching only keeps the sacrifice layer on the gate openings vertical sidewall;
Execution in step S108 forms high-k dielectric material on said dielectric protection layer with in the gate openings, said high-k dielectric material conformal covers said gate openings;
Execution in step S110 carries out annealing in process to said Semiconductor substrate, makes that the sacrifice layer on the gate openings vertical sidewall mixes dielectric layer with high-k dielectric material reaction formation, and said mixing dielectric layer has the dielectric constant less than high-k dielectric material.
In specific embodiment, said sacrifice layer can adopt semi-conducting material or carbon such as silicon, germanium, SiGe, and said high-k dielectric material comprises HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2Or LaAlO etc., said mixing dielectric layer is formed by sacrifice layer and high-k dielectric material reaction, and is corresponding, and said mixing dielectric layer comprises Hf
xSi
yO
z, Hf
xSi
yO
zH, Hf
uTi
xSi
yO
z, Hf
uTa
xSi
yO
z, Hf
uZr
xSi
yO
z, Si
xAl
yO
z, Hf
xGe
yO
zOr Hf
uSi
xGe
yO
zDeng.With said sacrifice layer is that Si, high-k dielectric material are HfO
2Be example, said Si and HfO
2The reaction back generates mixes dielectric layer Hf
xSi
yO
z, and said Hf
xSi
yO
zDielectric constant significantly be lower than HfO
2Dielectric constant.
After above-mentioned steps was accomplished, the dielectric layer in the said gate openings comprised: the high-k dielectric material (being high K gate dielectric layer) of gate openings bottom and the mixing dielectric layer on the gate openings vertical sidewall.Afterwards, also need continue in said gate openings, to fill the gate metal material, to form metal gates.
Next, in conjunction with concrete embodiment, the manufacture method of MOS transistor gate dielectric layer of the present invention is further explained.
Fig. 2 to Fig. 7 is the generalized section of each production phase of manufacture method of MOS transistor gate dielectric layer of the present invention.
As shown in Figure 2, Semiconductor substrate 201 is provided, be formed with pseudo-gate dielectric layer 202 and dielectric protection layer 203 on the said Semiconductor substrate 201 successively, said pseudo-gate dielectric layer 202 covers Semiconductor substrate 201 surfaces.Also be formed with gate openings 207 in the said dielectric protection layer 203, said gate openings 207 makes pseudo-gate dielectric layer 202 surfaces of its bottom expose.Optional, also being formed with clearance wall 205 in the dielectric protection layer 203 of said gate openings 207 both sides, said clearance wall 205 can adopt silicon nitride.
As shown in Figure 3, on said dielectric protection layer 203 with in the gate openings 207, form sacrifice layer 209, said sacrifice layer 209 conformals cover said gate openings 207.Said conformal covers and is meant that the thickness of sacrifice layer 209 is less for the degree of depth and width of gate openings 207, can not fill completely said gate openings 207, makes said gate openings 207 still keep and does not form the preceding similar shape of film.
In specific embodiment, adopt the mode of chemical vapor deposition to form said sacrifice layer 209, said sacrifice layer 209 comprises: semi-conducting material or carbon such as silicon, germanium, SiGe, its thickness is less than or equal to 20 dusts.Preferably, be mixed with protium or fluorine element in the sacrifice layer 209 that adopts silicon to form, the doping content of said protium is 5% to 30%, and the doping content of said fluorine element is 5% to 15%.The protium of said doping or fluorine element can reduce subsequent anneal handle in the reaction difficulty of silicon and high-k dielectric material.
As shown in Figure 4, the said sacrifice layer 209 of anisotropic etching removes on the dielectric protection layer 203 sacrifice layer 209 with gate openings 207 bottoms, only keeps the sacrifice layer 209 on gate openings 207 vertical sidewalls.Said residual sacrifice layer 209 can also strengthen the metal electrode of follow-up formation and the distance between source-drain area, thereby has reduced the grid parasitic capacitance.In addition, the shape of said sacrifice layer 209 can accurately be controlled, thereby has avoided the ion injection mode to form the unsteadiness of dielectric layer with low dielectric constant technology.
After said sacrifice layer 209 anisotropic etchings, the pseudo-gate dielectric layer 202 of gate openings 207 bottoms exposes.Afterwards, remove the pseudo-gate dielectric layer 202 that expose said gate openings 207 bottoms, until exposing said Semiconductor substrate 201 surfaces.In specific embodiment, said pseudo-gate dielectric layer 202 is a silica, and adopting concentration is that 1% hydrofluoric acid solution (DHF) removes said pseudo-gate dielectric layer 202, and the reaction time is 3 to 5 minutes.
According to the difference of specific embodiment, can also select not remove said pseudo-gate dielectric layer 202 and directly carry out subsequent technique.
As shown in Figure 5, on said dielectric protection layer 203 with in the gate openings 207, form high-k dielectric material 211, said high-k dielectric material 211 conformal cover gate openings 207.Said high-k dielectric material comprises HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2Perhaps LaAlO.In specific embodiment, the thickness of said high-k dielectric material is less than or equal to 60 dusts.
As shown in Figure 6, said Semiconductor substrate 201 is carried out annealing in process, sacrifice layer on said gate openings 207 vertical sidewalls and high-k dielectric material 211 reactions form and mix dielectric layer 213, and said mixing dielectric layer 213 is connected with clearance wall 205.Said mixing dielectric layer 213 has the dielectric constant less than high-k dielectric material 211.Adopt semi-conducting material or carbon such as silicon, germanium, SiGe at said sacrifice layer, and said high-k dielectric material adopts HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2Or under the situation of LaAlO, said mixing dielectric layer 213 is formed by sacrifice layer and high-k dielectric material reaction, for example can be Hf
xSi
yO
z, Hf
xSi
yO
zH, Hf
uTi
xSi
yO
z, Hf
uTa
xSi
yO
z, Hf
uZr
xSi
yO
z, Si
xAl
yO
z, Hf
xGe
yO
zOr Hf
uSi
xGe
yO
zDeng.The dielectric constant of the material of the mixing dielectric layer of more than enumerating 213 is all less than the high-k dielectric material of correspondence.
In specific embodiment, said annealing in process adopts short annealing to handle, and reaction temperature is 650 to 850 degrees centigrade, and the reaction time is 1 to 3 minute, and reaction atmosphere is a nitrogen.
Because said sacrifice layer only residues on the vertical sidewall of gate openings 207; When said annealing in process; The high-k dielectric material 211 of gate openings 207 bottoms can't change the mixing dielectric layer 213 of low-k into, has also just avoided the decline of the high K gate dielectric layer of the MOS transistor dielectric property of employing the present invention making.
As shown in Figure 7, after forming said mixing dielectric layer 213, continue in said gate openings, to fill up the gate metal material.Afterwards, the said gate metal material of planarization only keeps the gate metal material in the gate openings, and the gate metal material of said reservation promptly constitutes metal gates 215.
In specific embodiment, said gate metal material comprises: Ti, Co, Ni, Al or W, or one or more alloy or metal silicide among the Ti, Co, Ni, Al, W.
In various embodiment, before forming said gate metal material, can also in said gate openings, conformal cover the workfunction metal material, said workfunction metal material is used to regulate the threshold voltage of MOS transistor.Said workfunction metal material includes but not limited to TiN, TiAlN, TaN, TaAlN or TaC.
So far; The grid structure that comprises high K gate dielectric layer and metal gates that adopts the present invention to make completes; Said metal gates is positioned on the Semiconductor substrate; Be formed with high K gate dielectric layer between the bottom of metal gates and Semiconductor substrate, and said metal gates both sides are formed with the mixing dielectric layer with low-k, and said mixing dielectric layer is connected with clearance wall and metal gates respectively.Said mixing dielectric layer has the dielectric constant less than high K gate dielectric layer, thereby has reduced the grid parasitic capacitance.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (20)
1. the manufacture method of a MOS transistor gate dielectric layer is characterized in that, comprising:
Semiconductor substrate is provided, is formed with pseudo-gate dielectric layer and dielectric protection layer on the said Semiconductor substrate, be formed with gate openings in the said dielectric protection layer, said gate openings makes pseudo-gate dielectric layer expose;
On said dielectric protection layer with in the gate openings, form sacrifice layer, said sacrifice layer conformal cover gate opening;
The said sacrifice layer of anisotropic etching only keeps the sacrifice layer on the gate openings vertical sidewall;
On said dielectric protection layer with in the gate openings, form high-k dielectric material, said high-k dielectric material conformal covers said gate openings;
Said Semiconductor substrate is carried out annealing in process, make that the sacrifice layer on the gate openings vertical sidewall mixes dielectric layer with high-k dielectric material reaction formation, said mixing dielectric layer has the dielectric constant less than high-k dielectric material.
2. manufacture method as claimed in claim 1 is characterized in that said sacrifice layer comprises silicon, germanium, SiGe or carbon.
3. manufacture method as claimed in claim 2 is characterized in that, said sacrifice layer is a silicon, and the content of protium is 5% to 30% in the said sacrifice layer.
4. manufacture method as claimed in claim 2 is characterized in that, said sacrifice layer is a silicon, and the content of fluorine element is 5% to 15% in the said sacrifice layer.
5. manufacture method as claimed in claim 2 is characterized in that, adopts the mode of chemical vapor deposition to form said sacrifice layer.
6. manufacture method as claimed in claim 2 is characterized in that the thickness of said sacrifice layer is less than or equal to 20 dusts.
7. manufacture method as claimed in claim 1 is characterized in that said high-k dielectric material comprises HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2Or LaAlO.
8. manufacture method as claimed in claim 7 is characterized in that the thickness of said high-k dielectric material is less than or equal to 60 dusts.
9. manufacture method as claimed in claim 2 is characterized in that said high-k dielectric material comprises HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2Or LaAlO.
10. manufacture method as claimed in claim 9 is characterized in that the thickness of said high-k dielectric material is less than or equal to 60 dusts.
11. manufacture method as claimed in claim 9 is characterized in that, said mixing dielectric layer comprises Hf
xSi
yO
z, Hf
xSi
yO
zH, Hf
uTi
xSi
yO
z, Hf
uTa
xSi
yO
z, Hf
uZr
xSi
yO
z, Si
xAl
yO
z, Hf
xGe
yO
zOr Hf
uSi
xGe
yO
z
12. manufacture method as claimed in claim 1; It is characterized in that adopt short annealing to handle said Semiconductor substrate is carried out annealing in process, the reaction condition that said short annealing is handled is: reaction temperature is 650 to 850 degrees centigrade; Reaction time is 1 to 3 minute, and reaction atmosphere is a nitrogen.
13. manufacture method as claimed in claim 1 is characterized in that, on said dielectric protection layer with in the gate openings, forms before the high-k dielectric material, also comprises: remove the pseudo-gate dielectric layer of gate openings bottom and expose semiconductor substrate surface.
14. manufacture method as claimed in claim 1 is characterized in that, said pseudo-gate dielectric layer is a silica; Said manufacture method also comprises: adopting concentration is that 1% hydrofluoric acid solution removes said pseudo-gate dielectric layer, and the reaction time is 3 to 5 minutes.
15. manufacture method as claimed in claim 1 is characterized in that, also comprises: before forming sacrifice layer, in the dielectric protection layer of said gate openings both sides, form clearance wall, said clearance wall has the dielectric constant less than high-k dielectric material.
16. manufacture method as claimed in claim 15 is characterized in that, said clearance wall adopts silicon nitride.
17. the manufacture method of an application rights requirement 1 forms the method for MOS transistor, wherein, after said Semiconductor substrate is carried out annealing in process, also comprises:
In said gate openings, fill up the gate metal material;
The said gate metal material of planarization keeps the gate metal material in the gate openings.
18. the method for formation MOS transistor as claimed in claim 17, wherein, said gate metal material comprises Ti, Co, Ni, Al, W and alloy thereof or metal silicide.
19. the method for formation MOS transistor as claimed in claim 17 wherein, before forming said gate metal material, covers the workfunction metal material in said gate openings conformal.
20. the method for formation MOS transistor as claimed in claim 19, wherein, said workfunction metal material comprises TiN, TiAlN, TaN, TaAlN or TaC.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839813A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and method for forming same |
| CN105990119A (en) * | 2015-02-16 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device fabrication method, semiconductor device and electronic device |
| CN106816413A (en) * | 2015-11-27 | 2017-06-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN110034022A (en) * | 2018-01-12 | 2019-07-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790742A (en) * | 2004-11-02 | 2006-06-21 | 国际商业机器公司 | Damascene gate field effect transistor with an internal spacer structure |
| CN1846313A (en) * | 2003-09-09 | 2006-10-11 | 国际商业机器公司 | Structure and method for metal replacement gate of high performance device |
| CN101253602A (en) * | 2005-08-30 | 2008-08-27 | 英特尔公司 | Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer |
-
2010
- 2010-09-02 CN CN 201010275191 patent/CN102386083B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1846313A (en) * | 2003-09-09 | 2006-10-11 | 国际商业机器公司 | Structure and method for metal replacement gate of high performance device |
| CN1790742A (en) * | 2004-11-02 | 2006-06-21 | 国际商业机器公司 | Damascene gate field effect transistor with an internal spacer structure |
| CN101253602A (en) * | 2005-08-30 | 2008-08-27 | 英特尔公司 | Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839813A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and method for forming same |
| CN105990119A (en) * | 2015-02-16 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device fabrication method, semiconductor device and electronic device |
| CN105990119B (en) * | 2015-02-16 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor devices and electronic device |
| CN106816413A (en) * | 2015-11-27 | 2017-06-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN106816413B (en) * | 2015-11-27 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110034022A (en) * | 2018-01-12 | 2019-07-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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