CN105958996B - A kind of eight input look-up table configurations of non-all standing - Google Patents
A kind of eight input look-up table configurations of non-all standing Download PDFInfo
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
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- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
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Abstract
The present invention relates to the eight of a kind of non-all standing to input look-up table configuration, which includes 25 basic logic units, contains 2 LUT4,4 LUT3 and 19 alternative MUX；10 signal ports, A, B, C, D, E0, F0, E1, F1 and 2 signal output ports Y1, Y2 containing 8 signal input ports；5 are R0, R1, R2, R3 and R4 for controlling the storage unit of six LUT and two minor feature LUT pattern switching of input, by different configurations, the combined LUT function of the different inputs of realization.The present invention can fast implement vanning when being switched to six input LUT modes, reduce software runing time；When being switched to two minor feature LUT modes, sharing for input signal can be reduced, the utilization rate and flexibility ratio of LUT can be effectively improved, reduces software runing time.
Description
Technical field
The present invention relates to a kind of look-up table configuration, eight input look-up table configurations of especially a kind of non-all standing, belonging to can
The technical field of programmed logic device.
Background technique
Programmable logic device (PLD) is capable of providing the customized IC design of user, facilitates the design of user
Flexibility ratio shortens the chip R & D design period, has widened programmable logic device military such as aerospace, civilian such as consumption
The application range of the every field such as electronics.
Programmable logic device is mainly by the basic logics list such as logic array block (LAB) or configurable logic block (CLB)
Member is constituted, these logic units generally comprise the units such as look-up table (Look-up Table, abbreviation LUT), carry chain, register.
Because the performance of look-up table LUT affects the performance of entire chip, emphasis is needed to consider the area of single LUT
With the factors such as utilization rate.In Field Programmable Logic Array (FPGA) design of current industry mainstream, it is defeated that some products are based on four
Enter LUT structure, the product also having is based on six input LUT structures, such as the Virtex series of Xilinx.
One typical look-up table LUT circuitry can be realized a multi input to the power function singly exported, function representation
Relationship is determined by the content (" 0 " or " 1 ") for configuring LUT storage unit.Look-up table LUT is equivalent to one and has coupled many storages
The tree structure of unit, this tree structure are made of some alternative multiplexers (MUX).The first order of look-up table tree is single
2:1MUX, behind every level-one MUX quantity it is incremented by successively, be all twice of previous stage, afterbody MUX is coupled to storage unit
In.The control terminal of each 2:1MUX is to look for the logic input of table LUT.Realize that the LUT (LUTn) of n input needs 2n
A storage unit and (2n- 1) a MUX, and realize the LUT (LUT (n+1)) of n+1 input and then need 2n+1A storage unit and
(2n+1- 1) a MUX, it can be seen that the resource for realizing a LUT (n+1) needs is about twice of a LUTn.
Using the LUT of this common thinking design, area can increasing and exponentially increase with logic input terminal mouth,
Chip cost is of a high price.In order to overcome this disadvantage, in many practical applications, can not influence to realize function performance
Under the premise of, the quantity of storage unit and MUX is reduced by designing the LUT resource that can be combined, to save LUT area.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the existing defects, provides a kind of eight input look-up tables of non-all standing
Structure, by increasing the input of 2 road look-up tables, can reduce sharing for input signal, energy when realizing two minor feature LUT
The utilization rate of LUT is enough effectively improved, while increasing the flexibility ratio of LUT；This structure emphatically realize minor feature LUT, rather than compared with
Big LUT (such as seven inputs or eight input LUT) logic.
In order to solve the above-mentioned technical problems, the present invention provides the following technical solutions:
A kind of eight input look-up table configurations of non-all standing of the present invention, which includes 25 basic logic lists
Member contains 2 LUT4,4 LUT3 and 19 alternative MUX；10 signal ports contain 8 signal input ports A, B, C, D, E0,
F0, E1, F1 and 2 signal output ports Y1, Y2；5 for controlling six LUT and two minor feature LUT pattern switching of input
Storage unit, be R0, R1, R2, R3 and R4, by different configurations, realize the combined LUT function of different inputs.
Further, 2 LUT4,4 LUT3 are upper and lower two groups mutually isostructural LUT4, LUT3, LUT3 unit combinations.
Further, 19 alternative MUX, including 7 for pattern switching alternative MUX and 12 for realizing altogether
With the alternative MUX of look-up table logic.
Further, A, B, C, D, E0, F0, E1, F1 and 2 signal output ports Y1, Y2 of 8 signal input ports,
The middle port A and B input signal is respectively the shared address line of two groups of LUT4, LUT3, LUT3；C port input signal is above one
Group LUT4, LUT3, LUT3 shared address line, while by alternative MUX selection control, as following set LUT4, LUT3,
The shared address line of LUT3；The port D input signal is the shared address line of following set LUT4, LUT3, LUT3, while passing through two
Select MUX selection control, the shared address line as one group of LUT4, LUT3, LUT3 above；E0 and e1 port input signal difference
It is controlled and is gated by alternative MUX, as the shared address line of two groups of LUT4, LUT3, LUT3 in different modes；The end F0 and F1
Mouth input signal is respectively two independent address lines of look-up table configuration；The port Y1 and Y2 is respectively look-up table configuration both of which
Common output end mouth.
Further, 5 are used to control six storage units for inputting LUT and two minor feature LUT pattern switching, wherein
Storage unit R0 control six input LUT and two minor feature LUT pattern switching, storage unit R1, R2, R3 and R4 be two compared with
The combined LUT function of different inputs is controlled under small function LUT mode.
Further, six input LUT mode is as R0=0, and each MUX controls gating A, B, C, E0, F0, E1 respectively
Port input signal and VCC signal, the port D and F1 input signal are not gated on and invalid, realization LUT5 and LUT6 function.
Further, two minor feature LUT modes, be as R0=1, each MUX gate respectively storage unit R1,
R2, R3, R4 are as control signal, according to the configuration of different input LUT, 8 A, B, C, D, E0, F0, E1, the port F1 input signal
As effective input signal, the port Y1 and Y2 is respectively the output port of the LUT under different configurations, realizes LUT2, LUT3, LUT4
With LUT5 various combination function.
Further, it by different configurations, realizes the combined LUT function of different inputs, is when configuration inputs LUT six
When mode, realizes a LUT6 and realize a LUT5；When configuring in two minor feature LUT modes, a LUT3 is realized
With a LUT2, two LUT3 are realized, realize LUT4 and LUT3, realize two LUT4, realize LUT5 and one
A LUT2 realizes LUT5 and LUT3, realizes LUT5 and LUT4, realizes two LUT5.
Beneficial effects of the present invention: the characteristics of Integrated Development Environment can be according to user logic, it is automatic to realize six input LUT
With two minor feature LUT pattern switchings.When LUT input is greater than five, using six input LUT modes, dress can be fast implemented
Case reduces software runing time；When LUT input is less than or equal to five, using two minor feature LUT modes, LUT can be improved
Utilization rate and flexibility ratio, increase the efficiency of LUT.The look-up table configuration improves the utilization rate of LUT, while accelerating software
Vanning.
Detailed description of the invention
Fig. 1 a is two input LUT structure schematic diagrames of look-up table bottom floor units of the present invention；
Fig. 1 b is three input LUT structure schematic diagrames of look-up table bottom floor units of the present invention；
Fig. 1 c is four input LUT structure schematic diagrames of look-up table bottom floor units of the present invention；
Fig. 1 d is five input LUT structure schematic diagrames of look-up table bottom floor units of the present invention；
Fig. 2 is that the present invention six inputs LUT structure schematic diagram；
Fig. 3 is that the present invention six inputs LUT structure equivalent diagram；
Fig. 4 is two minor feature LUT structure schematic diagrames of the invention；
Fig. 5 is a kind of eight input look-up table configuration schematic diagrames of non-all standing of the present invention.
Specific embodiment
Embodiment cited by the present invention, is merely used to help understand the present invention, should not be construed as protecting model to the present invention
The restriction enclosed for those skilled in the art without departing from the inventive concept of the premise, can also be right
The present invention makes improvements and modifications, these improvement and modification are also fallen into the range of the claims in the present invention protection.
With reference to the accompanying drawing, specific embodiments of the present invention will be described in detail.
Fig. 1 a show two input LUT, occupies 4 storage units and 3 alternative MUX resources, functional relation Y
(A, B)；Fig. 1 b show three input LUT, occupies 8 storage units and 7 alternative MUX resources, functional relation Y
(A, B, C)；Fig. 1 c show four input LUT, occupies 16 storage units and 15 alternative MUX resources, functional relation
For Y (A, B, C, D)；Fig. 1 d show five input LUT, occupies 32 storage units and 31 alternative MUX resources, function
Relationship is Y (A, B, C, D, E).
As shown in Fig. 2, providing the structure chart of six input LUT.The six inputs LUT look-up table occupies 64 storages in total
Unit and 63 alternative MUX resources are made of two five input LUT, can fast implement the logic function of LUT5 and LUT6,
Y1 is the output of LUT5, and Y2 is the output of LUT6, and functional relation is Y1 (A, B, C, D, E), and Y2 (A, B, C, D, E, F) is this
Six input LUT structures be convenient for software realization, can Rapid matching, to improve speed.
Fig. 3 is the equivalent graph that Fig. 2 six inputs LUT structure, and Y1 is still the output of LUT5, and Y2 is still the output of LUT6, letter
Number relationship is still Y1 (A, B, C, D, E), Y2 (A, B, C, D, E, F), and a LUT4 can be by two LUT3 and alternative MUX
It realizes, and two LUT4 add one LUT5 of a MUX equivalence.
Fig. 4 show the structure chart of two minor feature LUT.It and Fig. 3 structure similarly include two groups of LUT4,
LUT3, LUT3 combination, the difference is that inserting one group of MUX 5 and MUX 6 in the MUX of the second level, and add one in the first order
A MUX 2, and used four storage units R1, R2, R3, R4 and MUX 15,16,17,18 as realization different functions more
Piece selected control system when function.A, B, C, D, E0, F0, E1, F1 are respectively eight input ports；A and B be respectively two groups of LUT4,
The shared address line input port of LUT3, LUT3 (9,10,11,12,13,14)；C be above one group of LUT4, LUT3, LUT3 (9,
10,11) shared address line input port, at the same can by MUX16 select control MUX 8, as following set LUT4,
The shared address line input port of LUT3, LUT3 (12,13,14)；D is following set LUT4, LUT3, LUT3 (12,13,14)
Shared address line input port, while control MUX 7 can be selected by MUX 15, as one group of LUT4, LUT3, LUT3 above
The shared address line input port of (9,10,11)；An optional input port of the E0 as MUX 15, while also driving MUX
17, MUX 17 output control MUX 3 and 12 output driving MUX 3 of 9 output driving MUX 3 of MUX 4, LUT4 and MUX 5, LUT4
Drive MUX 7, LUT3 13 and LUT3 14 that MUX 8, MUX 7 is driven to drive simultaneously simultaneously with MUX 5, LUT3 10 and LUT3 11
MUX 4 and MUX 6, MUX 8 drives MUX 4 and MUX 6；The input of the port F0 directly controls MUX1, MUX 3 and MUX 4 and drives simultaneously
Dynamic MUX 1, Y1 is the output port of MUX 1；Up-down structure is symmetrical, an optional input port of the E1 as MUX 16, simultaneously
Also MUX 18, the output control of MUX 18 MUX 5 and MUX 6 are driven；The input of the port F1 directly controls MUX 2, and the two-way of MUX 2 is defeated
Enter the output from MUX 5 and MUX 6, Y2 is the output port of MUX2.
Five input LUT functions, four input LUT may be implemented according to different configurations in two minor feature LUT look-up tables
Function, three input LUT functions, two input LUT functions can also realize the combined LUT function of other different inputs, below will be detailed
The mode of different input LUT is carefully described.
A.LUT5 mode
When work is in LUT5 mode, MUX 17 is by storage unit R2 configuration gating GND signal, and MUX 3 and MUX4 are all
Selection first (mark " 0 " end, similarly hereinafter) signal input, i.e., it is fixed to have gated one group of LUT4, LUT3, LUT3 (9,10,11) above
With two outputs of MUX 7.For MUX 18 by storage unit R4 configuration gating VCC signal, MUX5 and MUX 6 all select second
The input of (mark " 1 " end, similarly hereinafter) signal, i.e., fixed following set LUT4, LUT3, LUT3 (12,13,14) and the MUX 8 of having gated
Two outputs.MUX 15 passes through storage unit R3 configuration gating by storage unit R1 configuration gating E0 port signal, MUX 16
E1 port signal.
This configuration mode effectively half-and-half divides circuit structure, and function is reduced to two independent five inputs LUT functions,
Share two port A and B input signals.Y1 port output signal is A, B, C, E0, the function of the port F0 input signal, i.e. Y1
(A, B, C, E0, F0)；Y2 port output signal is A, B, D, E1, the function of the port F1 input signal, i.e. Y2 (A, B, D, E1,
F1)。
B.LUT4 mode
When work is in LUT4 mode, MUX 15, MUX 16, MUX 17, the configuration gated fashion of MUX 18 and above-mentioned
LUT5 mode is identical, the difference is that the storage unit in LUT can ignore respectively two groups of LUT's of circuit or more by special configuration
One input.For example, the storage unit in one group of LUT4, LUT3, LUT3 (9,10,11) above can make the end B by special configuration
Mouth input signal is effectively ignored, i.e., the signal that the value of B will not influence the port port Y1 exports result.Equally, following set
Storage unit in LUT4, LUT3, LUT3 (12,13,14) can be such that the port A input signal is effectively neglected by special configuration
Slightly, i.e., the signal that the value of A will not influence the port signal Y2 exports result.Therefore, Y1 port output signal is A, C, E0, the port F0
The function of input signal, i.e. Y1 (A, C, E0, F0).Y2 port output signal is B, D, E1, the function of the port F1 input signal, i.e.,
Y2 (B, D, E1, F1).Under this configuration mode, two independent LUT4 function performances may be implemented, it is shared defeated without having
Enter signal.
C.LUT3 mode
When work is in LUT3 mode, MUX 15, MUX 16, MUX 17, the configuration gated fashion of MUX 18 and above-mentioned
LUT4 mode is identical, the difference is that the storage unit in LUT ignores the circuit end that two groups of LUT are shared up and down by special configuration
The value of mouth A and B input signal, i.e. A and B all will not influence the signal output result of port Y1 and Y2.Therefore, the port Y1 output letter
It number is C, E0, the function of the port F0 input signal, i.e. Y1 (C, E0, F0)；Y2 port output signal is D, E1, the port F1 input letter
Number function, i.e. Y2 (D, E1, F1).Under this configuration mode, two independent LUT3 function performances may be implemented, without having
Shared input signal.
D.LUT2 mode
When work is in LUT2 mode, MUX 15, MUX 16, MUX 17, the configuration gated fashion of MUX 18 and above-mentioned
LUT3 mode is identical, the difference is that the storage unit in LUT ignores A in circuit, B, the port C and D input letter by special configuration
Number, i.e. A, B, the value of C and D all will not influence the signal output result of the port Y1 and Y2.Therefore, Y1 port output signal is E0,
The function of the port F0 input signal, i.e. Y1 (E0, F0).Y2 port output signal is E1, the function of the port F1 input signal, i.e. Y2
(E1, F1).Under this configuration mode, two independent LUT2 function performances may be implemented, without having shared input signal.
Above-mentioned each LUT mode can be combined with each other into different LUT modes again, realizes flexibly switching, can effectively keep away
Exempt from the wasting of resources of six input LUT look-up tables, two minor feature LUT look-up tables improve the flexibility ratio of LUT configuration, operation energy
Power and logic utilization rate, save LUT resource.
Fig. 5 is a kind of eight input look-up table configuration schematic diagrames of non-all standing, it is the comprehensive of the both of which of Fig. 3 and Fig. 4
It closes.Eight input look-up table configurations of non-all standing are on the basis of fig. 4, to increase storage unit R0 and by R0 as common
Alternative MUX 19, MUX 20, MUX 21, MUX 22, MUX 23, MUX 24 and the MUX 25 of control terminal.MUX3 and MUX 2 are defeated
Driving MUX 19, Y2 out is the output of MUX 19.MUX 22, MUX 23, MUX 24 and MUX 25 an input terminal connect respectively
VCC, the other end are connect respectively on storage unit R1, R2, R3, R4, and the output of four MUX controls gating MUX 15, MUX respectively
17,MUX 16,MUX 18.Signal C and D are input to MUX21, and signal E1 and MUX21 output respectively drive MUX 20, MUX 20 again
MUX 15 is given in output.
Six input LUT modes: as R0=0, the circuit function of realization is identical as structure in Fig. 3.MUX 22,MUX 23,
MUX 24 and MUX 25 gates VCC signal respectively, and MUX 20 selects e1 port signal, and MUX 21 selects C port signal, MUX
MUX 15 is given in 20 output, and MUX 16 selects e1 port input signal, and MUX 17 selects the port E0 input signal, and MUX 18 is selected
Select VCC signal.At this point, A, B, C, E0, F0, e1 port input signal is effective input signal, the port D and F1 input signal not by
Gating is invalid input signal.The port Y1 is the output port of LUT6, and the port Y2 is the output port of LUT5, functional relation point
It Wei not Y1 (A, B, C, E0, F0, E1) and Y2 (A, B, C, E0, E1).
Two minor feature LUT modes: as R0=1, the circuit function of realization is identical as structure in Fig. 4.MUX 22,
MUX 23, MUX 24 and MUX 25 gate storage unit R1, R2, R3, R4 control signal respectively, successively control MUX15, MUX
17,MUX 16,MUX 18.The signal that MUX 20 selects MUX 21 to export, MUX 21 select D port signal, and MUX 19 gates MUX
Output of 2 output as the port Y2, the port Y1 are the output port of MUX 1.According to it is different input LUT configurations, eight A,
The port B, C, D, E0, F0, E1, F1 input signal all can be used as effective input signal.Two minor feature LUT mode configurations and figure
4 configuration mode is identical, realizes the LUT power function relationship of various combination are as follows:
A. it is configured to LUT3 and LUT2, shares 0 input signal, functional relation is Y1 (C, E0, F0) and Y2
(E1, F1).
B. two LUT3 are configured to, 0 input signal is shared, functional relation is Y1 (C, E0, F0) and Y2 (D, E1, F1).
C. be configured to LUT4 and LUT3, share 0 input signal, functional relation be Y1 (A, C, E0, F0) and
Y2 (D, E1, F1).
D. two LUT4 are configured to, share 0 input signal, functional relation be Y1 (A, C, E0, F0) and Y2 (B, D, E1,
F1)。
E. it is configured to LUT5 and LUT2, shares 0 input signal, functional relation is Y1 (A, B, C, E0, F0)
With Y2 (E1, F1).
F. it is configured to LUT5 and LUT3, shares 0 input signal, functional relation is Y1 (A, B, C, E0, F0)
With Y2 (D, E1, F1).
G. it is configured to LUT5 and LUT4, shares 1 input signal, functional relation is Y1 (A, B, C, E0, F0)
With Y2 (A/B, D, E1, F1).
H. two LUT5 are configured to, share 2 input signals, functional relation be Y1 (A, B, C, E0, F0) and Y2 (A, B, D,
E1, F1).
Eight input look-up table configurations of this non-all standing, can flexibly be switched by configuration unit.As storage unit R0
When control is switched to six input LUT modes, the vanning of LUT can be fast implemented, reduces software runing time；When being switched to two
When minor feature LUT mode, by increasing the input of 2 road look-up tables, sharing for input signal can be reduced, can flexibly be realized
The look-up table of the various combinations such as LUT2, LUT3, LUT4 and LUT5.Using the look-up table configuration, can be improved LUT utilization rate and
Flexibility ratio reduces software runing time.
Claims (6)
1. a kind of eight input look-up table configurations of non-all standing, it is characterised in that: the look-up table configuration includes 25 and patrols substantially
Unit is collected, 2 LUT4,4 LUT3 and 19 alternative MUX are contained；10 signal ports contain 8 signal input ports A, B, C,
D, E0, F0, E1, F1 and 2 signal output ports Y1, Y2；5 for controlling six LUT and two minor feature LUT mode of input
The storage unit of switching is R0, R1, R2, R3 and R4, by different configurations, the combined LUT function of the different inputs of realization；Institute
8 signal input ports A, B, C, D, E0, F0, E1, F1 and 2 signal output ports Y1, Y2 are stated, wherein the port A and B input letter
Number be respectively two groups of LUT4, LUT3, LUT3 shared address line；C port input signal is one group of LUT4, LUT3, LUT3 above
Shared address line, while by alternative MUX selection control, the shared address as following set LUT4, LUT3, LUT3
Line；The port D input signal is the shared address line of following set LUT4, LUT3, LUT3, while passing through alternative MUX selection control
System, the shared address line as one group of LUT4, LUT3, LUT3 above；E0 and e1 port input signal pass through alternative MUX respectively
Control gating, as the shared address line of two groups of LUT4, LUT3, LUT3 in different modes；The port F0 and F1 input signal point
Not Wei look-up table configuration two independent address lines；The port Y1 and Y2 is respectively the common output end of look-up table configuration both of which
Mouthful；Described two minor feature LUT modes are as R0=1, and each MUX gates storage unit R1, R2, R3, R4 conduct respectively
Signal is controlled, according to the configuration of different input LUT, 8 A, B, C, D, E0, F0, E1, the port F1 input signal is as effectively input
Signal, the port Y1 and Y2 are respectively the output port of the LUT under different configurations, realize LUT2, LUT3, LUT4 and LUT5 difference group
Close function；
According to the configurations of different input LUT, eight A, B, C, D, E0, F0, E1, the port F1 input signal all can be used as effective input
Signal；Two minor feature LUT mode configurations realize the LUT power function relationship of various combination are as follows:
A. be configured to LUT3 and LUT2, share 0 input signal, functional relation be Y1 (C, E0, F0) and Y2 (E1,
F1)；
B. two LUT3 are configured to, 0 input signal is shared, functional relation is Y1 (C, E0, F0) and Y2 (D, E1, F1)；
C. be configured to LUT4 and LUT3, share 0 input signal, functional relation be Y1 (A, C, E0, F0) and Y2 (D,
E1, F1)；
D. two LUT4 are configured to, 0 input signal is shared, functional relation is Y1 (A, C, E0, F0) and Y2 (B, D, E1, F1)；
E. it is configured to LUT5 and LUT2, shares 0 input signal, functional relation is Y1 (A, B, C, E0, F0) and Y2
(E1, F1)；
F. it is configured to LUT5 and LUT3, shares 0 input signal, functional relation is Y1 (A, B, C, E0, F0) and Y2
(D, E1, F1)；
G. it is configured to LUT5 and LUT4, shares 1 input signal, functional relation is Y1 (A, B, C, E0, F0) and Y2
(A/B, D, E1, F1)；
H. two LUT5 are configured to, share 2 input signals, functional relation be Y1 (A, B, C, E0, F0) and Y2 (A, B, D, E1,
F1)。
2. eight input look-up table configurations of non-all standing according to claim 1, it is characterised in that: 2 LUT4,4
A LUT3 is upper and lower two groups mutually isostructural LUT4, LUT3, LUT3 unit combinations.
3. eight input look-up table configurations of non-all standing according to claim 1, it is characterised in that: 19 alternatives
MUX is used for the alternative MUX and 12 alternative MUX for realizing shared lookup table logic of pattern switching including 7.
4. eight input look-up table configurations of non-all standing according to claim 1, it is characterised in that: described 5 for controlling
System six input LUT and two minor feature LUT pattern switching storage units, wherein storage unit R0 control six input LUT and
Two minor feature LUT pattern switchings, storage unit R1, R2, R3 and R4 are that control is Bu Tong defeated under two minor feature LUT modes
Enter the LUT function of combination.
5. eight input look-up table configurations of non-all standing according to claim 1, it is characterised in that: the six inputs LUT
Mode is as R0=0, and each MUX controls gating A, B, C, E0, F0, e1 port input signal and VCC signal, D and F1 respectively
Port input signal is not gated on and invalid, realization LUT5 and LUT6 function.
6. eight input look-up table configurations of non-all standing according to claim 1, it is characterised in that: described by different
Configuration, the combined LUT function of the different inputs of realization are to realize a LUT6 and realization one when configuring in six input LUT modes
A LUT5；It when configuring in two minor feature LUT modes, realizes LUT3 and LUT2, realizes two LUT3, realize
One LUT4 and LUT3, realizes two LUT4, realizes LUT5 and LUT2, realizes one LUT5 and one
LUT3 realizes LUT5 and LUT4, realizes two LUT5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610331171.1A CN105958996B (en) | 2016-05-18 | 2016-05-18 | A kind of eight input look-up table configurations of non-all standing |
Applications Claiming Priority (1)
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| CN111934670A (en) * | 2020-08-17 | 2020-11-13 | 电子科技大学 | FPGA (field programmable Gate array) framework of quasi-N lookup table |
| CN113746473B (en) * | 2021-08-19 | 2022-04-22 | 北京中科胜芯科技有限公司 | Lookup table structure capable of realizing distributed memory function |
| CN113746474B (en) * | 2021-08-19 | 2022-04-22 | 北京中科胜芯科技有限公司 | Multi-granularity lookup table structure |
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