CN105955870B - A kind of monitoring system of FPGA operating statuses - Google Patents
A kind of monitoring system of FPGA operating statuses Download PDFInfo
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- CN105955870B CN105955870B CN201610346559.9A CN201610346559A CN105955870B CN 105955870 B CN105955870 B CN 105955870B CN 201610346559 A CN201610346559 A CN 201610346559A CN 105955870 B CN105955870 B CN 105955870B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3013—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
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Abstract
The present invention proposes a kind of monitoring system of FPGA operating statuses, including internal processing modules and outer watchdog circuit module, it is characterized in that, the internal processing modules include work clock domain and diagnosis clock domain, the work clock domain includes functional diagnosis module, and the diagnosis clock domain includes work clock diagnostic module, internal watchdog module and classification processing module.The present invention designs for dual clock domain, the gradable processing of failure, it is not necessary to which institute is faulty all to reset FPGA overall work clock domains, improves the availability of system.
Description
Technical field
The present invention relates to industrial control system more particularly to a kind of monitoring systems of FPGA operating statuses.
Background technology
The work of FPGA can be interfered by external electromagnetic field, radiation, circuit sequence poor designs, state machine design are unreasonable
Deng being absorbed in endless loop, whole system caused to be absorbed in dead state, unpredictable consequence occurs.
The real-time monitoring to FPGA operating statuses may be implemented in watchdog circuit so that system is in the state of unmanned monitoring
Continuous work.The design method of general adoption status machine, writes code, realization is seen using Verilog HDL language inside FPGA
The function of door dog circuit, Fig. 1 are typical FPGA watchdog circuits internal state realization method.If EN makes in free position
Energy signal is prohibited, then state machine enters IDLE state.Enter WAIT states after system power-on reset, the NUM3 times is waited for make
FPGA completes initialization；Into IDLE state, watchdog function is enabled；Into the cumulative timing of ADDING states, if limiting
Feeding-dog signal is monitored in time NUM1, shows program normal operation, is returned to IDLE state and is waited for feeding-dog signal next time, if
Do not receive feeding-dog signal more than NUM1, it is believed that program run it is winged, into EEROR states；Output reset signal in EEROR states
And reset counter；Into KEEPING states, low level is set to keep a period of time NUM2, this period is more than needed for FPGA
Resetting time；Into WAIT states, FPGA is resumed waiting for after reset and completes initialization, is moved in circles.FPGA external connections
Watchdog circuit realizes the mode for FPGA allomeric functions reset operation, and circuit implementations will be as shown in Fig. 2, will
The feeding-dog signal of the I/O foot connection watchdog circuit of FPGA, another I/O foot connects reset signal, by being compiled to FPGA
Journey constantly carries out feeding dog, stops feeding dog after winged, functional block fails when FPGA state machines are run, watchdog circuit carries out FPGA whole
Body resets operation.
Existing FPGA house dogs design scheme there are the problem of be operated in a clock domain for FPGA, not to system clock
The measure of monitoring, when internal logic breaks down, treatment measures are to reset entire logic function.
Invention content
To solve the above-mentioned problems, the present invention proposes a kind of monitoring system of FPGA operating statuses, including inter-process
Module and outer watchdog circuit module, which is characterized in that the internal processing modules include work clock domain and diagnosis clock
Domain, the work clock domain include functional diagnosis module, and the diagnosis clock domain includes that work clock diagnostic module, inside are guarded the gate
Dog module and classification processing module；
The work clock domain generates work clock domain clock signal, and work clock domain clock signal is sent to work
Make clock diagnostic module；
The functional diagnosis module, receive capabilities fault-signal generate feeding-dog signal and are sent to the classification processing mould
Block；
The diagnosis clock domain generates diagnosis clock domain clock signal；The work clock diagnostic module will be described in reception
Work clock domain clock signal is compared with the diagnosis clock domain clock signal, judges work clock domain clock letter
Number and the deviation of the diagnosis clock domain clock signal whether transfinite, and generate feeding-dog signal and be sent to the classification and handle mould
Block；
Internal divide in advance has formant functional block in the work clock domain, if formant functional block event
Barrier, then the classification processing module executes Global reset, if the functional block failure in unit functional module, the classification
Processing module executes local reset；If the low level signal sent out from work clock diagnostic module, resets work clock domain
Interior all functional blocks；If be simultaneously from the work clock diagnostic module and the functional diagnosis module, FPGA is carried out
Global reset processing；
The internal watchdog module generates the pulse feeding-dog signal of low and high level every the set time, and signal is sent out
It send to outer watchdog circuit module；
The outer watchdog circuit module receives the pulse feeding-dog signal for the low and high level that internal house dog generates, concurrently
It send and resets diagnostic signal to internal watchdog module.
Further, the work clock domain is driven by external work clock crystal oscillator.
Further, the diagnosis clock domain is driven by diagnosis clock crystal oscillator.
Further, the clock frequency in the work clock domain will be less than the clock frequency of the diagnosis clock domain.
Further, the functional diagnosis module includes register, and the register bit position generates feeding-dog signal.
Further, the feeding-dog signal that the register bit position generates depends on the value of register, and described value is 1 generation
High level feeding-dog signal, described value are 0 generation low level feeding-dog signal.
Further, if the fault-signal of functional diagnosis module reception is effective, low level feeding-dog signal is generated, if
The fault-signal of reception is invalid, then generates high level feeding-dog signal.
Further, if the work clock diagnostic module judges work clock domain clock signal with the diagnosis
The deviation of clock domain clock signal transfinites, then generates low level feeding-dog signal, if not transfiniting, generate high level feeds dog letter
Number.
Further, the outer watchdog circuit module is watchdog chip.
The present invention designs a kind of monitoring system of FPGA operating statuses, to FPGA implement dual clock domain (work clock domain with
Diagnose clock domain), can whether working properly by diagnosing clock domain diagnostic work clock domain, while by FPGA internal functional blocks
Fault category carries out classification processing, and is internally integrated house dog and external watchdog circuit and can realize diagnosis, guarantee house dog
The validity of circuit design.
Description of the drawings
Fig. 1 is existing FPGA house dogs realization method；
Fig. 2 is the plug-in watchdog circuits of existing FPGA；
Fig. 3 is dual clock domain in the present invention, double watchdogs diagnosis Organization Chart；
Fig. 4 is inside and outside watchdog reset diagnostic process in the present invention；
Fig. 5 is that inside and outside house dog mutually examines pulse signal in the present invention；
Fig. 6 is to execute to reset resolution flow chart in classification processing module in the present invention.
Specific implementation mode
A kind of specific implementation mode of the monitoring system of FPGA operating statuses of the present invention is carried out below in conjunction with the accompanying drawings detailed
Illustrate, examples are only for illustrating the present invention and not for limiting the scope of the present invention for this, and those skilled in the art are to the present invention
The modifications of various equivalent forms fall within the application range as defined in the appended claims.
Such as Fig. 3, a kind of monitoring system of FPGA operating statuses, including the internal processing modules that are arranged inside FPGA and set
Set the outer watchdog circuit module outside FPGA.The working regions FPGA are divided into two different clock-domains, that is, when working
Clock domain and diagnosis clock domain.By different external clock reference (work clock crystal oscillator and diagnosis clock crystal oscillator) driving, when work
Clock crystal oscillator is crystal oscillator, clock frequency necessary to working mainly for generation of FPGA；Diagnosis clock crystal oscillator is crystal
Oscillator is mainly used for driving diagnosis clock domain；The clock frequency in work clock domain will be less than the clock frequency of diagnosis clock domain.
Work clock domain includes functional diagnosis module, and diagnosis clock domain includes work clock diagnostic module, internal watchdog module and divides
Grade processing module.
It is to carry out Global reset or local reset as FPGA, can be divided according to the significance level of functional block,
Under normal circumstances, the formant functional block failure being in work clock domain executes Global reset, is in unit functional module
Interior functional block failure only executes local reset.
Functional diagnosis module receives the functional fault input signal generated when FPGA operations, is produced when by judging FPGA operations
Raw fault input signal is that high level generates the feeding-dog signal of high level in vain；It is defeated that functional diagnosis module receives functional fault
It is that low level effectively generates low level feeding-dog signal to enter signal.The bit of the corresponding register of functional diagnosis module generates
0 or 1,0 is low, and 1 is height.
Work clock diagnostic module by judge work clock domain clock signal itself shake deviation (JITTER) be
No influence clock sampling generates the feeding-dog signal of low and high level pulse.If the module judgment bias transfinites, generate low level
Feeding-dog signal generates the feeding-dog signal of high level if not transfiniting.
Above-mentioned two feeding-dog signal is sent to classification processing module, classification processing module is determined according to the source of feeding-dog signal
Whether local reset, Global reset are carried out to work clock domain-functionalities or operated without resetting.
If unit functional module generates low level fault signal, the local reset function of triggering classification processing module resets
Local function block, local reset function are to select reset function block according to the fault-signal that functional diagnosis module receives.If work
Clock diagnostic module judges that the clock signal in work clock domain generates fault-signal beyond predetermined range or main functional modules,
Belong to catastrophe failure, then generate low level signal, the global reset function of triggering classification processing module resets in work clock domain
All functional modules.
If work clock diagnostic module and functional diagnosis module receive fault-signal simultaneously, and send out feeding-dog signal to classification
Processing module is then classified processing module and is handled by Global reset, all functional modules in Global reset work clock domain.
Internal watchdog module is operated in diagnosis clock domain, and by diagnosing clock source driving, Verilog programmings are internal to be seen
Door dog module generates the pulse feeding-dog signal of low and high level every the set time, and feeding-dog signal is sent to outer watchdog circuit mould
Block.Internal watchdog module is primary every set time hello dog, while receiving the reset from outer watchdog circuit module and examining
Break signal decides whether to reset full wafer by being compared with expected setting value to resetting the diagnostic signal low level time
FPGA。
Outer watchdog circuit module is realized by traditional watchdog chip, generally by bridging capacitance pair of different sizes
Resetting time is arbitrarily adjusted.Meanwhile internal watchdog module can not also feed dog according to outer watchdog circuit module, sentence
Disconnected outer watchdog circuit module is bad, and carries out reset operation to full wafer FPGA.
Internal house dog is fed by the functional diagnosis module in work clock domain and the work clock diagnostic module of diagnosis clock domain
Dog, and feeding-dog signal is handled, classification processing is carried out according to different failure ranks, determines to carry out Global reset or office
Portion resets.The leveled reset functional block of internal house dog is external mainly by judging the feeding-dog signal of diagnostic work clock diagnosis
The failure rank that the reset diagnostic signal of house dog reports selects different reset modes, wherein outer watchdog failure reset whole
Piece FPGA (including work clock domain and diagnosis clock domain)；Work clock troubleshooting executes Global reset；Diagnostic function failure,
It then needs, according to failure rank, to execute Global reset or local reset, as shown in table 1, work clock domain failure then executes the overall situation
It resets (work clock domain-functionalities module)；Unit functional module failure need to according to the significance level of module execute local reset or
Global reset, such as table 2；House dog failure then executes FPGA resets.
Such as Fig. 6, the workflow for being classified processing module is it is first determined whether generating low level event by clock diagnostic module
Hinder signal, if so, executing Global reset, otherwise the whether faulty signal of judging unit function block register generates, if not having
Fault-signal generates, then does not reset, if faulty signal generates and then needs to judge the position of the fault-signal in a register
Whether it is main functional unit block fault bit, if so then execute Global reset, otherwise only executes local reset.
| Work clock failure | House dog failure | Unit functional module failure |
| Global reset | FPGA resets | Local reset or Global reset |
Table 1
Table 2
The present invention is operated under dual clock domain, i.e. work clock domain and diagnosis clock domain, resets the work of entire FPGA
Principle：At work, the house dog timing reset time is arbitrarily arranged as 2ms by outer watchdog circuit flying capcitor, passed through
To internal house dog programming realize every 1ms periodically generate feeding-dog signal to outer watchdog feed dog it is primary, internal house dog feed
Ten times, the tenth primary feeding-dog signal for sending out a 2.01ms is then reciprocal successively.When outer watchdog circuit is confiscated
When the feeding-dog signal of 2.01ms, if receiving the feeding-dog signal time is less than 2.01ms, narrow pulse signal will not be internally generated, it will not
Internal house dog is fed, entire FPGA can be resetted by outer watchdog, if receiving the feeding-dog signal time is more than 2.01ms, will produce
More than the pulse signal of setting range, it is believed that watchdog circuit module failure can also reset entire FPGA；When outer watchdog electricity
When road module receives the feeding-dog signal of 2.01ms, the low level signal (resetting diagnostic signal) of a 10us can be sent out, is sent to
The burst pulse that outer watchdog generates is considered invalid reset signal by internal house dog, internal house dog, keeps normal work
Make.The internal watchdog module of setting resets low level burst pulse of the Diagnostic Time less than 12us and is considered normal signal (such as Fig. 5)；
When the burst length that outer watchdog is sent out is more than that internal house dog judges the burst pulse time, i.e. house dog inside 12.12ms
Module does not receive 10us feeding-dog signals or receives the burst pulse more than 12us, then it is assumed that the event of outer watchdog circuit module
Barrier stops feeding dog, resets entire FPGA, workflow is as shown in Figure 4.
It can realize that watchdog module is guarded the gate with outside inside FPGA built-in functions leveled reset and FPGA by the above means
Dog circuit module is mutually examined, and ensures the reliability of FPGA work.
The present invention designs for dual clock domain, and each function section works without crosstalk, by diagnosing clock to work clock
The diagnosis of JITTER ensures that the function of tonic chord worked under system clock is effective, classification processing is carried out to logic fault in FPGA, right
The functional block failure of host state machine carries out Global reset under work clock domain, and part is carried out to sub-state machine auxiliary function block failure
It resets；The method diagnosed using double watchdogs, by outer watchdog, periodically internally house dog sends reset diagnostic signal, interior
Portion house dog periodically feeds the mode of outer dog, and guarantee is internally integrated effective in real time with the watchdog circuit of external connection.
The preferred embodiment of the present invention is described in detail above in association with attached drawing, still, the present invention is not limited to above-mentioned realities
The detail in mode is applied, within the scope of the technical concept of the present invention, a variety of letters can be carried out to technical scheme of the present invention
Monotropic type, these simple variants all belong to the scope of protection of the present invention.
Claims (9)
1. a kind of monitoring system of FPGA operating statuses, including internal processing modules and outer watchdog circuit module, feature
It is, the internal processing modules include work clock domain and diagnosis clock domain, and the work clock domain includes functional diagnosis mould
Block, the diagnosis clock domain include work clock diagnostic module, internal watchdog module and classification processing module；
The work clock domain generates work clock domain clock signal, when work clock domain clock signal is sent to work
Clock diagnostic module；
The functional diagnosis module, receive capabilities fault-signal generate feeding-dog signal and are sent to the classification processing module；
The diagnosis clock domain generates diagnosis clock domain clock signal；The work clock diagnostic module is by the work of reception
Clock domain clock signal is compared with the diagnosis clock domain clock signal, judge work clock domain clock signal with
Whether the deviation of the diagnosis clock domain clock signal transfinites, and generates feeding-dog signal and be sent to the classification processing module；
Internal divide in advance has formant functional block in the work clock domain, if the formant functional block failure,
The classification processing module executes Global reset, if the functional block failure in unit functional module, the classification processing
Module executes local reset；If the low level signal sent out from work clock diagnostic module resets institute in work clock domain
Functional piece；If be simultaneously from the work clock diagnostic module and the functional diagnosis module, FPGA is carried out global
Reset processing；
The internal watchdog module generates the pulse feeding-dog signal of low and high level every the set time, and sends the signal to
Outer watchdog circuit module；
The outer watchdog circuit module receives the pulse feeding-dog signal for the low and high level that internal house dog generates, and sends multiple
Position diagnostic signal gives internal watchdog module.
2. the monitoring system of FPGA operating statuses according to claim 1, which is characterized in that the work clock domain is by outer
Portion's work clock crystal oscillator driving.
3. the monitoring system of FPGA operating statuses according to claim 1, which is characterized in that the diagnosis clock domain is by examining
Disconnected clock crystal oscillator driving.
4. the monitoring system of FPGA operating statuses according to claim 1, which is characterized in that the work clock domain when
Clock frequency will be less than the clock frequency of the diagnosis clock domain.
5. the monitoring system of FPGA operating statuses according to claim 1, which is characterized in that the functional diagnosis module packet
Register is included, the register bit position generates feeding-dog signal.
6. the monitoring system of FPGA operating statuses according to claim 5, which is characterized in that the register bit position production
Raw feeding-dog signal depends on the value of register, and described value is 1 generation high level feeding-dog signal, and described value is 0 generation low level
Feeding-dog signal.
7. the monitoring system of FPGA operating statuses according to claim 1, which is characterized in that if the functional diagnosis module
The fault-signal of reception is effective, then generates low level feeding-dog signal, if the fault-signal received is invalid, generates high level and feeds dog
Signal.
8. the monitoring system of FPGA operating statuses according to claim 1, which is characterized in that the work clock diagnoses mould
If block judges that work clock domain clock signal and the deviation of the diagnosis clock domain clock signal transfinite, low level is generated
Feeding-dog signal generate the feeding-dog signal of high level if not transfiniting.
9. the monitoring system of FPGA operating statuses according to claim 1, which is characterized in that the outer watchdog circuit
Module is watchdog chip.
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| CN106527295B (en) * | 2016-12-28 | 2018-11-02 | 中核控制系统工程有限公司 | The diversity framework of safety level DCS double FPGAs |
| CN108919698B (en) * | 2018-06-07 | 2022-03-15 | 浙江国自机器人技术股份有限公司 | Monitoring system and method for controlling CPU in real time and mobile robot |
| CN111061243B (en) * | 2018-10-17 | 2023-05-26 | 联合汽车电子有限公司 | Electronic controller program flow monitoring system and method |
| CN111856916A (en) * | 2019-04-30 | 2020-10-30 | 联合汽车电子有限公司 | External clock diagnosis method |
| CN110794817A (en) * | 2019-12-03 | 2020-02-14 | 中国兵器装备集团自动化研究所 | Fault safety type current output channel diagnosis system and method thereof |
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| CN101089823A (en) * | 2006-06-12 | 2007-12-19 | 深圳市研祥智能科技股份有限公司 | Computer watchdog device and its working method |
| JP2012183877A (en) * | 2011-03-04 | 2012-09-27 | Calsonic Kansei Corp | Detection processing device of vehicle occupant protection system |
| CN104122854A (en) * | 2014-06-04 | 2014-10-29 | 华中科技大学 | Central controller of built-in power source system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101089823A (en) * | 2006-06-12 | 2007-12-19 | 深圳市研祥智能科技股份有限公司 | Computer watchdog device and its working method |
| JP2012183877A (en) * | 2011-03-04 | 2012-09-27 | Calsonic Kansei Corp | Detection processing device of vehicle occupant protection system |
| CN104122854A (en) * | 2014-06-04 | 2014-10-29 | 华中科技大学 | Central controller of built-in power source system |
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