CN105932966B - A kind of method and device generating digital sinusoidal signal - Google Patents
A kind of method and device generating digital sinusoidal signal Download PDFInfo
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- CN105932966B CN105932966B CN201610250784.2A CN201610250784A CN105932966B CN 105932966 B CN105932966 B CN 105932966B CN 201610250784 A CN201610250784 A CN 201610250784A CN 105932966 B CN105932966 B CN 105932966B
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- subinterval
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- sinusoidal signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B28/00—Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations
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Abstract
The invention discloses a kind of method and device generating digital sinusoidal signal, this method includes：The phase interval of digital sinusoidal signal is divided into multiple first subintervals；Each in multiple first subintervals is divided into multiple second subintervals；Each in multiple second subintervals is divided into multiple third subintervals；The phase value of digital sinusoidal signal to be generated is expressed as to the sum of phase initial value, the phase initial value corresponding to the second subinterval, the phase initial value corresponding to third subinterval and surplus corresponding to the first subinterval where it；And the digital sinusoidal signal value corresponding to integral multiple and surplus, signal value is calculated to generate digital sinusoidal signal with differenceization product formula.
Description
Technical field
The present invention relates to digital signal processing technique field more particularly to a kind of methods and dress generating digital sinusoidal signal
It sets.
Background technology
Digital sinusoidal signal can be generated by Direct Digital Synthesizer (DDS).The basic principle of DDS is to utilize
Sampling thheorem generates waveform by look-up table.
Fig. 1 shows the functional block diagram of DDS.Phase accumulator therein can be by the output of adder and phase register
Composition.Often carrying out a clock pulses, frequency control word K is added by adder with the accumulated phase data that phase register exports,
Result after being added is sent to the data input pin of accumulator register.Accumulator register is by adder in upper clock pulses institute
The new phase data feedback of generation to adder input terminal so that adder is when next clock pulses inputs, frequency
Control word accumulates once, and the data of phase accumulator output are exactly the phase of composite signal, and the spilling frequency of phase accumulator is just
It is the signal frequency of DDS outputs.Use the data that phase accumulator exports as the phase-samplomh address of wave memorizer (ROM),
The waveform sample value being stored in memory can thus be found, complete conversion of the phase to amplitude.Wave memorizer
Output can be sent to D/A converter, and the waveforms amplitude of digital quantity form can be converted to required frequency synthesis by D/A converter
Analog signal.
In order to improve generation signal precision, the prior art use increase phase quantization value number method, but
This can consume more wave memorizer spaces.
Invention content
The purpose of the present invention is to provide a kind of method and devices generating digital sinusoidal signal, to solve in the prior art
The problem of contradiction between existing signal accuracy and memory space.
An embodiment provides a kind of methods generating digital sinusoidal signal, including：Digital sine is believed
Number phase interval be divided into multiple first subintervals；Each in multiple first subintervals is divided into multiple second
Subinterval；Each in multiple second subintervals is divided into multiple third subintervals；By digital sinusoidal signal to be generated
Phase value be expressed as the phase initial value corresponding to the first subinterval where it, the starting of the phase corresponding to the second subinterval
The sum of phase initial value and surplus corresponding to value, third subinterval；And the number corresponding to integral multiple and surplus
Word sinusoidal signal value calculates signal value to generate digital sinusoidal signal with differenceization product formula.
An alternative embodiment of the invention provides a kind of device generating digital sinusoidal signal, including：First subinterval
Division module, for the phase interval of digital sinusoidal signal to be divided into multiple first subintervals；Second subinterval divides
Module, for each in multiple first subintervals to be divided into multiple second subintervals；Third subinterval division module is used
In each in multiple second subintervals is divided into multiple third subintervals；Phase value decomposing module, being used for will be to be generated
The phase value of digital sinusoidal signal be expressed as phase initial value corresponding to the first subinterval where it, the second subinterval institute
The sum of phase initial value and surplus corresponding to corresponding phase initial value, third subinterval；And range value computing module,
For the digital sinusoidal signal value corresponding to phase initial value and surplus, signal value is calculated to produce with differenceization product formula
Raw digital sinusoidal signal.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, various other advantages and benefit are common for this field
Technical staff will become clear.Attached drawing only for the purpose of illustrating preferred embodiments, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.Wherein in the accompanying drawings, reference number
Alphabetic flag later indicates that multiple identical components will omit its last alphabetic flag when referring to these components.Attached
In figure：
Fig. 1 show the structure diagram of existing Direct Digital Synthesizer；
Fig. 2 is the flow chart of one embodiment of the method for the generation digital sinusoidal signal of the present invention；
Fig. 3 show the schematic diagram of one embodiment of the device of the generation digital sinusoidal signal of the present invention；
Fig. 4 is divided subinterval schematic diagram by the present invention's.
In the accompanying drawings, same or similar element is referred to using same or similar label.
Specific implementation mode
Carry out detailed description of the present invention illustrative embodiments with reference to the drawings.It should be appreciated that shown in attached drawing and
The embodiment of description is only exemplary, it is intended that is illustrated the principle and spirit of the invention, and is not limited the model of the present invention
It encloses.
Fig. 2 is the flow chart of one embodiment 200 of the method for the generation digital sinusoidal signal of the present invention.Embodiment 200
It can comprise the following steps 201 to 205.
In step 201, the phase interval of digital sinusoidal signal is divided into multiple first subintervals.
In order to save the memory space of ROM, usually can according to SIN function between each quadrant corresponding relationship, only
The range value corresponding to the sin cos functions phase of first quartile is stored in ROM domestic demands.Therefore, number described in this step is being just
The phase interval of string signal can be the range of first quartile, i.e.,：Phase value is from 0 to pi/2.
In one embodiment of the invention, 0 to pi/2 phase interval can be divided into multiple first sub-districts
Between.As shown in figure 4,0 to pi/2 phase interval can be divided into 8 the first subintervals, each small fan in Fig. 4
Shape represents the range in first subinterval.
In step 202, each in multiple first subintervals is divided into multiple second subintervals.
For each first subinterval marked off by step 201, can also be divided further into multiple
Second subinterval.For example, each the first subinterval can be divided into 8 the second subintervals.
In step 203, each in multiple second subintervals is divided into multiple third subintervals.
For each second subinterval marked off by step 202, can also be divided further into multiple
Third subinterval.For example, each the second subinterval can be divided into 16 third subintervals.
In one embodiment of the invention, the number in the third subinterval in second subinterval could be provided as both
Not less than the total sum nor less than the first subinterval in the second subinterval.For example, if the sum in the first subinterval is k,
The number in the second subinterval in one the first subinterval is m, then the number n in the third subinterval in second subinterval can
To be divided into n >=k and n >=m.
In step 204, the first subinterval institute phase value of digital sinusoidal signal to be generated being expressed as where it
Phase initial value corresponding to phase initial value, third subinterval corresponding to corresponding phase initial value, the second subinterval with
The sum of surplus.
For the phase value of an arbitrary digital sinusoidal signal, the first subinterval institute where being expressed as it is right
Phase initial value corresponding to the phase initial value answered, the second subinterval, the phase initial value corresponding to third subinterval with it is surplus
The sum of surplus.By taking the segmentation number in the subintervals at different levels illustrated in above-mentioned steps as an example, for a phase valueIt can indicate
ForWherein,Indicate phase valuePhase corresponding to first subinterval at place
Position initial value；Indicate phase valuePhase initial value corresponding to second subinterval at place；Indicate phase valuePhase initial value corresponding to the third subinterval at place；D indicates remaining
Amount, d ＜ (pi/2/8/8)/16.
In step 205, the digital sinusoidal signal value corresponding to phase initial value and surplus, it is public with being accumulated with differenceization
Formula calculates signal value to generate digital sinusoidal signal.
It can utilize and differenceization product formula will need the digital sinusoidal signal value generated
It is launched into useWith the multinomial represented by the sine value of d, cosine value.Then it can inquire in ROM and deposit in advance
StorageSine value, cosine value and to the sine value of d, cosine value carry out approximate processing, to produce number
The sinusoidal signal of change.
So far the method according to the ... of the embodiment of the present invention for generating digital sinusoidal signal is described.
The present invention also provides the devices for generating digital sinusoidal signal.With reference to figure 3, Fig. 3 show the generation number of the present invention
The schematic diagram of one embodiment 300 of the device of word sinusoidal signal.Device 300 may include：First subinterval division module
301, for the phase interval of digital sinusoidal signal to be divided into multiple first subintervals；Second subinterval division module
302, for each in multiple first subintervals to be divided into multiple second subintervals；Third subinterval division module 303,
For each in multiple second subintervals to be divided into multiple third subintervals；Phase value decomposing module 304, for that will wait for
The phase value of the digital sinusoidal signal of generation is expressed as phase initial value, the second sub-district corresponding to the first subinterval where it
Between the sum of corresponding phase initial value, the phase initial value corresponding to third subinterval and surplus；And range value calculates
Module 305 calculates letter for the digital sinusoidal signal value corresponding to phase initial value and surplus with differenceization product formula
Number value is to generate digital sinusoidal signal.
In one embodiment of the invention, the number in the third subinterval in second subinterval can both be not less than
Sum of the sum in the second subinterval nor less than the first subinterval.
So far the device according to the ... of the embodiment of the present invention for generating digital sinusoidal signal is described.
Table 1 below illustrates the total k in the first subinterval, the number in the second subinterval in first subinterval is
The number n in the third subinterval in m and second subinterval be equal in the case of signal errors.
Table 1
| Phase shares at different levels | Sin mean square errors | Sin absolute errors |
| 2 | 0.0036 | 0.02 |
| 4 | 5.8553e-5 | 5e-4 |
| 8 | 1.0041e-6 | 5e-6 |
| 16 | 1.4320e-8 | 1e-7 |
Following table 2 shows the pass between the division number and signal errors in the subintervals at different levels by actual test
System.
Table 2
| Phase shares (k, m, n) at different levels | Sin mean square errors | Sin absolute errors |
| (2,2,1) | 0.0157 | 0.1 |
| (4,4,2) | 9.2805e-3 | 5e-3 |
| (8,8,4) | 5.8553e-5 | 5e-4 |
| (16,16,8) | 1.0041e-6 | 5e-6 |
| (1,2,2) | 0.0036 | 0.02 |
| (2,4,4) | 5.8553e-5 | 5e-4 |
| (4,8,8) | 1.0041e-6 | 5e-6 |
| (8,16,16) | 1.4320e-8 | 1e-7 |
| (2,1,2) | 0.0036 | 0.02 |
| (4,2,4) | 5.8553e-5 | 5e-4 |
| (8,4,8) | 1.0041e-6 | 5e-6 |
| (16,8,16) | 1.4320e-8 | 1e-7 |
Wherein, k is the sum in the first subinterval, and m is the number in the second subinterval in first subinterval, n mono-
The number in the third subinterval in a second subinterval.
Tables 1 and 2 is compared it is found that when dividing the number in subintervals at different levels, when third in second subinterval
The number in section is more and when the number in the second subinterval in first subinterval and the less sum in the first subinterval, both
Memory space can be saved, and can make that signal errors is smaller, precision is higher.For example, the number in subinterval at different levels is divided into table 2
When (8,16,16) or (16,8,16), subintervals at different levels are all being divided into 16 just in the error and table 1 of the sinusoidal signal generated
String signal error is almost the same, but according to the point-score of (8,16,16) or (16,8,16), can significantly save memory space.
Claims (4)
1. a kind of method generating digital sinusoidal signal, including：
The phase interval of digital sinusoidal signal is divided into multiple first subintervals；
Each in the multiple first subinterval is divided into multiple second subintervals；
Each in the multiple second subinterval is divided into multiple third subintervals；
The phase value of digital sinusoidal signal to be generated is expressed as phase initial value corresponding to the first subinterval where it,
The sum of phase initial value corresponding to phase initial value, third subinterval and surplus corresponding to second subinterval；And
According to the digital sinusoidal signal value corresponding to three phase initial values and surplus, signal value is calculated with differenceization product formula
To generate digital sinusoidal signal.
2. according to the method described in claim 1, it is characterized in that, the number in the third subinterval in second subinterval is neither
Less than the total sum nor less than the first subinterval in the second subinterval in first subinterval.
3. a kind of device generating digital sinusoidal signal, characterized in that including：
First subinterval division module, for the phase interval of digital sinusoidal signal to be divided into multiple first subintervals；
Second subinterval division module, for each in the multiple first subinterval to be divided into multiple second sub-districts
Between；
Third subinterval division module, for each in the multiple second subinterval to be divided into multiple third sub-districts
Between；
Phase value decomposing module, the first subinterval for being expressed as the phase value of digital sinusoidal signal to be generated where it
Phase initial value corresponding to corresponding phase initial value, the second subinterval, the phase initial value corresponding to third subinterval
The sum of with surplus；And
Range value computing module, for digital sinusoidal signal value corresponding to three phase initial values and surplus, with
Differenceization product formula calculates signal value to generate digital sinusoidal signal.
4. device according to claim 3, characterized in that the number in the third subinterval in second subinterval is neither
Less than the total sum nor less than the first subinterval in the second subinterval in first subinterval.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5815045A (en) * | 1995-08-21 | 1998-09-29 | Fujitsu Limited | Oscillation apparatus |
| EP0963075A2 (en) * | 1998-06-02 | 1999-12-08 | Victor Company Of Japan, Ltd. | Clock signal producing device |
| CN103580690A (en) * | 2012-07-24 | 2014-02-12 | 深圳格兰泰克科技有限公司 | Non-integral power of 2 digital sine and cosine frequency synthesizer and non-integral power of 2 digital sine and cosine frequency synthesis method |
| CN103901940A (en) * | 2014-03-26 | 2014-07-02 | 电子科技大学 | Method for generating digital cosine signals |
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2016
- 2016-04-21 CN CN201610250784.2A patent/CN105932966B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5815045A (en) * | 1995-08-21 | 1998-09-29 | Fujitsu Limited | Oscillation apparatus |
| EP0963075A2 (en) * | 1998-06-02 | 1999-12-08 | Victor Company Of Japan, Ltd. | Clock signal producing device |
| CN103580690A (en) * | 2012-07-24 | 2014-02-12 | 深圳格兰泰克科技有限公司 | Non-integral power of 2 digital sine and cosine frequency synthesizer and non-integral power of 2 digital sine and cosine frequency synthesis method |
| CN103901940A (en) * | 2014-03-26 | 2014-07-02 | 电子科技大学 | Method for generating digital cosine signals |
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