CN105930155B - A kind of method for visualizing of computer instruction implementation procedure - Google Patents
A kind of method for visualizing of computer instruction implementation procedure Download PDFInfo
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- CN105930155B CN105930155B CN201610244997.4A CN201610244997A CN105930155B CN 105930155 B CN105930155 B CN 105930155B CN 201610244997 A CN201610244997 A CN 201610244997A CN 105930155 B CN105930155 B CN 105930155B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/451—Execution arrangements for user interfaces
Abstract
The present invention relates to a kind of method for visualizing of computer instruction implementation procedure, belong to data calculation process visualization field.The display page is divided into memory field, central processing unit area, input area and viewing area first by the method for the present invention；Host divides into memory field and hard disk area；Address bus, control bus and data/address bus are set between memory field and central processing unit area；Code area, data field, data register area, address register area are set in memory field；In central processing unit area, program counter area, command register area, controller area etc. are set.Input area setting first operand input area, second operand input area determine control etc..Then an addition instruction is executed by simulation, dynamically shows storage position and the data flow of the data that each step obtains, realizes the visualization of computer instruction implementation procedure.The method of the present invention is conducive to computer learning person and understands computer instruction implementation procedure faster.
Description
Technical field
The present invention relates to a kind of method for visualizing of computer instruction implementation procedure, belong to data calculation process visualization neck
Domain.
Background technique
The working method of computer depends on its three basic element of character: memory, controller and arithmetic unit.These three portions
Part makes computer tool there are two basic capacity: first is that can storing data and program, second is that program can be automatically carried out.And
It with computer Solve problems and can obtain satisfied as a result, then depending on the correct and superiority and inferiority of program.Program is instruction
Gather, the process instructed in the execution program of computer in cycles exactly executes the process of program.But computer instruction is being counted
How to be executed inside calculation machine, most people is not known about simultaneously.Therefore, in Computer Basic Knowledge teaching process, need by
This process visualization.At present in existing document, the correlation of the visualization process of computer instruction implementation procedure is not found also
Data.
The present invention relates to prior art are as follows:
The execution of instruction: instruction is usually made of operation code and operand two parts.Operation code indicates the function of the instruction,
Such as it is operation or logical operation, is stored in command register.Operand indicates to instruct data or data place to be processed
Address.Whole instruction is stored in memory in the form of binary-coded.The execution of one instruction can be divided into three ranks
Section: instruction fetch, decoding and execution.
Summary of the invention
The purpose of the present invention is to propose to a kind of method for visualizing of computer instruction implementation procedure.
The purpose of the present invention is what is be achieved through the following technical solutions.
A kind of method for visualizing of computer instruction implementation procedure, concrete operation step are as follows:
Step 1: the display page is divided into memory field (RAM), central processing unit area (CPU), input area and viewing area.Host
Divide into memory field and hard disk area.It is total that address bus, control bus and data are set between memory field and central processing unit area
Line.Code area, data field, data register area, address register area are set in memory field.In central processing unit area, journey is set
Sequence counter area, command register area, controller area, the first general register area, the second general register area and arithmetical logic
Unit.Input area setting first operand input area, second operand input area determine control, instruction fetch control, Instruction decoding
Control, access are according to control, additional calculation control and resetting control.
Step 2: prepositioned instruction address in the program counter area in central processing unit area, described instruction address correspond to memory field
Code area a certain address, indicated with symbol A.The preset addition instruction of address A in the code area of memory field.
Step 3: inputting two decimal systems respectively in the first operand input area of input area and second operand input area
Integer.
Step 4: clicking and determine control, first operand and second operand are converted into binary integer and in input area
Display；Meanwhile the binary integer of first operand and second operand being shown in the data field of memory field.
Step 5: clicking instruction fetch control, IA preset in the program counter area in central processing unit area is passed through
Address bus is transferred to the address register area of memory field；Then the addition instruction is taken out from the address A of memory field to be shown in
The data register area of memory field；The addition instruction is passed through into the order register of data bus transmission to central processing unit area again
Device area.The data moving process of the step is presented by arrow animation.
Step 6: click commands decode control, in the addition instruction in the command register area in the central processing unit area
First 4 are shown in the controller area in central processing unit area.The data reproduction process of the step is presented by animation.
Step 7: click access according to control, the in the addition instruction in the command register area in the central processing unit area
5 to the 10th are transmitted to the address register area of memory field by address bus, and the 5th to the 10th in the addition instruction
Position indicates that first operand in the address of the data field of memory field, is indicated with symbol B；It will be in the data field of memory field in the B of address
Data be shown in the data register area of memory field；Data in the data register area of memory field are passed by data/address bus
It transports in the first general register area in central processing unit area.The data moving process of the step is in by arrow animation
It is existing.
Step 8: clicking access again according to control, in the addition instruction in the command register area in the central processing unit area
11st to the 16th is transmitted to the address register area of memory field by address bus, and the 11st in the addition instruction is extremely
16th expression second operand is indicated in the address of the data field of memory field with symbol C；By address in the data field of memory field
Data in C are shown in the data register area of memory field；Data in the data register area of memory field are total by data
Line is transmitted in the second general register area in central processing unit area.The data moving process of the step passes through arrow animation
It presents.
Step 9: additional calculation control is clicked, by the first general register area in central processing unit area and the second general deposit
Data in device area are transmitted separately to arithmetic logic unit, and after add operation, the results are shown in central processing unit areas
First general register area.Meanwhile calculated result is shown in input area.The data moving process of the step is presented by animation.
The visualization of computer instruction implementation procedure can be completed in operation through the above steps.
Beneficial effect
The display page is divided into memory field by a kind of method for visualizing of computer instruction implementation procedure proposed by the present invention
(RAM), central processing unit area (CPU), input area and viewing area, and each subregion is further segmented, and pass through flash demo
The implementation procedure of instruction is realized into visualization on the display page.The method of the present invention is conducive to computer learning person and understands faster
The implementation procedure of computer instruction.
Detailed description of the invention
Fig. 1 is the display page schematic diagram in the specific embodiment of the invention after the completion of step 2 operation；
Fig. 2 is the display page schematic diagram in the specific embodiment of the invention after the completion of step 4 operation；
Fig. 3 is the display page schematic diagram in the specific embodiment of the invention after the completion of step 5 operation；
Fig. 4 is the display page schematic diagram in the specific embodiment of the invention after the completion of step 6 operation；
Fig. 5 is the display page schematic diagram in the specific embodiment of the invention after the completion of step 7 operation；
Fig. 6 is the display page schematic diagram in the specific embodiment of the invention after the completion of step 8 operation；
Fig. 7 is the display page schematic diagram in the specific embodiment of the invention after the completion of step 9 operation.
Specific embodiment
According to the above technical scheme, the present invention is described in detail with embodiment with reference to the accompanying drawing.
In this example, realize that an addition refers to using the method for visualizing of computer instruction implementation procedure proposed by the present invention
It enables the virtual interacting of implementation procedure test to show, specific steps are as follows:
Step 1: the display page is divided into memory field (RAM), central processing unit area (CPU), input area and viewing area.Host
Divide into memory field and hard disk area.It is total that address bus, control bus and data are set between memory field and central processing unit area
Line.Code area, data field, data register area, address register area are set in memory field.In central processing unit area, journey is set
Sequence counter area, command register area, controller area, the first general register area, the second general register area and arithmetical logic
Unit.Input area setting first operand input area, second operand input area determine control, instruction fetch control, Instruction decoding
Control, access are according to control, additional calculation control and resetting control.
Step 2: prepositioned instruction address in the program counter area in central processing unit area: 0,000 0,000 00001010.Institute
The a certain address that IA corresponds to the code area of memory field is stated, is indicated with symbol A.Address A is pre- in the code area of memory field
Set an addition instruction: 0,001 1,101 0,011 0110, as shown in Figure 1.
Step 3: inputting two decimal systems respectively in the first operand input area of input area and second operand input area
Integer 1 and 2.
Step 4: clicking and determine control, first operand and second operand are converted into binary integer and in input area
Display；Meanwhile showing the binary integer of first operand and second operand in the data field of memory field, as shown in Figure 2.
Step 5: clicking instruction fetch control, IA preset in the program counter area in central processing unit area is passed through
Address bus is transferred to the address register area of memory field；Then the addition instruction is taken out from the address A of memory field to be shown in
The data register area of memory field；The addition instruction is passed through into the order register of data bus transmission to central processing unit area again
Device area.The data moving process of the step is presented by arrow animation, as shown in Figure 3.
Step 6: click commands decode control, in the addition instruction in the command register area in the central processing unit area
First 4 are shown in the controller area in central processing unit area.The data reproduction process of the step is presented by animation, such as Fig. 4 institute
Show.
Step 7: click access according to control, the in the addition instruction in the command register area in the central processing unit area
5 to the 10th are transmitted to the address register area of memory field by address bus, and the 5th to the 10th in the addition instruction
Position indicates that first operand in the address of the data field of memory field, is indicated with symbol B；It will be in the data field of memory field in the B of address
Data be shown in the data register area of memory field；Data in the data register area of memory field are passed by data/address bus
It transports in the first general register area in central processing unit area.The data moving process of the step is in by arrow animation
It is existing, as shown in Figure 5.
Step 8: clicking access again according to control, in the addition instruction in the command register area in the central processing unit area
11st to the 16th is transmitted to the address register area of memory field by address bus, and the 11st in the addition instruction is extremely
16th expression second operand is indicated in the address of the data field of memory field with symbol C；By address in the data field of memory field
Data in C are shown in the data register area of memory field；Data in the data register area of memory field are total by data
Line is transmitted in the second general register area in central processing unit area.The data moving process of the step passes through arrow animation
It presents, as shown in Figure 6.
Step 9: additional calculation control is clicked, by the first general register area in central processing unit area and the second general deposit
Data in device area are transmitted separately to arithmetic logic unit, and after add operation, the results are shown in central processing unit areas
First general register area.Meanwhile calculated result is shown in input area.The data moving process of the step is presented by animation,
As shown in Figure 7.
The visualization of computer instruction implementation procedure can be completed in operation through the above steps.
Although the embodiments of the invention are described in conjunction with the attached drawings, it will be apparent to those skilled in the art that not taking off
Under the premise of from the principle of the invention, several improvement can also be made, these also should be regarded as belonging to the scope of protection of the present invention.
Claims (1)
1. a kind of method for visualizing of computer instruction implementation procedure, it is characterised in that: its concrete operation step are as follows:
Step 1: the display page is divided into memory field, central processing unit area, input area and viewing area；In memory field and central processing
Address bus, control bus and data/address bus are set between device area；Code area, data field, data register are set in memory field
Device area, address register area；Lead in setting program counter area of central processing unit area, command register area, controller area, first
With register section, the second general register area and arithmetic logic unit；First operand input area, the second operation is arranged in input area
Number input area determines control, instruction fetch control, Instruction decoding control, access according to control, additional calculation control and resetting control；
Step 2: prepositioned instruction address in the program counter area in central processing unit area, described instruction address correspond to the generation of memory field
The a certain address in code area, is indicated with symbol A；The preset addition instruction of address A in the code area of memory field；
Step 3: inputting two decimal integers respectively in the first operand input area of input area and second operand input area；
Step 4: clicking and determine control, first operand and second operand are converted into binary integer and shown in input area
Show；Meanwhile the binary integer of first operand and second operand being shown in the data field of memory field；
Step 5: clicking instruction fetch control, IA preset in the program counter area in central processing unit area is passed through into address
Address register area of the bus transfer to memory field；Then the addition instruction is taken out from the address A of memory field be shown in memory
The data register area in area；The addition instruction is passed through into the command register of data bus transmission to central processing unit area again
Area；The data moving process of the step is presented by arrow animation；
Step 6: click commands decode control, preceding 4 in addition instruction in the command register area in the central processing unit area
Position is shown in the controller area in central processing unit area；The data reproduction process of the step is presented by animation；
Step 7: the 5th in addition instruction for clicking access according to control, in the command register area in the central processing unit area
It is transmitted to by address bus the address register area of memory field to the 10th, the 5th to the 10th in the addition instruction
Indicate that first operand in the address of the data field of memory field, is indicated with symbol B；It will be in the data field of memory field in the B of address
Data are shown in the data register area of memory field；Data in the data register area of memory field are passed through into data bus transmission
Into the first general register area in central processing unit area；The data moving process of the step is presented by arrow animation；
Step 8: the 11st in addition instruction for clicking access again according to control, in the command register area in the central processing unit area
Position is transmitted to by address bus the address register area of memory field to the 16th, and the 11st to the 16th in the addition instruction
Position indicates that second operand in the address of the data field of memory field, is indicated with symbol C；It will be in the data field of memory field in the C of address
Data be shown in the data register area of memory field；Data in the data register area of memory field are passed by data/address bus
It transports in the second general register area in central processing unit area；The data moving process of the step is in by arrow animation
It is existing；
Step 9: additional calculation control is clicked, by the first general register area and the second general register area in central processing unit area
In data be transmitted separately to arithmetic logic unit, after add operation, the results are shown in the first of central processing unit area
General register area；Meanwhile calculated result is shown in input area；The data moving process of the step is presented by animation；
The visualization of computer instruction implementation procedure can be completed in operation through the above steps.
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| CN201610235677 | 2016-04-15 | ||
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| US20080195843A1 (en) * | 2007-02-08 | 2008-08-14 | Jaya 3D Llc | Method and system for processing a volume visualization dataset |
| US20110227925A1 (en) * | 2010-03-16 | 2011-09-22 | Imb Corporation | Displaying a visualization of event instances and common event sequences |
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| CN2495004Y (en) * | 2001-02-23 | 2002-06-12 | 清华同方股份有限公司 | Experimental facility for computer composition principle |
| CN1434378A (en) * | 2003-02-25 | 2003-08-06 | 汕头市龙湖区汕龙电子有限公司 | Method and device for activating toy by computer instruction |
| CN104866628A (en) * | 2015-06-16 | 2015-08-26 | 长沙万商云信息技术有限公司 | Efficient uncoordinated selectivity big data analysis method and system performed by computer instruction |
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