CN105930132A - Coprocessor - Google Patents
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- CN105930132A CN105930132A CN201610143284.9A CN201610143284A CN105930132A CN 105930132 A CN105930132 A CN 105930132A CN 201610143284 A CN201610143284 A CN 201610143284A CN 105930132 A CN105930132 A CN 105930132A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
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Abstract
The invention discloses a coprocessor, including a PTP engine and a PTP transceiver module. The PTP engine includes an event source processing arbiter and a protocol coprocessor. The PTP transceiver module includes a PTP transmitting processing module and a PTP receiving processing module. The event source processing arbiter is configured with a corresponding relation between an event source and a program segment. The protocol coprocessor is used for executing a plurality of commands. The PTP transmitting processing module has an interface and module capable of use for the protocol coprocessor to access and an interface and module capable of use for an external CPU interface to access. The PTP receiving processing module has an interface and module capable of use for the protocol coprocessor to access. The invention makes up the shortcoming of the waste of external CPU resources in the prior art, effectively integrates various sources driven by the coprocessor through a CAM by using the command design of the protocol coprocessor, and completes the processing analysis and calculation of protocol control frames in a flexible manner of CAM configuration and coprocessor programming.
Description
Technical field
The present invention relates to a kind of coprocessor, more specifically, be about in communication, Protocol Control frame processes occasion under, a design using the general coprocessor dividing multi-segment program section with CAM.
Background technology
Existing accurate clock synchronization protocol includes the PTP protocol such as IEEE1588 and 802.1as (Precise Time Protocol, precision clock agreement).The feature of this quasi-protocol is that frame flow is smaller as Protocol Control frame, but the type of control frame is more, and include certain algorithm needs calculating to process simultaneously.One common practice is CPU (the Central Processing Unit outside needs, central processing unit) perform order, process the analysis of frame, the calculating of algorithm, framings etc. process, although the disposal ability of outer CPU typically ratio is more aggressive, but is because there is interface I/O (Input/Output, input/output) the operation of more relatively slow-response, the outside valuable cpu resource of significant wastage.Another kind of generally way is use local cpu in PTP protocol module, such as MIPS or ARM, as coprocessor, in addition to commercial CPU needs to authorize, also have because commercial CPU emphasis is the design such as streamline and efficiency, the general instruction having complexity, so resource occupation is more, is to resources of chip great waste the most in fact；The most common coprocessor, performing instruction to trigger has interruption and the conventional mode such as inquiry but not peripheral module, it has to as protocol processor when, periphery design is added more module and coordinated the work such as interruption.
Summary of the invention
The technical problem to be solved in the present invention is to overcome the prior art defect to the wasting of resources, it is provided that a kind of coprocessor.
The present invention is to solve above-mentioned technical problem by the following technical programs:
The present invention provides a kind of coprocessor, is characterized in, including: PTP protocol engine and PTP transceiver module；
Described PTP protocol engine includes: event source processes moderator and agreement coprocessor, and described PTP transceiver module includes: PTP sends processing module and PTP receiving processing module；
Described event source processes moderator and is configured with the corresponding relation of event source and program segment, for CAM input for event source, performs the program segment corresponding with the CAM hit, the base address of the index address instruction program section of the CAM of hit；
Described agreement coprocessor is used for performing some instructions；
Described PTP sends processing module to be possessed and is available for interface and module that described agreement coprocessor accesses and is available for interface and the module of outer CPU interface accessing；
Described PTP receiving processing module possesses interface and the module being available for the access of described agreement coprocessor.
CAM (Content Addressable Memory, Content Addressable Memory) whether hit usually used as to the special domain (content) of frame, filter out the frame of needs, the conversion of frame field domain, such as conversion of overall situation port port numbers and local port port numbers etc. work can also be done by the relation of content and address.Described PTP sends processing module and described PTP receiving processing module can be configured flexibly and revise.The technical program is to CAM brand-new derivative application, the feature processed based on Protocol Control frame, trigger using the hit of CAM as program segment, effectively event source and the program of Protocol Control frame are performed section and combine, and keep event source and program to perform the configurability of section most possibly, reduce resources of chip.The present invention is in addition to needs outer CPU initializes, in normal work process, completely by coprocessor self processing protocol control frame, it is achieved that protocol processor is the complete offload of host CPU (removing load).
It is preferred that described instruction includes one or more given an order:
Program segment tail indicator: for managing execution address location and the internal state control bit of program；
Look into CAM instruction: for configuring the CAM of CAM input hit；
Reading instruction；
Write command；
Add instruction；
Subtract instruction；
Do-nothing instruction.
It is preferred that the module being available for the access of described agreement coprocessor includes sending frame configuration RAM, transmission task FIFO and one or more sent in return FIFO；
And/or, the module being available for outer CPU interface accessing includes sending frame configuration RAM；
And/or, the module being available for the access of described agreement coprocessor includes one or more in reception task FIFO, reception frame buffer and PTP filtering frames module.
It is preferred that described PTP protocol engine also includes bus selector, described agreement coprocessor sends processing module with described PTP respectively by described bus selector and described PTP receiving processing module is connected.
It is preferred that described coprocessor also includes that frame pretreatment module, described PTP receiving processing module are connected with ethernet mac by described frame pretreatment module.
It is preferred that described PTP sends processing module also provides for the pretreatment module adaptive with ethernet mac.
It is preferred that described PTP transceiver module also includes timestamp (Timestamp) generator, described time stamp generator sends processing module with described PTP respectively and described PTP receiving processing module is connected, to provide timestamp.
It is preferred that described event source includes: at least one time counter, receipts frame and a frame interrupt, program segment tail looks into CAM event.
It is preferred that described instruction is micro-code instruction.
It is preferred that described coprocessor uses 72 micro-code instructions and assembler directive based on described micro-code instruction.
On the basis of meeting common sense in the field, above-mentioned each optimum condition, can combination in any, obtain the preferred embodiments of the invention.
The most progressive effect of the present invention is: the present invention utilizes the instruction of agreement coprocessor to design, particularly look into CAM instruction, the source various coprocessors driven by CAM is effectively integrated, by this framework, Treatment Analysis and the calculating of Protocol Control frame can be completed in the mode flexibly of CAM configuration and coprocessor programming: this framework in the module that PTP protocol processes as coprocessor, can be configured by CAM and assist process Programming Design equipment master (main equipment) and the application of slave (from equipment) on same hardware.
The present invention acts not only as the coprocessor of PTP protocol, it is also possible to the coprocessor as other non-traffic class control protocol uses.The application example configuring out on the use of PTP protocol simply this framework.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of embodiment of the present invention coprocessor.
Fig. 2 is that the function of the CAM of the present invention derives schematic diagram.
Fig. 3 is the flow chart of example 1PTP master time calibration function of the present invention.
Fig. 4 is the flow chart of example 2PTP slave time calibration function of the present invention.
Detailed description of the invention
Further illustrate the present invention below by the mode of embodiment, but the most therefore limit the present invention among described scope of embodiments.
Embodiment
As it is shown in figure 1, a kind of coprocessor includes: PTP protocol engine 1, PTP transceiver module 2 and frame pretreatment module 3.
Described PTP protocol engine includes: event source processes moderator 101, agreement coprocessor 102 and bus selector 103.
Described event source processes moderator and is configured with the corresponding relation of event source and program segment, for CAM input for event source, performs the program segment corresponding with the CAM hit, the base address of the index address instruction program section of the CAM of hit.
Described agreement coprocessor is used for performing some instructions, and described instruction is micro-code instruction.Described micro-code instruction includes one or more given an order:
Program segment tail indicator: for managing execution address location and the internal state control bit of program；
Look into CAM instruction: for configuring the CAM of CAM input hit；
Reading instruction；
Write command；
Add instruction；
Subtract instruction；
Do-nothing instruction.
Wherein, program segment tail instruction order can perform address location to program and internal state control bit does and effectively manages so that each program segment completes independent work；Look into the special return register r6 that input is protocol processor of CAM Command design CAM, namely this CAM input can process programming oneself by association and determine, such as can be from certain field domain of the frame received after acquisition information, determine the input source of CAM order, the hit of CAM be also one configurable, the index address of the CAM of hit is as an instruction of program segment, the result of CAM hit be trigger new program segment (if new program segment or the same with old program segment, be exactly nested execution, be also to support) execution.
Described PTP transceiver module includes: PTP sends processing module 201, PTP receiving processing module 202 and time stamp generator 203.
Described PTP sends processing module to be possessed and is available for interface and module that described agreement coprocessor accesses and is available for interface and the module of outer CPU interface accessing.Wherein, the module being available for the access of described agreement coprocessor includes sending frame configuration RAM (Random Access Memory, random access memory), transmission task FIFO (First In First Out FIFO caching) and one or more sent in return FIFO；The module being available for outer CPU interface accessing includes sending frame configuration RAM, send frame configuration RAM initialized time, simply configured the basic format of various types of transmission control frame by outer CPU, send frame configuration RAM the most simultaneously, support that coprocessor accesses amendment.Described PTP sends processing module and also provides for the pretreatment module adaptive with ethernet mac (Medium Access Control, media interviews control).
Described PTP receiving processing module possesses interface and the module being available for the access of described agreement coprocessor.Wherein, the module being available for the access of described agreement coprocessor includes one or more in reception task FIFO, reception frame buffer and PTP filtering frames module.Wherein, PTP filtering frames module is to need the frame of frame to be processed, such as IEEE1588 to filter out described protocol processor from substantial amounts of network frame.
Described PTP receiving processing module is connected with ethernet mac by described frame pretreatment module.
Described time stamp generator sends processing module with described PTP respectively and described PTP receiving processing module is connected, to provide timestamp.
Described agreement coprocessor sends processing module with described PTP respectively by described bus selector and described PTP receiving processing module is connected.Described bus selector uses 32 bit bus.
The coprocessor of the present embodiment is looked into " address " " content " on ordinary meaning and is derived and look into " instruction program fragment position " for " event source ", as shown in Figure 2, described event source includes: at least one time counter, receipts frame and a frame interrupt, program segment tail looks into CAM event: the action with time interval can be triggered in the event source of (1) multiple time counter, such as Fixed Time Interval send out certain format control frame, the more such as set time need to do certain algorithm；(2) receive and send the interruption routine after frame completes and also can be called by CAM；(3) can configure the program segment tail of enable by coprocessor to look into CAM event and complete the function calling execution (including nesting) of program segment, namely program segment tail looks on CAM event form one of the order being a CAM order and processing as association, the nesting of processing routine section and calling.Because the execution of the event source of design " program segment tail looks into CAM event " and non-" program segment tail looks into CAM event " all energy trigger sections, so can be configured by coprocessor programming and CAM, some states (such as time counter of combined with hardware, interrupt etc.), complete the combinative movement of complexity neatly.
In order to further illustrate the coprocessor of the present embodiment, explanation uses the coprocessor of the present embodiment to realize the method driving multi-segment program section based on CAM the most by way of example, and described coprocessor uses 72 micro-code instructions and assembler directive based on described micro-code instruction.Referring specifically to the instruction processed according to association of the instruction of table 1 and the explanation of the domain of instruction of table 2 and table 3 by the assembler directive of software design (namely oneself design one simplifies compiler) and explanation.
Table 1
Table 2
Table 3
| Assembler directive | Operation |
| e_vrd{seg_id rc addr} | Rc [31:0]=rdata [addr] |
| e_vrd_15to0{seg_id rc addr} | Rc [15:0]=rdata [addr] |
| e_vrd_47to16{seg_id rc addr} | Rc [47:16]=rdata [addr] |
| e_vrd_79to48{seg_id rc addr} | Rc [79:48]=rdata [addr] |
| e_vwe{seg_id addr be wdata} | The data write are wdata |
| e_vwe_add{seg_id addr be wdata ra} | The data write are wdata+ra |
| e_add{seg_id rc rb ra} | Rc=ra+rb |
| e_sub{seg_id rc rb ra} | Rc=ra-rb |
| e_cam{seg_id} | Inquiry CAM, obtains next program segment |
| e_end{seg_id} | Last order of each program segment |
| e_nop{seg_id} | Do-nothing operation |
The master of example 1:PTP function time calibration
In IEEE1588 agreement, the function of master is the most, the present invention lifts the example of a time calibration, other function can be analogized, relevant function has: (1) sends Sync frame (synchronization frame), writes down the delivery time t1 at physical interface and when sending Sync frame, t1 is write the timestamp timestamp territory of this frame；(2) Delay Req frame (latency request frame) is received, and send Delay_Resp frame (delay response frame), write down the moment t4 at the physical interface receiving Delay Req frame and t4 write the timestamp territory of this frame sending Delay_Resp frame when.
In order to complete above-mentioned relevant function, example 1 can so process:
1, the configuration design sending Sync frame is as follows: the basic format of (1) configuration Sync frame is to sending (corresponding Sync frame position in RAM, depositor indicate base address) in frame configuration RAM；(2) enumerator setup time timer1 is the time interval of Sync frame；(3), when the address of configuration CAM is 2, content is 0x04, wherein content 0x04 correspondence timer1, and CAM address 2 is the base address of program segment 2；(4) program of program segment 2 includes specifying the base address that send frame configuration RAM Sync frame place corresponding with (1st) step to coprocessor register, obtain the serial number SEQ_ID sent in frame configuration RAM Sync frame, and SEQ_ID writes original position after adding 1, Sync frame is written to transmission task FIFO in the base address sending frame configuration RAM, triggers the transmission of Sync frame.
Lower flow process is said below with time sequencing, as it is shown on figure 3, when time counter timer1 count down to, triggering CAM inquiry, because there being configuration above, thus seeking program segment 2, execution phase 2, Sync frame is sent.Wherein write down the moment t1 of physical interface and when sending Sync frame, t1 write the timestamp territory of this frame.
2, receive Delay Req frame, and it is as follows to send Delay Resp configuration: the basic format of (1) configuration Delay Resp frame goes to (corresponding Delay Resp frame position in RAM, depositor indicate base address) to sending frame configuration RAM；(2) when the address of configuration CAM is 0, content is 0x01, and wherein content 0x01 correspondence receives frame interruption, and CAM address 0 is the base address of program segment 0；(3) configure the address of CAM when being 6 simultaneously, content is 0x11, wherein the highest order of content 0x11 effectively shows that " the event source " of this CAM comes from 11 to 8 these 4 results of the general depositor r6 of coprocessor, programming below can be written as receiving the frame format type MSG_TYPE of frame, in this application, because receive is Delay Req frame, according to IEEE1588 agreement, therefore MSG_TYPE is 1, being combined with highest significant position is exactly content 0x11, and CAM address 6 is the base address of program segment 6；(4) program of program segment 0 includes reading the base address of this reception Delay Req frame during receiving frame buffer from task FIFO of reception, MSG_TYPE to 11 of coprocessor specified register r6 to 8 is obtained plus side-play amount by Delay Req frame base address, initiation CAM lookup instructs, because configuration above, program segment 6 can be jumped to；null(5) program of program segment 6 includes specifying the base address sending frame configuration RAM Delay Resp frame，From the serial number SEQ_ID receiving frame buffer acquisition reception Delay Req frame,And this serial number SEQ_ID is written to send the corresponding serial number SEQ_ID territory of frame configuration RAM Delay Resp frame，From the timestamp t4 received when frame buffer acquisition Delay Req frame enters this chip makes physical layer, (this timestamp has ethernet mac module to be placed directly in the token head of frame，Token labelling is the privately owned field on the basis of each PTP control frame plus local module，So that local coprocessor processes)，Again in the timestamp territory of Delay Resp frame in this timestamp t4 write transmission frame configuration RAM obtained，Last coprocessor is written to transmission task FIFO Delay Resp frame in the base address sending frame configuration RAM，Trigger the transmission of Delay Resp frame.
Lower flow process is said below with time sequencing, as shown in Figure 3, when PTP receiving processing module receives Delay Req frame when, frame is placed in reception frame buffer, simultaneously this frame base address in receiving frame buffer is put in reception task FIFO, produce to receive and interrupt, cause the CAM analysis to event source, because configuration above, the first program of trigger section 0, by program segment 0 trigger section 6 again, program segment 6 finally triggers and Delay Resp frame is sent.
The slave of example 2:PTP function time calibration
In IEEE1588 agreement, the function of slave also compares many, but the present invention lifts the example of a time calibration, other function can be analogized, relevant thing has: (1) receives and synchronizes Sync frame, obtain the timestamp t1 in Sync and write down timestamp t2 at the physical interface receiving this frame, and triggering or the Sync frame of reception synchronization several times trigger and once send Delay Req frame, write down timestamp t3 at the physical interface of this Delay Req frame of transmission；(2) receive Delay Resp and postpone response frame, obtain the timestamp t4 in Delay Resp frame, simultaneously according to algorithm time calibration, there are t1, t2, t3, t4 calculates the time deviation of slave and master, in order to calibrate the clock of slave on the basis of master clock.
In order to complete above-mentioned relevant function, example 2 can so process:
1, receive synchronization Sync frame, and it is as follows to send Delay Req configuration: the basic format of (1) configuration Delay Req frame goes to (corresponding Delay Req frame position in RAM, depositor indicate base address) to " send frame and configure RAM "；(2) when the address of configuration CAM is 0, content is 0x01, and wherein content 0x01 correspondence receives frame interruption, and CAM address 0 is the base address of program segment 0；(3) configure the address of CAM when being 7 simultaneously, content is 0x10, wherein the highest order of content 0x10 effectively shows that " the event source " of this CAM comes from 11 to 8 these 4 results of the general depositor r6 of coprocessor, programming below can be written as receiving the frame format type MSG_TYPE of frame, in this application, because receive is Sync frame, according to IEEE1588 agreement, therefore MSG_TYPE is 0, being combined with highest significant position is exactly content 0x10, and CAM address 7 is the base address of program segment 7；(4) program of program segment 0 includes reading the base address of this reception Sync frame during receiving frame buffer from task FIFO of reception, MSG_TYPE to 11 of coprocessor specified register r6 to 8 is obtained plus side-play amount by Sync frame base address, initiation CAM lookup instructs, because configuration above, program segment 7 can be jumped to；null(5) program of program segment 7 includes obtaining the timestamp t1 (the t1 moment is the physical timestamp that master sends Sync frame) to general register r1 receiving Sync frame and the timestamp t2 (this timestamp has ethernet mac module to be placed directly in the token head of frame) to general register r2 from reception frame buffer obtains this frame reception entrance this chip makes physical layer interface time from reception frame buffer，Specify the base address sending frame configuration RAM Delay Req frame，From the serial number SEQ_ID receiving frame buffer acquisition reception Sync frame，And this serial number SEQ_ID is written to send the corresponding serial number SEQ_ID territory of frame configuration RAM Delay Req frame，Last coprocessor is written to transmission task FIFO Delay Req frame in the base address sending frame configuration RAM，Trigger the transmission of Delay Req frame.Send return fifo status by inquiry (interrupt after design retention frame transmission and inquire about two kinds of methods, flow chart 4 example uses querying method), from send return FIFO obtains Delay Req send frame at physical interface at timestamp t3 to general register r3.
Lower flow process is said below with time sequencing, when PTP receiving processing module receives Sync frame when, frame is placed in reception frame buffer, simultaneously this frame base address in receiving frame buffer is put in reception task FIFO, produce to receive and interrupt, cause the CAM analysis to event source, because configuration above, first the program of trigger section 0, by program segment 0 trigger section 7 again, program segment 7 finally triggers and Delay Req frame is sent.
2, receive the configuration of Delay Resp frame: the address of (1) configuration CAM is when being 0, content be 0x01 and above the 1st step be that multiplexing configures；(2) configure the address of CAM when being 4 simultaneously, content is 0x19, wherein the highest order of content 0x19 effectively shows that " the event source " of this CAM comes from 11 to 8 these 4 results of the general depositor r6 of coprocessor, programming below can be written as receiving the frame format type MSG_TYPE of frame, in this application, because receive is Delay Resp frame, according to IEEE1588 agreement, therefore MSG_TYPE is 9, being combined with highest significant position is exactly content 0x19, and CAM address 4 is the base address of program segment 4；(4) program of program segment 0 is similar with step 1, simply receives frame and is changed into Delay Resp by Sync, but any PTP receives flow process and the code that frame is just as program segment 0；(5) program of program segment 4 includes from the timestamp t4 (the t4 moment is the physical timestamp that master receives Delay Req) to general register r4 receiving frame buffer acquisition reception Delay Resp frame；T1～t4 inside agreement general register r1～r4 is done plus-minus and calculates by protocol processor, final result is assigned in coprocessor special return register r5, by logical design, timing updates the time of this return register in the local zone time of slave.
Lower flow process is said below with time sequencing, when PTP receiving processing module receives Delay Resp frame when, frame is placed in reception frame buffer, simultaneously this frame base address in receiving frame buffer is put in reception task FIFO, produce to receive and interrupt, cause the CAM analysis to event source, because configuration above, the first program of trigger section 0, by program segment 0 trigger section 4 again, program segment 4 completes to calculate the time deviation of slave and master, and triggers the hardware calibration time.
Although the foregoing describing the detailed description of the invention of the present invention, it will be appreciated by those of skill in the art that these are merely illustrative of, protection scope of the present invention is defined by the appended claims.These embodiments, on the premise of without departing substantially from the principle of the present invention and essence, can be made various changes or modifications, but these changes and amendment each fall within protection scope of the present invention by those skilled in the art.
Claims (10)
1. a coprocessor, it is characterised in that including: PTP protocol engine and PTP transceiver module；
Described PTP protocol engine includes: event source processes moderator and agreement coprocessor, described PTP
Transceiver module includes: PTP sends processing module and PTP receiving processing module；
Described event source processes moderator and is configured with the corresponding relation of event source and program segment, for
CAM input is event source, performs the program segment corresponding with the CAM hit, the CAM's of hit
The base address of index address instruction program section；
Described agreement coprocessor is used for performing some instructions；
Described PTP sends processing module and possesses interface and the module being available for the access of described agreement coprocessor
And it is available for interface and the module of outer CPU interface accessing；
Described PTP receiving processing module possesses interface and the module being available for the access of described agreement coprocessor.
2. coprocessor as claimed in claim 1, it is characterised in that described instruction includes following finger
One or more of order:
Program segment tail indicator: for managing execution address location and the internal state control bit of program；
Look into CAM instruction: for configuring the CAM of CAM input hit；
Reading instruction；
Write command；
Add instruction；
Subtract instruction；
Do-nothing instruction.
3. coprocessor as claimed in claim 1, it is characterised in that be available for described agreement association and process
The module that device accesses includes that sending frame configuration RAM, transmission task FIFO and transmission returns in FIFO
One or more；
And/or, the module being available for outer CPU interface accessing includes sending frame configuration RAM；
And/or, the connection module being available for the access of described agreement coprocessor includes reception task FIFO, reception
One or more in frame buffer and PTP filtering frames module.
4. coprocessor as claimed in claim 1, it is characterised in that described PTP protocol engine is also
Including bus selector, described agreement coprocessor by described bus selector respectively with described PTP
Send processing module and described PTP receiving processing module connects.
5. coprocessor as claimed in claim 1, it is characterised in that described coprocessor also includes
Frame pretreatment module, described PTP receiving processing module is by described frame pretreatment module and Ethernet
MAC connects.
6. coprocessor as claimed in claim 1, it is characterised in that described PTP transmission processes mould
Block also provides for the pretreatment module adaptive with ethernet mac.
7. coprocessor as claimed in claim 1, it is characterised in that described PTP transceiver module is also
Including time stamp generator, described time stamp generator sends processing module and described with described PTP respectively
PTP receiving processing module connects, to provide timestamp.
8. coprocessor as claimed in claim 1, it is characterised in that described event source includes: extremely
A few time counter, receipts frame and a frame interrupt, program segment tail looks into CAM event.
9. coprocessor as claimed in claim 1, it is characterised in that described instruction is micro-code instruction.
10. coprocessor as claimed in claim 9, it is characterised in that described coprocessor uses 72
Position micro-code instruction and assembler directive based on described micro-code instruction.
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|---|---|---|---|---|
| CN110502278A (en) * | 2019-07-24 | 2019-11-26 | 福州瑞芯微电子股份有限公司 | Neural network coprocessor and its association's processing method based on RiscV extended instruction |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080109634A1 (en) * | 2005-03-30 | 2008-05-08 | George Chrysos | Credit-based activity regulation within a microprocessor |
| CN103746789A (en) * | 2013-12-18 | 2014-04-23 | 北京四方继保自动化股份有限公司 | Method for realizing high-precision time scales in IEEE-1588 protocol based on CPU universal timer |
-
2016
- 2016-03-14 CN CN201610143284.9A patent/CN105930132B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080109634A1 (en) * | 2005-03-30 | 2008-05-08 | George Chrysos | Credit-based activity regulation within a microprocessor |
| CN103746789A (en) * | 2013-12-18 | 2014-04-23 | 北京四方继保自动化股份有限公司 | Method for realizing high-precision time scales in IEEE-1588 protocol based on CPU universal timer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110502278A (en) * | 2019-07-24 | 2019-11-26 | 福州瑞芯微电子股份有限公司 | Neural network coprocessor and its association's processing method based on RiscV extended instruction |
| CN110502278B (en) * | 2019-07-24 | 2021-07-16 | 瑞芯微电子股份有限公司 | Neural network coprocessor based on RiccV extended instruction and coprocessing method thereof |
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