CN105915040A

CN105915040A - Electric leakage circuit

Info

Publication number: CN105915040A
Application number: CN201610400995.XA
Authority: CN
Inventors: 杨超; 张仁富; 马辉
Original assignee: STEADICHIPS Inc
Current assignee: STEADICHIPS Inc
Priority date: 2016-06-08
Filing date: 2016-06-08
Publication date: 2016-08-31

Abstract

The invention relates to the integrated circuit field and is especially suitable for a SOC (a system on chip) chip in which a large capacitor exists between a power supply and ground of a PCB (printed circuit board) or an internal portion of the chip. The invention especially discloses an electric leakage circuit. Charges stored by the capacitor between the power supply and the ground can be rapidly discharged. The chip is guaranteed to work normally. The circuit comprises the capacitor. One end of the capacitor is grounded. The circuit is characterized in that the other end of the capacitor is connected to a grid electrode of a first NMOS pipe, and a drain electrode and a grid electrode of a first PMOS pipe; a source electrode of the first NMOS pipe is grounded and a drain electrode is connected to one end of a resistor; and the other end of the resistor is connected to a source electrode of the first PMOS pipe and then is connected to a power supply VDD.

Description

A kind of leakage circuit

Technical field

The present invention relates to integrated circuit fields, be particularly well-suited to PCB(printed circuit board (PCB)) or the power supply of chip internal to the SOC(SOC(system on a chip) that there is bulky capacitor between ground) chip, be specially a kind of leakage circuit.

Background technology

Along with developing rapidly of SOC, digital circuit scale is the most increasing, and register, latch quantity in circuit increase rapidly, POR(electrification reset) circuit has become as a part indispensable in SOC circuit.Simultaneously because there is noise on power supply, in order to obtain a cleaner VDD, typically can put some bigger electric capacity at PCB and chip internal, this electric capacity is connected between power supply and ground, can effectively filter the noise of exterior power supply, stably be input to the VDD of chip.Traditional electrification reset circuit is also based on capacitor charge and discharge is needed certain time, is then passed through simulating integrated phase inverter and processes this signal, can obtain the signal waveform of anticipation.If but the unexpected power down of power supply, owing to power supply and ground are directly with the presence of a electric capacity the biggest, the power supply being now input to chip internal cannot be immediately turned into 0, if input power is not when dropping under a magnitude of voltage, power supply powers on again, and now the electrification reset circuit of chip cannot normally work.Thus cause digital units part and partial simulation part cannot be returned to initial value at the beginning of powering on, and cannot reset in register, to such an extent as to the initial value of circuit is wrong, final output is also wrong, causes chip abnormal work.

Summary of the invention

In order to solve the problems referred to above, the invention provides a kind of leakage circuit, its can quick-discharging power supply to the electric charge of electric capacity storage between ground, it is ensured that chip normally works.

Its technical scheme is such that a kind of leakage circuit, it includes electric capacity, described electric capacity one end ground connection, it is characterized in that, the described electric capacity other end connects the grid of the first NMOS tube, the drain and gate of the first PMOS, the source electrode polar region of described first NMOS tube, drain electrode connect resistance one end, and the described resistance other end connects power vd D after being connected with the source electrode of described first PMOS.

It is further characterized by, and described electric capacity is by the 3rd POMS pipe described first PMOS of connection, and the grid of described 3rd PMOS connects EN enable signal, drain electrode connects the described electric capacity other end, the drain and gate of source electrode described first PMOS of connection；

Described 3rd POMS pipe and second PMOS of at least connecting between described first PMOS；

The grid of described first NMOS tube connects the drain electrode of the second NMOS tube, and the grid of described second NMOS tube connects EN and enables signal, source ground.

After using the circuit of the present invention, the voltage of the point being connected due to the grid of resistance and the first NMOS tube is connected to by electric capacity, so this point voltage will not be immediately turned to 0, but through one slowly process just become 0, thus the first NMOS tube will not be closed at once, power vd D is connected to the ground is connect by resistance, the first NMOS tube composition path, make power supply be able to quick-discharging to the electric charge stored above the electric capacity between ground to fall, so the voltage of power vd D also can quickly drop to a very low level, it is ensured that por circuit normally works.

Accompanying drawing explanation

Fig. 1 is that circuit of the present invention connects por circuit module diagram；

Fig. 2 is C_LEAKAGE point voltage situation of change schematic diagram；

Fig. 3 is the two kinds of situation of change schematic diagrames of VDD with or without leakage circuit of the present invention；

Fig. 4 is the two kinds of exporting change situation schematic diagrames of POR with or without leakage circuit of the present invention.

Detailed description of the invention

See Fig. 1, Fig. 2, Fig. 3, shown in Fig. 4, a kind of leakage circuit, it includes electric capacity 3_1, electric capacity 3_1 one end ground connection, the electric capacity 3_1 other end connects the drain electrode of the 3rd PMOS 1_3, the grid of the first NMOS tube 2_1, the drain electrode of the second NMOS tube 2_2, the grid of the 3rd PMOS 1_3 connects EN and enables signal, power vd D is connected after source series the second PMOS 1_2 and the first PMOS 1_1, the source electrode polar region of the first NMOS tube 2_1, drain electrode connects resistance 4_1 one end, the resistance 4_1 other end connects power vd D, the grid of the second NMOS tube 2_2 connects EN and enables signal, source ground.Power vd D connects por circuit module.The point that in figure, the grid of resistance 4_1 and the first NMOS tube 2_1 is connected is C_LEAKAGE point.3rd PMOS 1_3 and the second NMOS tube 2_2 are controlled by EN signal, and Main Function is when circuit needs to turn off, and cuts off electric leakage module, so can reduce circuit and turn off the current drain of module.

From figure 3, it can be seen that when the unexpected power down of power supply, the supply voltage adding leakage circuit of the present invention can drop to 0.5V at 123.5ms from 2.8V, and the voltage not adding the power supply of leakage circuit of the present invention can only drop to 2.3V from 2.8V at 10s.If the minimum operating voltage of circuit is 2.6V, operating voltage minimum for POR is 0.8V, then the POR of chip can be caused to work if circuit continues to work at power down 10S.As it has been described above, cause chip abnormal work.Can regulate, by the size of regulation resistance 4_1, the speed that VDD declines simultaneously.

What Fig. 4 was given is in the case of power supply power-fail, there is not electric leakage module and there is the POR output waveform of electric leakage module.It can be seen that at the beginning of powering in figure, owing to there is no electric charge on electric capacity, so two kinds of circuit all can complete to reset；But after power supply power-fail, there is no cannot again resetting of leakage circuit of the present invention, and the electrification reset that still can normally complete that there is leakage circuit of the present invention works, it is ensured that the normal work of circuit.

Claims

1. a leakage circuit, it includes electric capacity, described electric capacity one end ground connection, it is characterized in that, the described electric capacity other end connects the grid of the first NMOS tube, the drain and gate of the first PMOS, the source electrode polar region of described first NMOS tube, drain electrode connect resistance one end, and the described resistance other end connects power vd D after being connected with the source electrode of described first PMOS.

A kind of leakage circuit the most according to claim 1, it is characterized in that, described electric capacity is by the 3rd POMS pipe described first PMOS of connection, and the grid of described 3rd PMOS connects EN enable signal, drain electrode connects the described electric capacity other end, the drain and gate of source electrode described first PMOS of connection.

A kind of leakage circuit the most according to claim 2, it is characterised in that described 3rd POMS pipe and second PMOS of at least connecting between described first PMOS.

A kind of leakage circuit the most according to claim 1, it is characterised in that the grid of described first NMOS tube connects the drain electrode of the second NMOS tube, the grid of described second NMOS tube connects EN and enables signal, source ground.