CN105913873B

CN105913873B - Precise reading time sequence control circuit for ultra-high-speed nonvolatile memory

Info

Publication number: CN105913873B
Application number: CN201610218419.3A
Authority: CN
Inventors: 郭家荣
Original assignee: Shanghai Dianji University
Current assignee: Shanghai Dianji University
Priority date: 2016-04-08
Filing date: 2016-04-08
Publication date: 2020-01-24
Anticipated expiration: 2036-04-08
Also published as: CN105913873A

Abstract

The invention discloses a precise reading time sequence control circuit for a super-high-speed nonvolatile memory, which comprises: the buffer circuit is used for buffering and amplifying the clock signal to improve the loaded capacity of the clock signal; the induction amplifier circuit is used for converting the information of the memory into digital voltage; the adjustable delay unit is used for delaying and outputting the input signal under the control of the delay control signal; a reference pulse generator for generating a reference pulse at each read cycle; the phase discriminator is used for comparing the phase of the reference pulse with the longest delay time in the read path so as to output a delay control signal to the adjustable delay unit.

Description

Precise reading time sequence control circuit for ultra-high-speed nonvolatile memory

Technical Field

The present invention relates to a read timing control circuit, and more particularly, to an accurate read timing control circuit for a super-high speed nonvolatile memory.

Background

The read timing control circuit for the ultra-high speed nonvolatile memory in the prior art often adopts the following two ways: with RC delay and VT compensation. Fig. 1 is a circuit diagram of a conventional read timing control circuit in the prior art, which includes an RC/VT delay unit, a plurality of buffers Bclk1, Bclk2, Bufx, Buf0, and a plurality of sense amplifiers SAx0 … … Saxn, SA00 … … SA0n, wherein the entire timing delay is the delay of the delay unit plus the delay from the delay unit to the sense amplifiers (the line and logic delays in the figure).

The read timing control circuit has the following disadvantages:

1) the timing generator (the whole circuit) is easily affected by process corner (process corner), voltage and temperature variation, so that the generated timing has deviation;

2) the resulting offset timing cannot be adjusted in real time.

Disclosure of Invention

In order to overcome the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a circuit for controlling a precise read timing for an ultra-high speed nonvolatile memory, which can solve the problem that the timing in the ultra-high speed nonvolatile memory is difficult to be precisely controlled.

To achieve the above and other objects, the present invention provides a precise read timing control circuit for a super high speed nonvolatile memory, comprising:

the buffer circuit is used for buffering and amplifying the clock signal to improve the loaded capacity of the clock signal;

the induction amplifier circuit is used for converting the information of the memory into digital voltage;

the adjustable delay unit is used for delaying and outputting the input signal under the control of the delay control signal;

a reference pulse generator for generating a reference pulse at each read cycle;

and the phase detector is used for comparing the phase of the reference pulse with the longest delay time in the reading path so as to output a delay control signal to the adjustable delay unit.

Further, the buffer circuit comprises a plurality of buffers, wherein the buffer (Bclk1), the adjustable delay unit and the buffer (Bclk2) are sequentially cascaded, the output of the buffer (Bclk2) is connected to the input end of each buffer (Buf0-Buf x), and the outputs of the buffers (Buf0-Buf x) are respectively connected to the sense amplifier circuits.

Further, the sense amplifier circuit includes a plurality of sense amplifiers, which are divided into a plurality of groups and respectively connected to the output terminals of the buffers (Buf0-Buf x).

Further, the clock with the longest delay in each group is buffered by a buffer (Bclk3) and then connected to the input end of the phase detector, and the number of the sensing amplifiers depends on the number of the row memory cells.

Further, the reference pulse generator has an input clock and an output connected to the phase detector.

Further, the output end of the phase detector is connected to the control end of the adjustable delay unit.

Further, the adjustable delay unit is a unit that can be varied according to a control signal.

Further, the adjustable delay unit can adjust the total delay time from the input clock to the farthest sense amplifier to the same value as the reference pulse by adjusting the delay time of the unit.

Further, the operation of the read timing automatic adjustment of the circuit is performed throughout the quiescent period.

Further, before the first read operation is really started, the reference pulse generator starts to work and sends a false read cycle, and the adjustable delay unit is corrected through a feedback signal generated by the phase discriminator so as to ensure that the real read cycle has accurate time sequence control.

Compared with the prior art, the accurate read timing control circuit for the ultra-high-speed nonvolatile memory realizes the control of the read timing by utilizing the reference pulse generator, the adjustable delay unit and the phase discriminator, and solves the problem that the timing in the ultra-high-speed nonvolatile memory is difficult to accurately control.

Drawings

FIG. 1 is a circuit diagram of a conventional read timing control circuit of the prior art;

FIG. 2 is a circuit diagram of a precise read timing control circuit for an ultra-high speed nonvolatile memory according to the present invention;

FIG. 3 is a diagram illustrating a comparison of the timing waveforms for generating the offset according to the present invention.

Detailed Description

Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

FIG. 2 is a circuit diagram of a precise read timing control circuit for a super high speed nonvolatile memory according to the present invention. As shown in fig. 2, the precise read timing control circuit for a super-high speed nonvolatile memory according to the present invention includes an adjustable delay unit 10, a reference pulse generator 20, a phase detector 30, a buffer circuit 40, and a sense amplifier circuit 50.

The buffer circuit 40 comprises a plurality of buffers Bclk1-Bclk3 and Buf0-Bufx, is mainly used for buffering and amplifying clock signals to improve the load carrying capacity of the clock signals and is a general circuit; the sense amplifier circuit 50 includes a plurality of sense amplifiers SA00-SA0n, … …, SAx0-SAxn, the number of which depends on the number of column memory cells, for converting the information of the memory into digital voltages, which is also a general circuit; the adjustable delay unit 10 is used for delaying and outputting the input signal under the control of the delay control signal; a reference pulse generator 20 for generating a reference pulse at each read cycle; the phase detector 30 is used to phase compare the reference pulse with the longest delay in the read path to output a delay control signal.

The buffer Bclk1, the adjustable delay unit 10 and the buffer Bclk2 are sequentially cascaded, the output of the buffer Bclk2 is connected to the input end of the buffer Buf0-x, the output of the buffer Buf0-x is respectively connected to the sense amplifiers SA00-SA0n, … … and SAx0-SAxn, the clock with the longest delay is buffered by the buffer Bclk3 and then connected to the input end of the phase detector 30, the input clock CLK is buffered by the Bclk1 and then branched to the reference pulse generator 20, the reference pulse generated by the reference pulse generator 20 is connected to the other input end of the phase detector 30, specifically, the reference pulse generator 20 generates a reference pulse at each read clock, the input of the reference pulse is the input clock CLK, and the output of the reference pulse generator is connected to the phase detector 30; the output terminal of the phase detector 30 is connected to the control terminal of the adjustable delay unit 10, that is, the phase detector 30 has two input sources, one is the reference pulse from the reference pulse generator 20, and the other is the longest delay in the read path, the phase detector 30 compares the two sources, and then generates a control signal to modulate the adjustable delay unit 10, the adjustable delay unit 10 is a unit that can be changed according to the control signal, and by adjusting the delay time of the unit, the whole delay time outputted from the CLK to the farthest Sense Amplifier (SA) can be adjusted to be the same as the reference pulse.

The read sequence auto-adjustment operation of the present invention is performed throughout the static (Standby) period. Before the first read operation is really started, the reference pulse generator starts to work and sends a fake read cycle, and the purpose is to correct the adjustable delay unit through a feedback signal generated by the phase discriminator so as to ensure that the real read cycle has accurate time sequence control

FIG. 3 is a graph comparing the timing waveforms for generating deviations according to the present invention. Where the first waveform is the desired sense timing target. Different processes and different Sense amplifiers in the same chip have time sequence deviations, such as Actual Delay1, Actual Delay2 and Actual Delay3 in waveform diagrams, and the last waveform is the final target to be realized by the invention, namely, the internal time sequence control and the target time sequence (the sensing timing target in the diagram) are realized to be accurate and consistent.

In summary, the present invention is a precise read timing control circuit for an ultra-high speed nonvolatile memory, which realizes the control of read timing by using a reference pulse generator, an adjustable delay unit, and a phase discriminator, and solves the problem that the timing in the ultra-high speed nonvolatile memory is difficult to be precisely controlled.

Compared with the prior art, the invention has the following advantages:

1) the entire read timing (delay cell delay + line/logic delay) is not susceptible to voltage, temperature and process corner;

2) the reading time sequence is automatically adjusted at different voltages and temperatures;

3) sufficient read margin is a guarantee that correct reading of data is achieved. Compared with the traditional scheme, the method has the same reading margin under the slowest condition and has larger reading margin under other conditions.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims

1. A precise read timing control circuit for ultra-high speed non-volatile memory, comprising:

the reference pulse generator is used for generating a reference pulse in each reading period, starts to work before the first reading operation is really started, sends a false reading period, and corrects the adjustable delay unit through a feedback signal generated by the phase discriminator so as to ensure that the real reading period has accurate time sequence control;

the phase discriminator is used for comparing the phase of the reference pulse with the longest delay time in the reading path so as to output a delay control signal to the adjustable delay unit;

the buffer circuit comprises a plurality of buffers, wherein the buffer Bclk1, the adjustable delay unit and the buffer Bclk2 are sequentially cascaded, the output of the buffer Bclk2 is connected to the input end of each buffer Buf0-Bufx, and the outputs of the buffers Buf0-Bufx are respectively connected to the sensing amplifier circuit;

the sensing amplifier circuit comprises a plurality of sensing amplifiers which are divided into a plurality of groups and are respectively connected to the output end of the buffer Buf 0-Bufx;

the clock with the longest delay in each group is buffered by a buffer Bclk3 and then connected to the input end of the phase discriminator, and the number of the sense amplifiers depends on the number of the row storage units;

the input of the reference pulse generator is an input clock, and the output of the reference pulse generator is connected to the phase discriminator;

the adjustable delay unit can adjust the whole delay time from an input clock to the farthest sensing amplifier by adjusting the delay time of the unit to be the same as that of a reference pulse, wherein the farthest sensing amplifier is the last sensing amplifier in each group which receives the clock signal.

2. A precise read timing control circuit for a super high speed nonvolatile memory as claimed in claim 1, wherein: the output end of the phase discriminator is connected to the control end of the adjustable delay unit.

3. A precise read timing control circuit for a super high speed nonvolatile memory as claimed in claim 2, wherein: the adjustable delay unit is a unit that can be varied according to a control signal.

4. A precise read timing control circuit for a super high speed nonvolatile memory as claimed in claim 3, wherein: the operation of the read timing auto-adjustment of the circuit is performed throughout the quiescent period.