CN105867847A - Memory access control method, device and system - Google Patents
Memory access control method, device and system Download PDFInfo
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- CN105867847A CN105867847A CN201610184196.3A CN201610184196A CN105867847A CN 105867847 A CN105867847 A CN 105867847A CN 201610184196 A CN201610184196 A CN 201610184196A CN 105867847 A CN105867847 A CN 105867847A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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Abstract
The embodiment of the invention provides a memory access control method, device and system. The method comprises the steps that a processor executes a memory setting command, wherein the memory setting command comprises a command code, an original memory address scope and a target value, and the command code is identification information of the memory setting command; after the processor executes the memory setting command, memory setting information is generated, wherein the memory setting information comprises a target memory address scope and the target value; the processor sends the memory setting information to a memory controller, so that the memory controller sets the value of a target area corresponding to the target memory address scope in a memory to be the target value according to the memory setting information. According to the memory access control method, device and system, the memory setting command is executed through the processor, the memory setting information is sent to the memory controller, the memory controller executes operation of memory setting, the processor can execute other types of operation, the situation that it takes a great amount of processing time for the processer to conduct memory setting is avoided, and processing efficiency of the processor is improved.
Description
Technical field
The present embodiments relate to communication technical field, particularly relate to a kind of access control method, device and
System.
Background technology
Along with the sustainable development of processor technology, memory access performance become affect processor performance main because of
Element.In many memory access modes, memory setting (memset) class is the most important one.
Memory setting class memory access is generally used for initializing one section of continuous print memory headroom, the example include but not
Be limited to: in application program to the specific assignment of array continuous element element, memset built-in function, in GPU to frame
The removing of relief area.The feature of this kind of memory access is mainly that memory access scope is big, memory access mode is simple.
But, memory setting class memory access needs processor to perform access instruction one by one, thus occupies process
The time that processes in a large number of device, the treatment effeciency of processor is caused to be greatly reduced.
Summary of the invention
The embodiment of the present invention provides a kind of access control method, Apparatus and system, to improve the place of processor
Reason efficiency.
One aspect of the embodiment of the present invention is to provide a kind of access control method, including:
Processor performs memory setting instruction, and the instruction of described memory setting includes order code, original internal memory ground
Location scope and described desired value, described order code is the identification information of described memory setting instruction；
Described processor generates memory setting information, described memory setting after performing the instruction of described memory setting
Information includes target memory address realm and described desired value；
Described processor sends described memory setting information to Memory Controller Hub, so that described Memory Controller Hub
According to described memory setting information by the value of target area corresponding for target memory address realm described in internal memory
It is set to described desired value.
Another aspect of the embodiment of the present invention is to provide a kind of access control method, including:
Memory Controller Hub receives the memory setting information that processor sends, and described memory setting information includes mesh
Mark memory address range and described desired value, described memory setting information is that the execution of described processor is described interior
Depositing the information generated after arranging instruction, the instruction of described memory setting includes order code, original memory address model
Enclosing and described desired value, described order code is the identification information of described memory setting instruction；
Described Memory Controller Hub according to described memory setting information by target memory address realm described in internal memory
The value of corresponding target area is set to described desired value.
Another aspect of the embodiment of the present invention is to provide a kind of memory access and controls device, including:
Instruction performs module, is used for performing memory setting instruction, the instruction of described memory setting include order code,
Original memory address range and described desired value, described order code is the mark letter of described memory setting instruction
Breath；
Memory setting information generating module, is used for generating memory setting information, described memory setting information bag
Include target memory address realm and described desired value；
Sending module, for sending described memory setting information to Memory Controller Hub, so that described internal memory control
Device processed according to described memory setting information by target area corresponding for target memory address realm described in internal memory
Value be set to described desired value.
Another aspect of the embodiment of the present invention is to provide a kind of Memory Controller Hub, including:
Memory setting information receiving module, for receiving the memory setting information that processor sends, described interior
Depositing configuration information and include target memory address realm and described desired value, described memory setting information is described
Processor perform described memory setting instruction after generate information, described memory setting instruction include order code,
Original memory address range and described desired value, described order code is the mark letter of described memory setting instruction
Breath；
Memory setting module, is used for target memory address described in internal memory according to described memory setting information
The value of the target area that scope is corresponding is set to described desired value.
Another aspect of the embodiment of the present invention is to provide a kind of memory access control system, including internal memory, described
Memory access control device and described Memory Controller Hub.
The access control method of embodiment of the present invention offer, Apparatus and system, perform internal memory by processor
Instruction is set, and memory setting information is sent to Memory Controller Hub, Memory Controller Hub perform internal memory and set
The operation put, processor can perform other operations, it is to avoid memory setting takies when processing in a large number of processor
Between, improve the treatment effeciency of processor.
Accompanying drawing explanation
The access control method flow chart that Fig. 1 provides for the embodiment of the present invention；
The system construction drawing that the access control method that Fig. 2 provides for the embodiment of the present invention is suitable for；
The access control method flow chart that Fig. 3 provides for another embodiment of the present invention；
The access control method flow chart that Fig. 4 provides for another embodiment of the present invention；
The access control method flow chart that Fig. 5 provides for another embodiment of the present invention；
Fig. 6 controls the structure chart of device for the memory access that the embodiment of the present invention provides；
Fig. 7 controls the structure chart of device for the memory access that another embodiment of the present invention provides；
The structure chart of the Memory Controller Hub that Fig. 8 provides for the embodiment of the present invention；
The structure chart of the Memory Controller Hub that Fig. 9 provides for another embodiment of the present invention；
The structure chart of the memory access control system that Figure 10 provides for the embodiment of the present invention.
Detailed description of the invention
The access control method flow chart that Fig. 1 provides for the embodiment of the present invention；Fig. 2 is the embodiment of the present invention
The system construction drawing that the access control method provided is suitable for.The embodiment of the present invention is for memory setting class memory access
Need processor to perform access instruction one by one, thus occupy a large amount of process times of processor, cause place
The treatment effeciency of reason device is greatly reduced, it is provided that access control method, the method specifically comprises the following steps that
Step S101, processor perform memory setting instruction, described memory setting instruction include order code,
Original memory address range and described desired value, described order code is the mark letter of described memory setting instruction
Breath；
As in figure 2 it is shown, the system that the access control method that the embodiment of the present invention provides is suitable for includes processor
20, Memory Controller Hub 21 and internal memory 22, processor 20 is specifically as follows central processing unit (Central
Processing Unit, be called for short CPU), graphic process unit (Graphics Processing Unit,
It is called for short GPU) or the equipment of memory setting class memory access；In processor 20 is accessed by Memory Controller Hub 21
Depositing 22, the most directly access internal memory 22, processor 20 includes address conversioning unit 201 and cache
Consistency treatment unit 202, Memory Controller Hub 21 includes memory access unit 211.When processor 20 need right
When a certain region of internal memory 22 carries out memory setting, processor 20 performs memory setting instruction, described interior
Depositing and arrange instruction and include order code, original memory address range and described desired value, described order code is institute
State the identification information of memory setting instruction.
Step S102, described processor generate memory setting information, institute after performing the instruction of described memory setting
State memory setting information and include target memory address realm and described desired value；
Processor 20 generates memory setting information after performing the instruction of described memory setting, and described memory setting is believed
Breath includes that target memory address realm and described desired value, described target memory address realm are processor 20
The address realm of the target area in the internal memory 22 that needs are arranged, this address realm is specially bound.
Step S103, described processor send described memory setting information to Memory Controller Hub, so that described
Memory Controller Hub according to described memory setting information by mesh corresponding for target memory address realm described in internal memory
The value in mark region is set to described desired value.
After processor 20 generates memory setting information, this memory setting information is sent to Memory Controller Hub
21, the memory access unit 211 in Memory Controller Hub 21 is according to this memory setting message reference internal memory 22, tool
Body, the value of target area corresponding for this target memory address realm in internal memory 22 is set by memory access unit 211
It is set to described desired value.
The embodiment of the present invention performs memory setting by processor and instructs, and memory setting information is sent to
Memory Controller Hub, is performed the operation of memory setting by Memory Controller Hub, and processor can perform other operations,
Avoid memory setting to take a large amount of process times of processor, improve the treatment effeciency of processor.
The access control method flow chart that Fig. 3 provides for another embodiment of the present invention.The embodiment of the present invention carries
The method of confession specifically comprises the following steps that
Step S301, processor perform memory setting instruction, described memory setting instruction include order code,
Original memory address range and described desired value, described order code is the mark letter of described memory setting instruction
Breath；
In embodiments of the present invention, memory setting instruction includes order code, original memory address range and institute
Stating desired value, described order code is the identification information of described memory setting instruction.
The address that step S302, described original memory address range represent is virtual address；Described processor
Described virtual address is converted to physical address obtain described target memory address realm and generate memory setting
Information；
If during the memory setting instruction that processor 20 performs, memory setting instructs the original memory address included
The address of Range Representation is virtual address, as in figure 2 it is shown, the then address conversioning unit in processor 20
This virtual address is converted to physical address by 201 to be obtained described target memory address realm and generates internal memory and set
Confidence ceases, and described memory setting information includes target memory address realm and described desired value.
What target memory address realm and original memory address range pointed to is same region of memory, difference
Place is that original memory address range virtual address represents, target memory address realm physical address table
Show.
Step S303, described processor send described memory setting information to Memory Controller Hub, so that described
Memory Controller Hub according to described memory setting information by mesh corresponding for target memory address realm described in internal memory
The value in mark region is set to described desired value.
This virtual address is converted to physically by the embodiment of the present invention by the address conversioning unit in processor
Location, it is ensured that internal memory configuration information is correctly identified by Memory Controller Hub.
The access control method flow chart that Fig. 4 provides for another embodiment of the present invention.At Fig. 1 or Fig. 3 pair
On the basis of the embodiment answered, processor can also include cache, it is preferred that the embodiment of the present invention exists
On the basis of the embodiment that Fig. 3 is corresponding, processor can also include cache, corresponding memory access controlling party
Method specifically comprises the following steps that
Step S401, processor perform memory setting instruction, described memory setting instruction include order code,
Original memory address range and described desired value, described order code is the mark letter of described memory setting instruction
Breath；
The instruction of described memory setting includes order code, original memory address range and described desired value, described
Order code is the identification information of described memory setting instruction.
The address that step S402, described original memory address range represent is virtual address；Described processor
Described virtual address is converted to physical address obtain described target memory address realm and generate memory setting
Information；
Step S403, described processor are by the described target memory address realm of storage in described cache
The value of corresponding target area carries out writing back or invalid；
In embodiments of the present invention, processor also includes cache, and this cache may store
Stating the value of target area corresponding to target memory address realm, the embodiment of the present invention is mainly used in internally depositing into
Row accesses and arranges, and owing to cache is consistent with the address distribution of internal memory, same address is pointed to
Cache is consistent with the region of internal memory, in order to prevent in the internal memory after arranging and cache
The value of storage is different, before Memory Controller Hub 21 accesses and arranges internal memory 22, at cache coherence
Reason unit 202 is by target area corresponding for the described target memory address realm of storage in described cache
Value carry out writing back or invalid.
Step S404, described processor send described memory setting information to Memory Controller Hub, so that described
Memory Controller Hub according to described memory setting information by mesh corresponding for target memory address realm described in internal memory
The value in mark region is set to described desired value；
Step S405, described processor receive the label information that described Memory Controller Hub returns, described labelling
Information is the information returning to described processor after described Memory Controller Hub successfully arranges internal memory；
Processor 20 label information is returned to after Memory Controller Hub 21 successfully arranges internal memory.
Step S406, described processor produce and interrupt.
During arranging internal memory 22 due to Memory Controller Hub 21, processor 20 may perform other journeys
Sequence, produces after processor 20 receives the label information that Memory Controller Hub 21 returns and interrupts to stop
Perform other and process operation response memory setting.
The embodiment of the present invention is before Memory Controller Hub accesses and arranges internal memory, and cache coherence processes single
The value of target area corresponding for the target memory address realm stored in cache is carried out writing back or nothing by unit
Effect, it is to avoid internal memory after the arranging value from cache the most stored is different, it is ensured that internal memory and height
Data consistency in speed caching.
The access control method flow chart that Fig. 5 provides for another embodiment of the present invention, embodiment of the present invention pin
Need processor to perform access instruction one by one memory setting class memory access, thus occupy a large amount of of processor
The process time, the treatment effeciency of processor is caused to be greatly reduced, it is provided that access control method, the method
Specifically comprise the following steps that
Step S501, Memory Controller Hub receive the memory setting information that processor sends, described memory setting
Information includes that target memory address realm and described desired value, described memory setting information are described processors
The information generated after performing the instruction of described memory setting, the instruction of described memory setting includes order code, original
Memory address range and described desired value, described order code is the identification information of described memory setting instruction；
As in figure 2 it is shown, the system that the access control method that the embodiment of the present invention provides is suitable for includes processor
20, Memory Controller Hub 21 and internal memory 22, processor 20 is specifically as follows central processing unit (Central
Processing Unit, be called for short CPU), graphic process unit (Graphics Processing Unit,
It is called for short GPU) or the equipment of memory setting class memory access；In processor 20 is accessed by Memory Controller Hub 21
Depositing 22, the most directly access internal memory 22, processor 20 includes address conversioning unit 201 and cache
Consistency treatment unit 202, Memory Controller Hub 21 includes memory access unit 211.When processor 20 need right
When a certain region of internal memory 22 carries out memory setting, processor 20 performs memory setting instruction, described interior
Depositing and arrange instruction and include order code, original memory address range and described desired value, described order code is institute
State the identification information of memory setting instruction.
Processor 20 generates memory setting information after performing the instruction of described memory setting, and described memory setting is believed
Breath includes that target memory address realm and described desired value, described target memory address realm are processor 20
The address realm of the target area in the internal memory 22 that needs are arranged, this address realm is specially bound.
After processor 20 generates memory setting information, this memory setting information is sent to Memory Controller Hub
21。
Step S502, described Memory Controller Hub according to described memory setting information by target described in internal memory
The value depositing target area corresponding to address realm is set to described desired value.
Memory access unit 211 in Memory Controller Hub 21 is according to this memory setting message reference internal memory 22, tool
Body, the value of target area corresponding for this target memory address realm in internal memory 22 is set by memory access unit 211
It is set to described desired value.
The embodiment of the present invention performs memory setting by processor and instructs, and memory setting information is sent to
Memory Controller Hub, is performed the operation of memory setting by Memory Controller Hub, and processor can perform other operations,
Avoid memory setting to take a large amount of process times of processor, improve the treatment effeciency of processor.
On the basis of the embodiment that Fig. 5 is corresponding, after step S502, also include:
Described Memory Controller Hub is used for representing institute to described processor return label information, described label information
State Memory Controller Hub and internal memory is successfully set.
Concrete, after Memory Controller Hub 21 successfully arranges internal memory, return to processor 20 label information.
Fig. 6 controls the structure chart of device for the memory access that the embodiment of the present invention provides.The visit that the embodiment of the present invention provides
Depositing control device and can perform the handling process that access control method embodiment provides, this memory access controls device
Can be a module in the processor 21 in above-described embodiment or processor 21, such as Fig. 5 institute
Showing, memory access controls device 40 and includes that instruction performs module 41, memory setting information generating module 42 and sends out
Sending module 43, wherein, instruction performs module 41 and is used for performing memory setting instruction, described memory setting
Instruction includes order code, original memory address range and described desired value, and described order code is described internal memory
The identification information of instruction is set；Memory setting information generating module 42 is used for generating memory setting information, institute
State memory setting information and include target memory address realm and described desired value；Sending module 43 is for inwardly
Memory controller sends described memory setting information, so that described Memory Controller Hub is believed according to described memory setting
The value of target area corresponding for target memory address realm described in internal memory is set to described desired value by breath.
The embodiment of the present invention performs memory setting by processor and instructs, and memory setting information is sent to
Memory Controller Hub, is performed the operation of memory setting by Memory Controller Hub, and processor can perform other operations,
Avoid memory setting to take a large amount of process times of processor, improve the treatment effeciency of processor.
Fig. 7 controls the structure chart of device for the memory access that another embodiment of the present invention provides.At above-described embodiment
On the basis of, the address that described original memory address range represents is virtual address；Memory setting information is raw
Module 42 is become to obtain described target memory address specifically for described virtual address is converted to physical address
Scope also generates memory setting information.
Memory access controls device 40 and also includes cache coherence processing unit 202, cache coherence
Processing unit 202 is for target area corresponding to the described target memory address realm that will store in cache
The value in territory carries out writing back or invalid.
Memory access controls device 40 and also includes that receiver module 44, receiver module 44 are used for receiving described internal memory control
The label information that device processed returns, described label information is to return after described Memory Controller Hub successfully arranges internal memory
Information to described processor.
Memory access controls device 40 and also includes that interrupt module 45, interrupt module 45 connect for receiver module 44
Produce after receiving described label information and interrupt.
The memory access that the embodiment of the present invention provides controls device can be specifically for performing what above-mentioned Fig. 1 was provided
Embodiment of the method, here is omitted for concrete function.
This virtual address is converted to physically by the embodiment of the present invention by the address conversioning unit in processor
Location, it is ensured that internal memory configuration information is correctly identified by Memory Controller Hub；In Memory Controller Hub accesses and arranges
Before depositing, cache coherence processing unit is by corresponding for the memory address range stored in cache
The value of target area carries out writing back or invalid, it is to avoid the internal memory after arranging is the most stored with cache
Value different, it is ensured that internal memory and the data consistency in cache.
The structure chart of the Memory Controller Hub that Fig. 8 provides for the embodiment of the present invention.The embodiment of the present invention provides
Memory Controller Hub can perform the handling process that access control method embodiment provides, as shown in Figure 8, interior
Memory controller 80 includes memory setting information receiving module 81 and memory setting module 82, wherein, internal memory
Configuration information receiver module 81 is for receiving the memory setting information that processor sends, and described memory setting is believed
Breath includes that target memory address realm and described desired value, described memory setting information are that described processor is held
Row described memory setting instruction after generate information, described memory setting instruction include order code, original in
Depositing address realm and described desired value, described order code is the identification information of described memory setting instruction；In
Deposit arrange module 82 for according to described memory setting information by target memory address realm described in internal memory
The value of corresponding target area is set to described desired value.
The embodiment of the present invention performs memory setting by processor and instructs, and memory setting information is sent to
Memory Controller Hub, is performed the operation of memory setting by Memory Controller Hub, and processor can perform other operations,
Avoid memory setting to take a large amount of process times of processor, improve the treatment effeciency of processor.
The structure chart of the Memory Controller Hub that Fig. 9 provides for another embodiment of the present invention.On the basis of Fig. 8,
Memory Controller Hub 80 also includes label information sending module 83, and label information sending module 83 is for institute
State processor return label information, in described label information is used for representing that described Memory Controller Hub is successfully arranged
Deposit.
The Memory Controller Hub that the embodiment of the present invention provides can be specifically for performing the side that above-mentioned Fig. 5 is provided
Method embodiment, here is omitted for concrete function.The memory access that Figure 10 provides for the embodiment of the present invention controls system
The structure chart of system.This memory access control system can be used for performing the access control method described in above-described embodiment,
As shown in Figure 10, memory access control system 100 includes that memory access controls device 40, Memory Controller Hub 80 and interior
Depositing 90, wherein, memory access controls device 40 and controls for the memory access described in embodiment corresponding for Fig. 6 or Fig. 7
Device 40, Memory Controller Hub 80 is the Memory Controller Hub 80 described in embodiment corresponding for Fig. 8 or Fig. 9.
This memory access control system can be used for performing the access control method described in above-described embodiment, detailed process
Consistent with above-described embodiment, here is omitted.
In sum, the embodiment of the present invention performs memory setting by processor and instructs, and by memory setting
Information is sent to Memory Controller Hub, Memory Controller Hub perform the operation of memory setting, and processor can perform
Other operations, it is to avoid memory setting takies a large amount of process times of processor, improves the process of processor
Efficiency；By the address conversioning unit in processor, this virtual address is converted to physical address, it is ensured that
Internal memory configuration information is correctly identified by Memory Controller Hub；Before Memory Controller Hub accesses and arranges internal memory, high
Speed buffer consistency processing unit is by target area corresponding for the target memory address realm that stores in cache
The value in territory carries out writing back or invalid, it is to avoid the value the most stored with cache of the internal memory after arranging is not
With, it is ensured that internal memory and the data consistency in cache.
In several embodiments provided by the present invention, it should be understood that disclosed apparatus and method,
Can realize by another way.Such as, device embodiment described above is only schematically,
Such as, the division of described unit, it is only a kind of logic function and divides, actual can have additionally when realizing
Dividing mode, the most multiple unit or assembly can in conjunction with or be desirably integrated into another system, or
Some features can be ignored, or does not performs.Another point, shown or discussed coupling each other or
Direct-coupling or communication connection can be the INDIRECT COUPLING by some interfaces, device or unit or communication link
Connect, can be electrical, machinery or other form.
The described unit illustrated as separating component can be or may not be physically separate, makees
The parts shown for unit can be or may not be physical location, i.e. may be located at a place,
Or can also be distributed on multiple NE.Can select according to the actual needs part therein or
The whole unit of person realizes the purpose of the present embodiment scheme.
It addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit,
Can also be that unit is individually physically present, it is also possible to two or more unit are integrated in a list
In unit.Above-mentioned integrated unit both can realize to use the form of hardware, it would however also be possible to employ hardware adds software
The form of functional unit realizes.
The above-mentioned integrated unit realized with the form of SFU software functional unit, can be stored in a computer
In read/write memory medium.Above-mentioned SFU software functional unit is stored in a storage medium, including some fingers
Make with so that a computer equipment (can be personal computer, server, or the network equipment etc.)
Or processor (processor) performs the part steps of method described in each embodiment of the present invention.And it is aforementioned
Storage medium include: USB flash disk, portable hard drive, read only memory (Read-Only Memory, ROM),
Random access memory (Random Access Memory, RAM), magnetic disc or CD etc. are various permissible
The medium of storage program code.
Those skilled in the art are it can be understood that arrive, for convenience and simplicity of description, only with above-mentioned respectively
The division of functional module is illustrated, and in actual application, can above-mentioned functions be divided as desired
Join and completed by different functional modules, the internal structure of device will be divided into different functional modules, with
Complete all or part of function described above.The specific works process of the device of foregoing description is permissible
With reference to the corresponding process in preceding method embodiment, do not repeat them here.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right
It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common
Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it,
Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and
The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.
Claims (15)
1. an access control method, it is characterised in that including:
Processor performs memory setting instruction, and the instruction of described memory setting includes order code, original internal memory ground
Location scope and described desired value, described order code is the identification information of described memory setting instruction；
Described processor generates memory setting information, described memory setting after performing the instruction of described memory setting
Information includes target memory address realm and described desired value；
Described processor sends described memory setting information to Memory Controller Hub, so that described Memory Controller Hub
According to described memory setting information by the value of target area corresponding for target memory address realm described in internal memory
It is set to described desired value.
Method the most according to claim 1, it is characterised in that described original memory address range table
The address shown is virtual address；Described processor generates memory setting letter after performing the instruction of described memory setting
Breath, including:
Described virtual address is converted to physical address and obtains described target memory address realm by described processor
And generate memory setting information.
Method the most according to claim 1 and 2, it is characterised in that described processor includes at a high speed
Caching；Described method also includes:
Described processor is by target corresponding for the described target memory address realm of storage in described cache
The value in region carries out writing back or invalid.
Method the most according to claim 3, it is characterised in that described processor is to Memory Controller Hub
After sending described memory setting information, also include:
Described processor receives the label information that described Memory Controller Hub returns, and described label information is described
Memory Controller Hub returns to the information of described processor after successfully arranging internal memory.
Method the most according to claim 4, it is characterised in that described processor receives described internal memory
After the label information that controller returns, also include:
Described processor produces and interrupts.
6. an access control method, it is characterised in that including:
Memory Controller Hub receives the memory setting information that processor sends, and described memory setting information includes mesh
Mark memory address range and described desired value, described memory setting information is that the execution of described processor is described interior
Depositing the information generated after arranging instruction, the instruction of described memory setting includes order code, original memory address model
Enclosing and described desired value, described order code is the identification information of described memory setting instruction；
Described Memory Controller Hub according to described memory setting information by target memory address realm described in internal memory
The value of corresponding target area is set to described desired value.
Method the most according to claim 6, it is characterised in that described Memory Controller Hub is according to described
The value of target area corresponding for target memory address realm described in internal memory is set to institute by memory setting information
After stating desired value, also include:
Described Memory Controller Hub is used for representing institute to described processor return label information, described label information
State Memory Controller Hub and internal memory is successfully set.
8. a memory access controls device, it is characterised in that including:
Instruction performs module, is used for performing memory setting instruction, the instruction of described memory setting include order code,
Original memory address range and described desired value, described order code is the mark letter of described memory setting instruction
Breath；
Memory setting information generating module, is used for generating memory setting information, described memory setting information bag
Include target memory address realm and described desired value；
Sending module, for sending described memory setting information to Memory Controller Hub, so that described internal memory control
Device processed according to described memory setting information by target area corresponding for target memory address realm described in internal memory
Value be set to described desired value.
Memory access the most according to claim 8 controls device, it is characterised in that described original internal memory ground
The address of location Range Representation is virtual address；
Described memory setting information generating module obtains specifically for described virtual address is converted to physical address
Obtain described target memory address realm and generate memory setting information.
The most according to claim 8 or claim 9, memory access control device, it is characterised in that also includes:
Cache coherence processing unit, for the described target memory address that will store in cache
The value of the target area that scope is corresponding carries out writing back or invalid.
11. memory access according to claim 10 control device, it is characterised in that also include:
Receiver module, for receiving the label information that described Memory Controller Hub returns, described label information is
Described Memory Controller Hub returns to the information of described processor after successfully arranging internal memory.
12. memory access according to claim 11 control device, it is characterised in that also include:
Interrupt module, produces after described receiver module receives described label information and interrupts.
13. 1 kinds of Memory Controller Hub, it is characterised in that including:
Memory setting information receiving module, for receiving the memory setting information that processor sends, described interior
Depositing configuration information and include target memory address realm and described desired value, described memory setting information is described
Processor perform described memory setting instruction after generate information, described memory setting instruction include order code,
Original memory address range and described desired value, described order code is the mark letter of described memory setting instruction
Breath；
Memory setting module, is used for target memory address described in internal memory according to described memory setting information
The value of the target area that scope is corresponding is set to described desired value.
14. Memory Controller Hub according to claim 13, it is characterised in that also include:
Label information sending module, for described processor return label information, described label information is used
In representing that described Memory Controller Hub successfully arranges internal memory.
15. 1 kinds of memory access control systems, it is characterised in that include internal memory, as arbitrary in claim 8-12
Memory access described in Xiang controls the Memory Controller Hub described in device and claim 13 or 14.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111949317A (en) * | 2019-05-17 | 2020-11-17 | 上海寒武纪信息科技有限公司 | Instruction processing method and device and related product |
| CN111949318A (en) * | 2019-05-17 | 2020-11-17 | 上海寒武纪信息科技有限公司 | Instruction processing method and device and related product |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020144244A1 (en) * | 2001-03-30 | 2002-10-03 | Rakesh Krishnaiyer | Compile-time memory coalescing for dynamic arrays |
| CN102981886A (en) * | 2012-12-21 | 2013-03-20 | 中国科学院声学研究所 | Method for generating optimized memset standard library function assembly code |
| CN103827834A (en) * | 2013-11-22 | 2014-05-28 | 华为技术有限公司 | Migration method of in-memory data, computer and device |
| CN104252422A (en) * | 2013-06-26 | 2014-12-31 | 华为技术有限公司 | Memory access method and memory controller |
| CN104346285A (en) * | 2013-08-06 | 2015-02-11 | 华为技术有限公司 | Memory access processing method, device and system |
| CN105426322A (en) * | 2015-12-31 | 2016-03-23 | 华为技术有限公司 | Data prefetching method and device |
-
2016
- 2016-03-28 CN CN201610184196.3A patent/CN105867847B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020144244A1 (en) * | 2001-03-30 | 2002-10-03 | Rakesh Krishnaiyer | Compile-time memory coalescing for dynamic arrays |
| CN102981886A (en) * | 2012-12-21 | 2013-03-20 | 中国科学院声学研究所 | Method for generating optimized memset standard library function assembly code |
| CN104252422A (en) * | 2013-06-26 | 2014-12-31 | 华为技术有限公司 | Memory access method and memory controller |
| CN104346285A (en) * | 2013-08-06 | 2015-02-11 | 华为技术有限公司 | Memory access processing method, device and system |
| CN103827834A (en) * | 2013-11-22 | 2014-05-28 | 华为技术有限公司 | Migration method of in-memory data, computer and device |
| CN105426322A (en) * | 2015-12-31 | 2016-03-23 | 华为技术有限公司 | Data prefetching method and device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111949317A (en) * | 2019-05-17 | 2020-11-17 | 上海寒武纪信息科技有限公司 | Instruction processing method and device and related product |
| CN111949318A (en) * | 2019-05-17 | 2020-11-17 | 上海寒武纪信息科技有限公司 | Instruction processing method and device and related product |
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