CN105095138A - Method and device for expanding synchronous memory bus function - Google Patents
Method and device for expanding synchronous memory bus function Download PDFInfo
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- CN105095138A CN105095138A CN201510369681.3A CN201510369681A CN105095138A CN 105095138 A CN105095138 A CN 105095138A CN 201510369681 A CN201510369681 A CN 201510369681A CN 105095138 A CN105095138 A CN 105095138A
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Abstract
The invention relates to the field of computers. The invention provides a method and device for expanding a synchronous memory bus function. The device comprises a processor, an auxiliary access module and an extended memory controller. The processor is used for generating a memory access request, and sending the memory access request to the auxiliary access module. The auxiliary access module is used for determining whether the memory access request is to access a system memory or expend a memory according to the address attribute information contained in the memory access request, sending the memory access request to a memory controller if the memory access request is to access the system memory, otherwise, generating an access request whose target address is the extended memory controller. The extended memory controller is used for sending an access expanded memory request generated by the auxiliary access module to a memory expanded chip. The method and device can distinguish an expanded memory access request, and can replace a processor to interact an expanded memory controller, the efficiency of access can be raised.
Description
Technical field
The present invention relates to computer realm, particularly relate to a kind of method and apparatus expanding isochronous memory bus functionality.
Background technology
Along with the evolution in multinuclear epoch and the arriving of large data age, computer system is constantly strengthened for the demand of Large Copacity internal memory.Multiple concurrent application can be put and be run on a single die by polycaryon processor, the internal memory of needs i.e. the summation of all application data demands.And the most emerging take Spark as the internal memory computation schema of representative, when processing large market demand, can attempt working set memory-resident, to avoid disk operating slowly.This all illustrates that Large Copacity internal memory has become the deciding factor affecting performance.
In recent years with Memister (RRAM, Resistiverandom-accessmemory), ferroelectric memory (FeRAM, Ferroelectricrandom-accessmemory), phase transition storage (PCM, etc. PhaseChangeMemory) be the emerging non-volatile random storage medium (NVM of representative, Non-volatilememory) access performance is at Step wise approximation dynamic RAM (DRAM, DynamicRandomAccessMemory).The thought designing novel mixing memory hierarchy based on novel memory devices part and traditional DRAM also gradually accept by people.Isomery storage significantly can promote memory size under the prerequisite keeping cost and energy demand advantages, and the I/O performance overcome between internal memory and external memory is not mated, and will become the important thinking optimizing large data processing.
Can find out through above analysis, memory system all faces higher requirement in capacity, medium etc., needs constantly to expand.But transmit the industrywide standard SDRAM (SynchronousDynamicRandomAccessMemory of data between processor and internal memory, synchronous dynamic random access memory) bus employing fixed time sequence access memory particle, and fixing operating lag is unfavorable for that realizing capacity cascade expands, also bring difficulty to building mixing memory system.
In order to solve problems of the prior art, existing technology connects by extended chip the expansion that multiple memory chip or other storage mediums realize capacity.Be described according to Fig. 1 below, Fig. 1 comprises processor (Processor) 101, Installed System Memory 102, memory expansion chip 103, and exented memory 104, wherein, processor 1011 is integrated with, Memory Controller Hub 1012 and I/O controller 1013, wherein in processor system 101, inner at processor system 101, processor 1011 is connected by on-chip bus 1014 with Memory Controller Hub 1012 and I/O controller 1013.Installed System Memory 102 is connected with processor system 101 by rambus 105, exented memory 104 is connected with memory expansion chip 103 by rambus 105, and processor system 101 can adopt various ways bus to be connected by I/O controller 1012 and memory expansion chip 103.
The implementation of prior art one adopts interconnection between I/O bus or processor to come connection handling device system 101 and memory expansion chip 103, conventional bus is PCI-E (PeripheralComponentInterconnectExpress, high speed peripheral component interlinkage standard), IntelQPI (QuickPathInterconnect, FASTTRACK) or AMDHT (HyperTransport, Hyper Transport) bus.Adopt above-mentioned bus, the problem that delay is larger can be there is, and need to carry out meticulous the pipeline design, the delay of accessing with this obfuscated data to internal memory extended chip 103.In addition, because memory expansion chip have employed different I/O buses, compatibility issue is there is between processor meeting and memory expansion chip, such as based on the server system that arm processor is built, if there is no the mandate of Intel, just cannot by the capacity of IntelQPI memory expansion chip Extended RAM system.
The implementation of prior art two adopts rambus to come connection handling device system 101 and memory expansion chip 103, adopt rambus 105 that memory expansion chip 103 and processor system 101 can be made directly can to share exented memory 104, the delay of memory access is less, has also possessed better compatibility.But in prior art two, also there are the following problems: owing to there is memory expansion chip 103 between processor system 101 and exented memory 104, after processor system 101 sends the memory access request conducted interviews to the data in exented memory 104, after integrated memory controller 1011 accepts this memory access request, when adopting DDR protocol access exented memory 104, the existence of memory expansion chip 103 brings extra time delay, the result of memory access request cannot be returned according in the time delay of DDR protocol requirement, thus affect the feasibility that above computer system accesses exented memory 104.In order to solve the problem of time delay, prior art two generally adopts the mode of the time sequence parameter of amendment Memory Controller Hub, namely by modifying to the time sequence parameter of the integrated Memory Controller Hub in processor inside, the time sequence parameter of processor is made to be greater than internal memory physical memory access delay, but the maximum time sequence parameter due to processor support arranges and is limited in scope, be difficult to compensate access delay extra in access extended memory process.
Summary of the invention
For the deficiencies in the prior art, the present invention proposes a kind of method and apparatus expanding isochronous memory bus functionality.
The present invention also proposes a kind of device expanding isochronous memory bus functionality, comprising:
Processor, auxiliary memory access module, exented memory controller;
Wherein, described memory access request for generating memory access request, and is sent to auxiliary memory access module by processor;
Described auxiliary memory access module, for according to the address properties information comprised in described memory access request, judge that described memory access request is access system internal memory or exented memory, if access described Installed System Memory, then described memory access request is sent to Memory Controller Hub, if access extended memory, then generate the access request that destination address is exented memory controller;
Described exented memory controller, for receiving the access request that described destination address is exented memory controller, and issues exented memory by described request of access.
The device of described expansion isochronous memory bus functionality, described auxiliary memory access module, also for judging whether access extended memory terminates according to returning results of described exented memory controller, if described in return results into except exception flag data except data, then described returning results is issued processor, otherwise the new destination address of regeneration one is the access request of described exented memory controller.
The device of described expansion isochronous memory bus functionality, described auxiliary memory access module also comprises token counter, the initial value of described token counter is set to the cacheable maximum write request number of exented memory controller, after described auxiliary memory access module sends a write request, the value of described token counter subtracts 1, after the value of described token counter reduces to 0, described auxiliary memory access module just stops the write request of receiving processor access extended memory; Token release counter, at exented memory controller, the write request data of buffer memory are write after in exented memory by described exented memory controller, the value of described token release counter adds 1, token release counter described in described auxiliary memory access module timer access, and recover the value of described token counter.
The device of described expansion isochronous memory bus functionality, described Memory Controller Hub is used for according to the address properties information comprised in described memory access request, judge described memory access request access system internal memory or exented memory, when being defined as access system internal memory, described memory access request is sent to described Installed System Memory, when being defined as accessing described exented memory, described memory access request is sent to described exented memory controller.
The device of described expansion isochronous memory bus functionality, exented memory controller at least comprises execution module, for performing the read operation to data to be visited in described exented memory; Data buffer, reads data to be visited for temporary described execution module from described exented memory;
Wherein execution module often receives the request of a described exented memory of access, the data of needs whether are saved in data buffer described in priority check, if had, on rambus, then directly return the data of described needs, otherwise return an exception flag data, and access described exented memory, by the data that get stored in described data buffer.
The device of described expansion isochronous memory bus functionality, also comprise on-chip bus, described on-chip bus support request is out of order to be returned, and each read request of request promoter attaches a request marks, the request marks of simultaneously asking belonging to return data when request recipient's return data time.
The present invention also proposes a kind of method being implemented on the expansion isochronous memory bus functionality of apparatus of the present invention, comprising:
Step 1, generates memory access request, and described memory access request is sent to auxiliary memory access module;
Step 2, according to the address properties information comprised in described memory access request, judge that described memory access request is access system internal memory or exented memory, if access described Installed System Memory, then described memory access request is sent to Memory Controller Hub, if access extended memory, then generate the access request that destination address is exented memory controller;
Step 3, exented memory controller receives the access request that described destination address is exented memory controller, and described request of access is issued exented memory.
The method of described expansion isochronous memory bus functionality, described step 2 also comprises and judges whether access extended memory terminates according to returning results of described exented memory controller, if described in return results into except exception flag data except data, then described returning results is issued processor, otherwise the new destination address of regeneration one is the access request of described exented memory controller.
The method of described expansion isochronous memory bus functionality, also comprises the operational data stored in described processor implementation.
The method of described expansion isochronous memory bus functionality, also comprise: the request often receiving a described exented memory of access, the data of needs whether are saved in data buffer described in priority check, if had, on rambus, then directly return the data of described needs, otherwise return an exception flag data, and access described exented memory, by the data that get stored in described data buffer.
From inventing above, the invention has the advantages that:
Auxiliary memory access module is a hardware module supporting standard on-chip bus, can insert between processor and Memory Controller Hub easily and without the need to revising other modules.The access request of auxiliary memory access module monitors processor, identify the request that belongs to access extended memory and replace processor and memory expansion chip mutual, running that software on a processor need not revise just can access extended memory and not mating without the need to consideration delay smoothly, and bandwidth such as not to mate at the problem.Adopt the solution of the present invention, namely the processor of different model can be applied to (as long as which provide standard SDRAM interface, as DDR, DDR2, DDR3, DDR4 etc.), memory expansion chip also can connect the storage resources of different medium, builds the memory subsystem of high extended capability under being widely used in various scene.
Accompanying drawing explanation
Fig. 1 existing exented memory device schematic diagram;
The structural representation of the device of isochronous memory bus functionality is expanded in Fig. 2 the present invention;
Fig. 3 assists the process flow diagram of memory access resume module read request;
Fig. 4 assists the memory access resume module process flow diagram of read request on medium at a slow speed;
The process flow diagram of Fig. 5 exented memory controller process read request;
Fig. 6 assists the process flow diagram of memory access CMOS macro cell prefetch request;
The process flow diagram of Fig. 7 exented memory controller process prefetch request;
Fig. 8 assists memory access module to use the process flow diagram of token counter;
Fig. 9 exented memory controller uses the process flow diagram of token release counter;
Figure 10 assists the process flow diagram of memory access resume module fence instruction;
Figure 11 assists the structural representation of memory access module embodiments.
Embodiment
Clearly understand to make object of the present invention, technical scheme and advantage, below in conjunction with drawings and Examples, a kind of method and apparatus expanding isochronous memory bus functionality of the present invention is further elaborated, be to be understood that, specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
General, program module comprises the structure of routine, program, assembly, data structure and the other types performing particular task or realize particular abstract data type.In addition, it will be appreciated by those skilled in the art that, each embodiment can be implemented by other computer system configurations, comprise portable equipment, multicomputer system, based on microprocessor or programmable consumer electronics, small-size computer, mainframe computer and similar computing equipment, realize in the distributed computing environment that each embodiment can also be performed by the remote processing devices connected by communication network in task, in a distributed computing environment, program module can be arranged in local and remote memory storage device.
Each embodiment can be implemented as the computer-readable storage medium that computer implemented process, computing system or such as computer program or computer system perform the computer program of the request of instantiation procedure.Such as: computer-readable recording medium can realize via one or more in volatile computer memories, nonvolatile memory, hard disk drive, flash drive, floppy disk or compact-disc (CompactDisc) and similar mediums.
Run through this instructions, term " processor (Processor) " is the CPU (central processing unit) of computer system, be used for the memory access request generated in receiving target program process, address according to data to be visited generates memory access request, and memory access request is sent to Memory Controller Hub.
Run through this instructions, term " auxiliary memory access module " is referred to and is connected by on-chip bus interface & processor and Memory Controller Hub, the request of access of monitoring processor access exented memory, is translated into a series of access requests of access extended memory controller.
Run through this instructions, term " Memory Controller Hub (MemoryController) " is the computer module that inside computer system controls internal memory, makes by Memory Controller Hub the exchange can carrying out data between internal memory and processor.Wherein, " Memory Controller Hub " in this instructions is used to realize controlling the access of Installed System Memory (SystemMemory).
Run through this instructions, term " on-chip bus (On-ChipBus) " is the data bus that processor system inside connects modules.
Run through this instructions, term " exented memory controller " is referred to and is connected with Memory Controller Hub by memory interface, as the bridge that processor conducts interviews to exented memory.
Run through this instructions, term " exented memory " refers to the storer connected by memory expansion chip, is used for realizing the expansion of internal memory.Exented memory can adopt following form but be not limited to following form and realize, for example: DRAM (DynamicRandomAccessMemory, dynamic RAM), PCM (Phase-ChangeMemory, phase transition storage) and MRAM (MagneticRandomAccessMemory, magnetic RAM) etc.
Run through this instructions, term " memory access request ", again referred to as " access request ", refer to source code (SourceCode) when obtaining that institute comprises the access requests such as Load/Store in object code (ObjectCode) by compiling (Compile), processor just needs these access requests.In the process performed, processor needs by virtual address (VirtualAddress) to physical address (PhysicalAddress) transfer process, be physical address by the virtual address translation in access request, and generate memory access request, send to Memory Controller Hub (MemoryController) to perform.
Run through this instructions, term " memory access request ", again referred to as " access request ", refer to the request that the data in internal memory are conducted interviews generated after access request being performed by processor.Access request comprises: read request and write request.
Run through this instructions, term " data buffer " refers to the memory device for storing the data to be visited read from exented memory, can be integrated in exented memory controller inner, also independently can realize with exented memory controller.
In order to the contradiction between both low delay sequential that long delay when overcoming access extended memory and standard SDRAM ask, the present invention utilizes multiple access request to carry out the read request of an exented memory, if exented memory controller is not ready for data, just return an exception flag data and represent that current SDRAM read request does not obtain True Data, processor system is needed to send a read request again to exented memory controller, and consider the easy and compatible of software programming, the present invention adds an auxiliary memory access module in processor system, software code is only needed to send a request of access, after auxiliary memory access module sees this exented memory read request, by this CMOS macro cell and manage access extended memory all the other request, simultaneously in order to reduce the number of requests required for each access extended memory, return auxiliary memory access module and add pre-fetch function.
For the write request of access extended memory, because SDRAM write request does not need response, so there is no the problem asking to return delay, but due to exented memory write bandwidth sum write delay generalized case all cannot mate rambus write bandwidth sum postpone requirement, need the data temporary storage of write request in the data buffer of exented memory controller, this just requires between processor and exented memory, to realize a flow-control mechanism to ensure that data buffer can not receive new write request again after being occupied full, the present invention is provided with a token counter in auxiliary memory access module, initial value is set to the cacheable maximum write request number of exented memory controller, such as 16, after auxiliary memory access module sends a write request, token counter just subtracts 1, when token counter to reduce to after 0 the write request of auxiliary memory access module just no longer receiving processor access extended memory, a token release counter is set in exented memory controller, the write request data of a buffer memory are really write after in exented memory by exented memory controller, token release counter just adds 1, the value of token counter is recovered after auxiliary memory access module timer access token release counter.
Be below system hardware framework corresponding to the embodiment of the present invention, as follows:
Before introducing the specific embodiment of the invention, first corresponding to embodiment of the present invention system hardware composition structure is introduced, and referring to Fig. 2, comprises following assembly:
Processor system (ProcessingSystem) 201: comprise processor 2011, auxiliary memory access module 2012, Memory Controller Hub 2013 and on-chip bus 2014.As the executive module of request, in embodiment provided by the present invention, processor system 201 is used for receiving the memory access request that generates in the process of implementation of executable program, and generates memory access request according to memory access request.
Wherein, processor 2011, for processing internal storage access (MemoryAccess) request, generates memory access request, and memory access request is sent to auxiliary memory access module 2012.
Auxiliary memory access module 2012 is according to the address properties information comprised in memory access request, and judgement is access system internal memory 202 or exented memory 204, when determining to be access system internal memory 202, memory access request is sent to Memory Controller Hub 2013; When determining to be access extended memory 204, generate the access request that an objective address is exented memory controller 203, judge whether access extended memory terminates according to the result that exented memory controller 2013 returns, if returning results is not an exception flag data, illustrate that request terminates, to return results and issue processor 2011, otherwise the new destination address of regeneration one is the access request of exented memory controller 2013.
Memory Controller Hub 2013 is according to the position attribution information comprised in memory access request, and judgement is access system internal memory 202 or exented memory 204, when determining to be access system internal memory 202, memory access request is sent to Installed System Memory 202; When determining to be access extended memory 204, memory access request is sent to exented memory controller 203.
On-chip bus 2014 is supported that request is out of order and is returned, each read request of request promoter attaches a request marks, also to return the request marks of asking belonging to these data, so that request promoter judges the return data that have received which request when request recipient's return data time simultaneously.
Installed System Memory (Memory) 202: refer to the storer be directly connected with processor system 201 by rambus 205, is used for temporary transient storage of processor system 201 operational data in the process of implementation.
Exented memory controller (ExtendedMemoryController) 203: for receiving the access request that described destination address is exented memory controller, and described request of access is issued exented memory, described exented memory controller, for connecting exented memory 204, carries out the bridge of internal storage access process as processor system 201 pairs of exented memories 204.In exented memory controller 203, at least comprise as lower module: execution module 2031, be used for performing read operation to data to be visited in exented memory, and data buffer 2032, be used for the data to be visited that temporary execution module 2031 reads from exented memory 204.Execution module 2031 often receives the request of an access extended memory 204, the data of needs whether are saved in priority check data buffer 2032, if had, then on rambus 205, directly return these data, otherwise return an exception flag data, and access extended memory 204, by the data got stored in data buffer 2032.
Exented memory (ExtendedMemory) 204: refer to and be different from Installed System Memory 202, the storer as expansion uses, for the operational data in storage of processor 201 implementation.Exented memory 204 can adopt different storage mediums to realize, for example: DRAM (DynamicRandomAccessMemory, dynamic RAM), PCM (Phase-ChangeMemory, phase transition storage) and MRAM (MagneticRandomAccessMemory, magnetic RAM) etc.
Rambus (MemoryBus) 205 is buses that Installed System Memory 202 and exented memory controller 203 are connected with processor system 201, the bus of these types includes but not limited to: DDR (DoubleDataRate, Double Data Rate) bus, LPDDR (LowPowerDDR, low-power consumption DDR) bus or WideI/O bus.
Access memory request in the present invention, access system internal memory 202 and access extended memory 204 two kinds is divide into according to its address properties information comprised, there is different treatment schemees respectively, the address properties information of access memory request is determined when program source code being translated into machine code by compiler (compiler), this requires that program increases a statement when defining variable for the variable being stored in exented memory 204, and compiler will distribute the address of this variable in the address space of exented memory 204 after identifying this statement.
The present invention also proposes a kind of method being implemented on the expansion isochronous memory bus functionality of apparatus of the present invention, comprising:
Step 1, generates memory access request, and described memory access request is sent to auxiliary memory access module;
Step 2, according to the address properties information comprised in described memory access request, judge that described memory access request is access system internal memory or exented memory, if access described Installed System Memory, then described memory access request is sent to Memory Controller Hub, if access extended memory, then generate the access request that destination address is exented memory controller;
Step 3, exented memory controller receives the access request that described destination address is exented memory controller, and described request of access is issued exented memory.
Also comprise the operational data stored in described processor implementation.
Often receive the request of a described exented memory of access, the data of needs whether are saved in data buffer described in priority check, if had, on rambus, then directly return the data of described needs, otherwise return an exception flag data, and access described exented memory, by the data that get stored in described data buffer.
Described step 2 also comprises and judges whether access extended memory terminates according to returning results of described exented memory controller, if described in return results into except exception flag data except data, then described returning results is issued processor, otherwise the new destination address of regeneration one is the access request of described exented memory controller.
Be below embodiment of the method for the present invention, as follows:
Fig. 3 is the processing procedure after auxiliary memory access module receives the memory access read request that processor sends, and as shown in Figure 3, described method, comprises the following steps:
Step 301, auxiliary memory access module receives the access request of processor from on-chip bus, request ID is i, and reference address is a;
Step 302, judges whether a belongs to exented memory space, if so, then performs step 303, otherwise performs step 310;
Step 303, the access request that auxiliary memory access CMOS macro cell one is new, request ID is i+1, and reference address is a, mails to Memory Controller Hub;
Step 304, receiving the request ID that Memory Controller Hub sends is the return data of i+1;
Step 305, judges whether return data equals exception flag data 1 (as 0x5a5a5a5a5a5a5a), if so, then performs step 306, otherwise performs step 309;
Step 306, waits for pre-set time (storage medium depending on exented memory), the access request that auxiliary memory access CMOS macro cell one is new, and request ID is i+2, and reference address is a, mails to Memory Controller Hub;
Step 307, receiving the request ID that Memory Controller Hub sends is the return data of i+2;
Step 308, judges whether return data equals exception flag data 2 (as 0xffff0000ffff0000), if so, then performs step 303, otherwise performs step 309;
Step 309, auxiliary memory access module is using the return data of return data as request i, and mail to processor, request ends process;
Step 310, request ID is i by auxiliary memory access module, and reference address is that Memory Controller Hub is mail in the request of a;
Step 311, receiving the request ID that Memory Controller Hub sends is the return data of i, and the return data as request i mails to processor, and request ends process.
For some scene, such as exented memory is the dram chip of low delay, new request can in addition before request return before just send, postpone to reduce bulk treatment, Fig. 4 is the fast processing process after auxiliary memory access module receives the memory access read request that processor sends, as shown in Figure 4, described method, comprises the following steps:
Step 401, auxiliary memory access module receives the request of low delay storage medium processor access exented memory space from on-chip bus, request ID is i, and reference address is a;
Step 402, the access request that auxiliary memory access CMOS macro cell one is new, request ID is i+1, and reference address is a, mails to Memory Controller Hub;
Step 403, auxiliary memory access module waits for a pre-set time, and generates a new access request, ask ID to be i+2, reference address is a, mails to Memory Controller Hub;
Step 404, receiving the request ID that Memory Controller Hub sends is the return data of i+1;
Step 405, judges whether return data equals the flag data 1 that makes an exception, and if so, then performs step 406, otherwise performs step 408;
Step 406, receiving the request ID that Memory Controller Hub sends is the return data of i+2;
Step 407, judges whether return data equals the flag data 1 that makes an exception, and if so, then performs step 402, otherwise performs step 408;
Step 408, auxiliary memory access module is using the return data of return data as request i, and mail to processor, request ends process.
Fig. 5 is the processing procedure after exented memory controller receives the access request that Memory Controller Hub sends, and as shown in Figure 5, described method, comprises the following steps:
Step 501, exented memory controller receives the access request of Memory Controller Hub from rambus, and reference address is a;
Step 502, execution module judges that the data of address a are whether in data buffer, if so, then perform step 511, otherwise perform step 503;
Step 503, execution module judges whether that first time receives the access request of address a, if so, then performs step 504, otherwise performs step 505;
Step 504, execution module sends the request of reference address a to exented memory;
Step 505, exception flag data 1 is issued Memory Controller Hub as return data by execution module;
Step 506, exented memory controller receives the access request of Memory Controller Hub from rambus, and reference address is a;
Step 507, execution module judges that the data of address a are whether in data buffer, if so, then perform step 511, otherwise perform step 508;
Step 508, exception flag data 2 is issued Memory Controller Hub as return data by execution module;
Step 509, exented memory controller receives the access request of Memory Controller Hub from rambus, and reference address is a;
Step 510, execution module judges that the data of address a are whether in data buffer, if so, then perform step 511, otherwise perform step 505;
Step 511, the data of the address a of buffer memory in data buffer are issued Memory Controller Hub as return data by execution module, and request ends process.
Fig. 6 is the processing procedure that auxiliary memory access module sends access request of looking ahead, and as shown in Figure 6, described method, comprises the following steps:
Step 601, auxiliary memory access module have received the request in the access extended memory space that N continuous (N can sets itself, be usually more than or equal to 2) individual sequence of addresses increases progressively from processor;
Step 602, auxiliary memory access module produces a prefetch request, address a, and length is l, and the address that wherein a equals N number of request adds 64 bytes, and l can the length of a page, also can be the length of a line in data buffer;
Step 603, auxiliary memory access module produces a write request, and request address is the prefetch register address of exented memory controller, and the data that write are the values be stitched together by a and l;
Step 604, the request of neotectonics is mail to Memory Controller Hub by auxiliary memory access module, and operation terminates.
Fig. 7 is the processing procedure after exented memory controller receives access request of looking ahead, and as shown in Figure 7, described method, comprises the following steps:
Step 701, exented memory controller receives a write request, and request address is the prefetch register address of exented memory controller.
Step 702, execution module goes out the address a and length l that will look ahead from the extracting data of writing of request;
Step 703, execution module constantly accesses the exented memory wanting prefetch data to be positioned at, and is that the data of l are stored in data buffer by length;
Step 704, operation terminates.
Fig. 8 is that auxiliary memory access module is receiving for token counter processing procedure separately under read request or write request two kinds of scenes, and as shown in Figure 8, described method, comprises the following steps:
Step 801, auxiliary memory access module have received the request in access extended memory space from processor;
Step 802, judges whether request is write request, if so, then performs step 803, otherwise performs step 806;
Step 803, judges whether the value i of token counter is 0, if so, then performs step 804, otherwise performs step 805;
Step 804, auxiliary memory access module reads the token release counter of exented memory controller, and obtain j, make i=i+j, the value upgrading token counter is i, performs step 803;
Step 805, auxiliary memory access module token counter subtracts 1, and write request is dealt into Memory Controller Hub, performs step 809;
Step 806, is dealt into Memory Controller Hub read request, receives the request return data that Memory Controller Hub is sent;
Step 807, judges whether return data is exception flag data, if so, then performs step 808, otherwise performs step 809;
Step 808, obtains the currency j of token release counter, is added on the currency i of token counter, obtains new result i+j, upgrade token counter, perform step 809 from exception flag data;
Step 809, auxiliary memory access module terminates the process to token counter.
Fig. 9 is that exented memory controller is receiving the processing procedure for token release counter under read request or write request two kinds of scenes, and as shown in Figure 9, described method, comprises the following steps:
Step 901, exented memory controller have received the request in access extended memory space from processor;
Step 902, judges that whether ask is the request that access token discharges counter, if so, then performs step 903, otherwise performs step 906;
Step 903, the value of token release counter returns to Memory Controller Hub, performs step 905;
Step 904, the data of token release counter merge with exception flag data, return to Memory Controller Hub;
Step 905, token release counter is set as 0, and operation terminates;
Step 906, judges whether request is write request, if so, then performs step 909, otherwise performs step 907;
Step 907, judges read request desired data whether in data buffer, if so, then performs step 908, otherwise performs step 904;
Step 908, takes data away from data buffer and returns to Memory Controller Hub, and operation terminates;
Step 909, writes data buffer by request msg;
Whether step 910, judge that exented memory is current and can write, and if so, then performs step 912, otherwise perform step 911;
Step 911, waits for the pre-set time, prepares access extended memory again, performs step 910;
Step 912, reads request msg from data buffer, write exented memory;
Step 913, token release counter adds 1, and operation terminates.
Fence request is a kind of synchronization request that current processor has supported for local system internal memory, before can fence being ensured write access request all process be over after perform fence again after write access request, the present invention utilizes token counter to achieve a kind of fence towards exented memory and asks, Figure 10 is that auxiliary memory access module receives the processing procedure of fence request from processor, as shown in Figure 10, described method, comprises the following steps:
Step 1010, auxiliary memory access module receives fence request from processor;
Step 1020, the also untreated request received before fence is all issued Memory Controller Hub by auxiliary memory access module;
Step 1030, the request received from processor is afterwards cached by auxiliary memory access module, does not temporarily issue Memory Controller Hub;
Step 1040, judges whether the value i of token counter is max, if so, then performs step 1050, otherwise performs step 1070;
Step 1050, auxiliary memory access module reads the token release counter of exented memory controller;
Step 1060, auxiliary memory access module reads the token release counter of exented memory controller, and obtain j, make i=i+j, the value upgrading token counter is i, performs step 1040;
Step 1070, auxiliary memory access module terminates the process of sfence, and Memory Controller Hub is issued in the request of buffer memory, and operation terminates.
Apparatus embodiments of the present invention, as follows:
Present invention also offers the apparatus embodiments of auxiliary memory access module, referring to Figure 11, be applied to the access of processor to exented memory of computing machine, described auxiliary memory access module is connected to described processor and Memory Controller Hub by on-chip bus, and this auxiliary memory access module comprises:
Judge module 1110, for all access requests that receiving processor sends, according to Installed System Memory or exented memory that the address judgement of access request is access, if exented memory, just request forward is done further process to exented memory request generation module, if Installed System Memory, be then directly transmitted to Memory Controller Hub.Also all request ID do not completed to be issued request response processing module simultaneously.
Exented memory request generation module 1120, for the treatment of the access request of all access extended memory received, mainly contains three functions: one is the request generating access extended memory; Two is the response results receiving access extended memory request, and does further process according to result; Three is the sequence rules of monitoring processor access exented memory, suitably produces some prefetch request and issues exented memory controller.
Request response processing module 1130, for receiving the response data of the access request that Memory Controller Hub returns.Maintain all access request ID confiscating response message in module, if Memory Controller Hub returns the request response of an Installed System Memory request of access, just it is directly passed to processor; If Memory Controller Hub returns the request response of an exented memory request of access, be just transmitted to exented memory request generation module.
Claims (10)
1. expand a device for isochronous memory bus functionality, it is characterized in that, comprising:
Processor, auxiliary memory access module, exented memory controller;
Wherein, described memory access request for generating memory access request, and is sent to auxiliary memory access module by processor;
Described auxiliary memory access module, for according to the address properties information comprised in described memory access request, judge that described memory access request is access system internal memory or exented memory, if access described Installed System Memory, then described memory access request is sent to Memory Controller Hub, if access extended memory, then generate the access request that destination address is exented memory controller;
Described exented memory controller, for receiving the access request that described destination address is exented memory controller, and issues exented memory by described request of access.
2. the device of expansion isochronous memory bus functionality as claimed in claim 1, it is characterized in that, described auxiliary memory access module, also for judging whether access extended memory terminates according to returning results of described exented memory controller, if described in return results into except exception flag data except data, then described returning results is issued processor, otherwise the new destination address of regeneration one is the access request of described exented memory controller.
3. the device of expansion isochronous memory bus functionality as claimed in claim 1, it is characterized in that, described auxiliary memory access module also comprises token counter, the initial value of described token counter is set to the cacheable maximum write request number of exented memory controller, after described auxiliary memory access module sends a write request, the value of described token counter subtracts 1, and after the value of described token counter reduces to 0, described auxiliary memory access module just stops the write request of receiving processor access extended memory; Token release counter, at exented memory controller, the write request data of buffer memory are write after in exented memory by described exented memory controller, the value of described token release counter adds 1, token release counter described in described auxiliary memory access module timer access, and recover the value of described token counter.
4. the device of expansion isochronous memory bus functionality as claimed in claim 1, it is characterized in that, described Memory Controller Hub is used for according to the address properties information comprised in described memory access request, judge described memory access request access system internal memory or exented memory, when being defined as access system internal memory, described memory access request being sent to described Installed System Memory, when being defined as accessing described exented memory, described memory access request being sent to described exented memory controller.
5. the device of expansion isochronous memory bus functionality as claimed in claim 1, it is characterized in that, exented memory controller at least comprises execution module, for performing the read operation to data to be visited in described exented memory; Data buffer, reads data to be visited for temporary described execution module from described exented memory;
Wherein execution module often receives the request of a described exented memory of access, the data of needs whether are saved in data buffer described in priority check, if had, on rambus, then directly return the data of described needs, otherwise return an exception flag data, and access described exented memory, by the data that get stored in described data buffer.
6. the device of expansion isochronous memory bus functionality as claimed in claim 1, it is characterized in that, also comprise on-chip bus, described on-chip bus support request is out of order to be returned, each read request of request promoter attaches a request marks, the request marks of simultaneously asking belonging to return data when request recipient's return data time.
7. be implemented on a method for the expansion isochronous memory bus functionality as claim 1 device, it is characterized in that, comprising:
Step 1, generates memory access request, and described memory access request is sent to auxiliary memory access module;
Step 2, according to the address properties information comprised in described memory access request, judge that described memory access request is access system internal memory or exented memory, if access described Installed System Memory, then described memory access request is sent to Memory Controller Hub, if access extended memory, then generate the access request that destination address is exented memory controller;
Step 3, exented memory controller receives the access request that described destination address is exented memory controller, and described request of access is issued exented memory.
8. the method for expansion isochronous memory bus functionality as claimed in claim 7, it is characterized in that, described step 2 also comprises and judges whether access extended memory terminates according to returning results of described exented memory controller, if described in return results into except exception flag data except data, then described returning results is issued processor, otherwise the new destination address of regeneration one is the access request of described exented memory controller.
9. the method for expansion isochronous memory bus functionality as claimed in claim 7, is characterized in that, also comprise the operational data stored in described processor implementation.
10. the method for expansion isochronous memory bus functionality as claimed in claim 7, it is characterized in that, also comprise: the request often receiving a described exented memory of access, the data of needs whether are saved in data buffer described in priority check, if had, then on rambus, directly return the data of described needs, otherwise return an exception flag data, and access described exented memory, by the data that get stored in described data buffer.
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