CN105845726A - Fully-wrapped gate field effect transistor and manufacturing method thereof - Google Patents
Fully-wrapped gate field effect transistor and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000002353 field-effect transistor method Methods 0.000 title 1
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- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000005669 field effect Effects 0.000 claims abstract description 20
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 18
- 229910052760 oxygen Inorganic materials 0.000 description 18
- 239000001301 oxygen Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- 238000003475 lamination Methods 0.000 description 3
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- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
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Abstract
The invention discloses a method for manufacturing a fully-enclosed gate field effect transistor, which comprises the following steps: providing an SOI substrate, wherein a fin is formed in top silicon; forming a pseudo gate device on the fin, and covering two sides of the pseudo gate to form an interlayer dielectric layer; removing the dummy gate to form an opening; removing the buried oxide layer with the thickness of the lower part of the opening to release the fin in the opening; a gate is formed in the opening surrounding the fin. The method is compatible with the existing device integration process, does not need additional supporting parts, and is easy to improve the integration level.
Description
Technical field
The invention belongs to field of manufacturing semiconductor devices, particularly relate to a kind of all-around-gate field effect transistor
Pipe and manufacture method thereof.
Background technology
Highly integrated along with semiconductor device, MOSFET channel length constantly shortens, a series of
In MOSFET long raceway groove model, negligible effect becomes more notable, even becomes and affects device
The leading factor of energy, this phenomenon is referred to as short-channel effect.Short-channel effect can deteriorate the electrical property of device
Can, as caused threshold voltage of the grid decline, power consumption to increase and degradation problem under signal to noise ratio.
In order to overcome short-channel effect, it is proposed that all-around-gate (AAWG, All Around Wrapped Gate)
Field-effect transistor, i.e. grid surround nano wire (nanowire) one week, with the whole perimeter surface of nano wire
For raceway groove, increase device operation current, thus improve the short-channel effect of device.
In the technique of current all-around-gate field-effect transistor, generally formed after forming nano wire and surround
Grid, and in order to discharge nano wire, need to be formed the extra supporting construction of nano wire, be unfavorable for device
The most integrated, also cannot compared with device integration process compatible.Additionally, due to etching technics holds
It is easily formed undercutting, the upper and lower discordance of size of grid can be caused, thus affect the performance of device.
Summary of the invention
It is an object of the invention to overcome deficiency of the prior art, it is provided that a kind of full encirclement field effect is brilliant
Body pipe and manufacture method thereof are compatible with existing device technology, it is not necessary to form additional support structures.
For achieving the above object, the technical scheme is that
A kind of manufacture method of all-around-gate field-effect transistor, including step:
Thering is provided laminated substrate, laminated substrate includes insulating barrier and semiconductor layer thereon, in semiconductor layer
It is formed with fin；
Fin is formed pseudo-gate device, and covers dummy grid both sides formation interlayer dielectric layer；
Remove dummy grid, to form opening；
Remove lower opening portion and divide the insulating barrier of thickness, with the fin in release opening；
Form the grid surrounding fin in the opening.
Optionally, in the step forming pseudo-gate device, also include:
Being formed between dummy grid and the step of side wall, the part that anisotropy removes dummy grid both sides is thick
The insulating barrier of degree；
In the step forming side wall, side wall covers dummy grid and the insulating barrier of dummy grid lower part thickness
Sidewall.
Optionally, anisotropy removes the insulating barrier of the segment thickness of dummy grid both sides, the insulation of removal
The thickness of layer is 10nm.
Optionally, side wall includes the material layer different from insulating barrier.
Optionally, use isotropic lithographic method, remove lower opening portion and divide the insulating barrier of thickness,
With the fin in release opening.
Optionally, the method using ALD, form the grid surrounding fin in the opening.
Optionally, described grid includes metal gates.
Additionally, present invention also offers a kind of all-around-gate field-effect transistor, including: laminated substrate,
Laminated substrate includes insulating barrier and semiconductor layer thereon, is formed with fin in semiconductor layer；It is positioned at insulation
On layer, across fin and the grid of encirclement fin；Side wall on the sidewall of grid；On the fin of grid both sides
Source-drain area.
Optionally, side wall includes the material layer different from insulating barrier.
Optionally, grid includes metal gates.
The all-around-gate field-effect transistor of the present invention and manufacture method thereof, in the rear grid technique of fin,
After removing pseudo-grid, the insulating barrier of the segment thickness in opening is removed, thus by the fin in opening
Part release, and then re-form the full grid surrounding fin, form the device of all-around-gate, this technique
Mutually compatible with existing device integration process, it is not necessary to extra support member, it is easy to improve integrated level.
Further, formed between dummy grid and the step of side wall, also that the part of dummy grid both sides is thick
The insulating barrier of degree is removed, and so, when forming side wall, the bottom of dummy grid is also covered by side wall, in release
During fin, it is to avoid form undercutting, the size of effective control gate during etching in bottom, improve the performance of device.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme that the present invention implements, below will be to required in embodiment
The accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only the present invention
Some embodiments, for those of ordinary skill in the art, before not paying creative work
Put, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the manufacture method flow process of the all-around-gate field-effect transistor according to the embodiment of the present invention
Figure；
Fig. 3-Figure 11 C is each manufacture manufacturing all-around-gate field-effect transistor according to the embodiment of the present invention
During structural representation, wherein Fig. 4-11 is the schematic top plan view of transistor in each manufacture process,
Fig. 2, Fig. 3, Fig. 4 A-11A is that in each manufacture process, cross section along the transistor of the width of grid shows
Being intended to, Fig. 4 B-11B is the schematic cross-section of transistor in each manufacture process along fin direction, figure
4C-11C is the schematic cross-section of transistor in each manufacture process along grid length direction.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, the most right
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention
Other can also be used to be different from alternate manner described here implement, those skilled in the art can be not
Doing similar popularization in the case of running counter to intension of the present invention, therefore the present invention is not by following public specific embodiment
Restriction.
Secondly, the present invention combines schematic diagram and is described in detail, when describing the embodiment of the present invention in detail, for ease of
Illustrate, represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is only
Being example, it should not limit the scope of protection of the invention at this.Additionally, should comprise in actual fabrication length,
Width and the three-dimensional space of the degree of depth.
In the present invention, it is proposed that the manufacture method of a kind of all-around-gate field-effect transistor, with reference to Fig. 1 institute
Show, including: SOI substrate is provided, top layer silicon is formed fin；Fin is formed pseudo-gate device, and
Cover dummy grid both sides and form interlayer dielectric layer；Remove dummy grid, to form opening；Remove under opening
The oxygen buried layer of segment thickness, with the fin in release opening；Form the grid surrounding fin in the opening.
In the present invention, in the rear grid technique of fin, after removing pseudo-grid, by the segment thickness in opening
Insulating barrier remove, thus the part of the fin in opening is discharged, and then re-forms the full fin that surrounds
Grid, forms the device of all-around-gate, and this technique is mutually compatible with existing device integration process, it is not necessary to
Extra support member, it is easy to improve integrated level.
In order to be better understood from technical scheme and technique effect, show below with reference to concrete flow process
Being intended to Fig. 1 to be described in detail specific embodiment, in the accompanying drawings, wherein Fig. 4-11 makes for each
The schematic top plan view of transistor during making, Fig. 2, Fig. 3, Fig. 4 A-11A is edge in each manufacture process
The schematic cross-section (the AA direction with reference in schematic top plan view) of the transistor of the width of grid, figure
4B-11B be in each manufacture process along the schematic cross-section of transistor in fin direction (with reference to schematic top plan view
In BB direction), Fig. 4 C-11C be in each manufacture process along grid length direction transistor cross section signal
Figure (the CC direction with reference in schematic top plan view).For the accompanying drawing of same sequence number, such as Fig. 5,5A, figure
5B and 5C, for the schematic diagram of the different directions of transistor in same manufacture process.
First, in step S01, it is provided that laminated substrate 100, laminated substrate include insulating barrier 100-2 and
Semiconductor layer 100-3 thereon, is formed with fin 102 in semiconductor layer, referring to figs. 2 and 3 shown.
In the present invention, described substrate can be the lamination lining with the semiconductor layer on insulating barrier and insulating barrier
The end, semiconductor layer is used for being formed fin, and insulating barrier is used for supporting and discharging fin.
In the present embodiment, described substrate can be SOI substrate 100, as in figure 2 it is shown, described SOI
Substrate 100 includes top layer silicon 100-3, buries 100-1 at the bottom of oxide layer 100-2 and backing, and oxygen buried layer is
Silicon oxide layer, described in bury oxide layer 100-2 and be the insulating barrier of substrate, described top layer silicon 100-3 is
The semiconductor layer of substrate.
In the present embodiment, fin 102 can be formed as follows in top layer silicon 100-3.
It is possible, firstly, to form hard mask layer on substrate, such as silicon oxide and the hard mask layer of nitride layer stack,
And hard mask layer is patterned, then use lithographic technique, the method for such as RIE (reactive ion etching),
Etching top layer silicon 100-3, until oxygen buried layer 100-2, thus form fin 102, then, hard mask layer is gone
Remove, as shown in Figure 3.
Then, in step S02, fin is formed pseudo-gate device, and covers dummy grid both sides formation interlayer
Dielectric layer 112, with reference to Fig. 8, Fig. 8 A (AA of Fig. 8 is to schematic cross-section), Fig. 8 B (Fig. 8
BB to schematic cross-section) and Fig. 8 C (CC of Fig. 8 is to schematic cross-section).
In embodiments of the present invention, pseudo-gate device at least includes the dummy grid across fin, the source-drain area at fin two ends
And the side wall of dummy grid.
In specific embodiment, first, the pseudo-gate dielectric layer of deposit and dummy grid material, and pattern,
Form pseudo-gate dielectric layer (not shown) and dummy grid 104, as Fig. 4, Fig. 4 A (AA of Fig. 4 to
Schematic cross-section), Fig. 4 B (BB of Fig. 4 is to schematic cross-section) and Fig. 4 C (CC of Fig. 4 to
Schematic cross-section), wherein, pseudo-gate dielectric layer can be thermal oxide layer or other suitable dielectric materials,
Dummy grid can be non-crystalline silicon, polysilicon or silicon oxide etc., and in the present embodiment, pseudo-gate dielectric layer is hot oxygen
Changing layer, dummy grid is polysilicon.
Then, in more excellent embodiment, before forming side wall, the removal of oxygen buried layer 100-2 is carried out,
Anisotropic etching can be used to remove the oxygen buried layer of the uncovered segment thickness in dummy grid both sides, remove
The thickness of insulating barrier can be 10nm, after the oxygen buried layer in the region not covered by dummy grid and fin is removed,
Compared to the region covered by dummy grid 104, removed region forms sunken regions 106, as Fig. 5,
Fig. 5 A (AA of Fig. 5 is to schematic cross-section), Fig. 5 B (BB of Fig. 5 is to schematic cross-section) and
Fig. 5 C (CC of Fig. 5 is to schematic cross-section).
Then, carrying out the formation of side wall, side wall can use and include the material layer different from oxygen buried layer,
To have selectivity in subsequent etching, in the present embodiment, carrying out the deposit of silicon nitride, thickness can be
5-20nm, and perform etching, the sidewall of dummy grid 104 forms side wall 108, owing to having carried out upper
State the removal of the oxygen buried layer having carried out segment thickness in step, in side wall processing step, in sunken regions
Also can cover side wall 108 on the sidewall of the oxygen buried layer of 106, such as Fig. 6, Fig. 6 A, (AA of Fig. 6 is to cutting
Face schematic diagram), Fig. 6 B (BB of Fig. 6 is to schematic cross-section) and Fig. 6 C (CC of Fig. 6 to cut
Face schematic diagram).
Then, carry out the formation of source-drain area 110, N-type or P can be carried out according to desired type of device
The doping of type, and carry out annealing activation, to form source-drain area 110 at the two ends of fin, such as Fig. 7, Fig. 7 A
(AA of Fig. 7 is to schematic cross-section), Fig. 7 B (BB of Fig. 7 is to schematic cross-section) and Fig. 7 C
(CC of Fig. 7 is to schematic cross-section), for N-type device, carries out n-type doping such as P, As
Deng, for P-type device, carry out P-type dopant such as B, In etc., it is also possible to by epitaxial growth also
Carrying out adulterates in situ forms the source-drain area of extension, to improve the stress effect of raceway groove, improves current-carrying further
The mobility of son.So far, defining the pseudo-gate device of the present embodiment, this puppet gate device includes the puppet across fin
Side wall 108 on gate dielectric layer and dummy grid 104, the source-drain area 110 at fin two ends and dummy grid 104 sidewall.
Then, the deposit of interlayer dielectric layer, the most unadulterated silicon oxide (SiO are carried out2), doping oxygen
SiClx (such as Pyrex, boron-phosphorosilicate glass etc.), silicon nitride (Si3N4) or other low k dielectric materials,
Then planarizing, such as CMP (chemically-mechanicapolish polishes), until exposing the upper of dummy grid 104
Surface, thus form described interlayer dielectric layer (ILD) 112, interlayer dielectric layer 112 covers dummy grid
The fin of both sides, as Fig. 8, Fig. 8 A (AA of Fig. 8 is to schematic cross-section), Fig. 8 B (Fig. 8's
BB is to schematic cross-section) and Fig. 8 C (CC of Fig. 8 is to schematic cross-section).
Then, in step S03, dummy grid 104 is removed, to form opening 114, with reference to Fig. 9, figure
9A (AA of Fig. 9 is to schematic cross-section), Fig. 9 B (BB of Fig. 9 is to schematic cross-section) and figure
9C (CC of Fig. 9 is to schematic cross-section).
In the present embodiment, wet etching can be used to remove dummy grid and pseudo-gate dielectric layer, an enforcement
In example, Tetramethylammonium hydroxide (TMAH) can be passed through and remove the dummy grid of non-crystalline silicon, thus be formed and open
Mouth 114, as shown in Fig. 9,9A, 9B and 9C, can remove dioxy by the HF of dilution further
The pseudo-gate dielectric layer of SiClx, this puppet gate dielectric layer can also in the step of fin in release opening in the lump
Remove.
Then, in step S04, the insulating barrier of opening 114 lower part thickness is removed, with release opening 114
In fin 102, with reference to Figure 10, Figure 10 A (AA of Figure 10 is to schematic cross-section), Figure 10 B (figure
The BB of 10 is to schematic cross-section) and Figure 10 C (CC of Figure 10 is to schematic cross-section).
In embodiments of the present invention, the lithographic method of isotropic, wet method or dry etching can be used,
In one embodiment, the HF of dilution can be used to carry out the removal of oxygen buried layer 100-2 of segment thickness,
Removing a good appetite suddenly appearing in a serious disease, due to the existence of side wall 108 so that the oxygen buried layer 100-2 in opening and opening both sides
Oxygen buried layer is kept apart, this way it is possible to avoid formed along grid length direction at the bottom section of etching in Ke Shi
Undercutting, and cause the grid length of the upper and lower of etch areas inconsistent.Part under etching opening
After oxygen buried layer 100-2 after, the part oxygen buried layer under fin 102 in opening 114 is also removed, shape
Become cavity 115, so that the part release of the fin 102 in opening 114, such as Figure 10,10A, 10B
Shown in 10C, due to the buffer action of side wall, along the upper and lower of this cavity 115 of grid length direction
Width have preferable concordance.
Then, in step S05, opening 114 forms the grid 120 surrounding fin 102, with reference to figure
11, Figure 11 A (AA of Figure 11 is to schematic cross-section), (BB of Figure 11 shows Figure 11 B to cross section
It is intended to) and Figure 11 C (CC of Figure 11 is to schematic cross-section).
Formation grid can be used conventional methods.In the present embodiment, ALD (atomic layer can be used
Deposition) method, carry out gate dielectric layer and the deposit of grid 120, gate dielectric layer can be high K medium material
Material, (such as, comparing with silicon oxide, there is the material of high-k) or other suitable medium materials
Material, high K medium material such as hafnio oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO
Deng, thickness can be 1-3nm, and grid can be metal gates, such as Ti, TiAlx、TiN、TaNx、
HfN、TiCx、TaCxOr W etc. or their lamination, and planarize, until exposing interlayer
Dielectric layer, thus form the grid 120 surrounding fin in opening 114, such as Figure 11,11A, 11B and
Shown in 11C.The structure and material being here formed as all-around-gate pole is merely illustrative, can be according to concrete
Need to form material requested and the grid of structure.So far, the all-around-gate of the embodiment of the present invention is defined
FET device.
In this embodiment, formed between dummy grid and the step of side wall, also by the portion of dummy grid both sides
The insulating barrier dividing thickness is removed, and so, when forming side wall, the bottom of dummy grid is also covered by side wall,
During release fin, it is to avoid form undercutting, the size of effective control gate during etching in bottom, improve the property of device
Energy.
Then, the following process of device, such as contact and metal interconnection structure etc. can be completed as required.
Above the manufacture method of the all-around-gate FET device of the embodiment of the present invention is carried out in detail
Thin description, additionally, present invention also offers the all-around-gate field-effect transistor that said method is formed.
With reference to shown in Figure 11,11A, 11B and 11C, this transistor includes: laminated substrate, and lamination serves as a contrast
The end, includes insulating barrier 100-2 and semiconductor layer 100-3 thereon, is formed with fin 102 in semiconductor layer；
It is positioned on insulating barrier 100-2, across fin 102 and the grid 120 of encirclement fin；On the sidewall of grid 120
Side wall 108；Source-drain area 110 on the fin of grid both sides.
Wherein, side wall includes the material layer different from insulating barrier, and grid includes metal gates.
At whole area of grid, fin is enclosed in grid 120, forms all-around-gate field effect transistor
Tube device.
In an embodiment of the present invention, as shown in Figure 11,11A, 11B and 11C, laminated substrate is SOI
Substrate, insulating barrier 100-2 is its oxygen buried layer, and semiconductor layer 100-3 is its top layer silicon, and fin 102 is formed
In top layer silicon on oxygen buried layer.
The all-around-gate field-effect transistor of the present invention, with the collection of existing fin formula field effect transistor device
Become technique mutually compatible, it is not necessary to extra support member, it is easy to improve integrated level.
The above, be only presently preferred embodiments of the present invention, not the present invention is made any in form
Restriction.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention.Any
Those of ordinary skill in the art, without departing under technical solution of the present invention ambit, may utilize
Technical solution of the present invention is made many possible variations and modification by method and the technology contents of stating announcement, or
It is revised as the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention,
And repair any simple modification made for any of the above embodiments, equivalent variations according to the technical spirit of the present invention
Decorations, all still fall within the range of technical solution of the present invention protection.
Claims (10)
1. the manufacture method of an all-around-gate field-effect transistor, it is characterised in that include step:
Thering is provided laminated substrate, laminated substrate includes insulating barrier and semiconductor layer thereon, in semiconductor layer
It is formed with fin；
Fin is formed pseudo-gate device, and covers dummy grid both sides formation interlayer dielectric layer；
Remove dummy grid, to form opening；
Remove lower opening portion and divide the insulating barrier of thickness, with the fin in release opening；
Form the grid surrounding fin in the opening.
Manufacture method the most according to claim 1, it is characterised in that forming pseudo-gate device
In step, also include:
Being formed between dummy grid and the step of side wall, the part that anisotropy removes dummy grid both sides is thick
The insulating barrier of degree；
In the step forming side wall, side wall covers dummy grid and the insulating barrier of dummy grid lower part thickness
Sidewall.
Manufacture method the most according to claim 2, it is characterised in that anisotropy removes pseudo-grid
The insulating barrier of the segment thickness of both sides, pole, the thickness of the insulating barrier of removal is 10nm.
Manufacture method the most according to claim 2, it is characterised in that side wall includes and insulating barrier
Different material layers.
Manufacture method the most according to claim 2, it is characterised in that use isotropic quarter
Etching method, removes lower opening portion and divides the insulating barrier of thickness, with the fin in release opening.
6. according to the manufacture method according to any one of claim 1-5, it is characterised in that use ALD
Method, in the opening formed surround fin grid.
Manufacture method the most according to claim 1, it is characterised in that described grid includes metal
Grid.
8. an all-around-gate field-effect transistor, it is characterised in that including:
Laminated substrate, laminated substrate includes insulating barrier and semiconductor layer thereon, is formed in semiconductor layer
There is fin；
It is positioned on insulating barrier, across fin and the grid of encirclement fin；
Side wall on the sidewall of grid；
Source-drain area on the fin of grid both sides.
Field-effect transistor the most according to claim 8, it is characterised in that side wall include with absolutely
The material layer that edge layer is different.
Field-effect transistor the most according to claim 8, it is characterised in that grid includes gold
Belong to grid.
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| CN201510018931.9A CN105845726A (en) | 2015-01-14 | 2015-01-14 | Fully-wrapped gate field effect transistor and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155101A (en) * | 2017-12-22 | 2018-06-12 | 中国科学院微电子研究所 | Stacked nanowire and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577850A (en) * | 2003-06-27 | 2005-02-09 | 英特尔公司 | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
| US20140197370A1 (en) * | 2013-01-11 | 2014-07-17 | International Business Machines Corporation | Overlap capacitance nanowire |
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- 2015-01-14 CN CN201510018931.9A patent/CN105845726A/en active Pending
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| CN1577850A (en) * | 2003-06-27 | 2005-02-09 | 英特尔公司 | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
| US20140197370A1 (en) * | 2013-01-11 | 2014-07-17 | International Business Machines Corporation | Overlap capacitance nanowire |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108155101A (en) * | 2017-12-22 | 2018-06-12 | 中国科学院微电子研究所 | Stacked nanowire and manufacturing method thereof |
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