CN105845659A - Lead pad structure and forming method thereof - Google Patents
Lead pad structure and forming method thereof Download PDFInfo
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- CN105845659A CN105845659A CN201510019493.8A CN201510019493A CN105845659A CN 105845659 A CN105845659 A CN 105845659A CN 201510019493 A CN201510019493 A CN 201510019493A CN 105845659 A CN105845659 A CN 105845659A
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- passivation layer
- layer
- metal wire
- metal
- lead wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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Abstract
The invention provides a lead pad structure and a forming method thereof. In the lead pad structure, a lead pad covers the top end of a metal wire and part of the side surface of the metal wire, and is connected with a top metal interconnection wire through the metal wire. As the edge of the lead pad forms a flanging sealing and surrounding part of the side surface on the top of the metal wire, the lead pad is acted upon by the constraint stress of the flanging sealing and surrounding the side surface of the metal wire in addition to the adhesion force between the lead pad and the top end face of the metal wire covered by the lead pad, and the magnitude of the constraint stress depends on the deformation yield stress and/or tensile yield stress of the flanging. Accordingly, if there is a need to make the lead pad warped up from the end face of the metal wire covered by the lead pad, the lead pad needs to overcome the constraint stress applied by the flanging to the lead pad in addition to the adhesion force. Therefore, the problem that the metal of the lead pad flakes off due to too large mechanical stress and a semiconductor chip is thus scrapped is avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of lead wire welding mat structure and forming method thereof.
Background technology
In integrated circuit (IC) package fabrication process, it is to connect core using gold thread (gold wire) as lead-in wire mostly
Sheet (die) and support plate, existing lead wire welding mat structure as shown in Figure 1, including semiconductor chip 10, semiconductor chip
10 include the dielectric layer 11 being positioned at the superiors, are formed with top-level metallic interconnection line 12 in dielectric layer 11；At top layer
Metal interconnecting wires 12 surface forms lead wire welding mat 13；Lead-in wire 14 is by routing (wire bonding) processing procedure and lead-in wire weldering
Pad 13 connection；Conventionally, as top-level metallic interconnection line 12 typically uses the metallic copper of low-resistivity, and
For the consideration with lead-in wire 14 good adhesivenesses, lead wire welding mat 13 generally uses metallic aluminium.
Compared to gold thread, copper cash (copper wire) has the advantage of low cost and has preferably electric conductivity, heat conduction
Property and mechanical strength, therefore the line footpath of copper bonding wire can be designed to thinner and can provide preferably radiating efficiency, thus at present
Gradually replace tradition gold thread with copper cash to be applied in the routing processing procedure of semiconductor chip.Owing to beating to lead wire welding mat
In line process, need certain mechanical stress make lead-in wire good adhere to lead wire welding mat, when use copper cash replace tradition
When gold thread carries out routing, owing to the melt capacity of copper cash is poor more than gold thread, accordingly, it would be desirable to bigger mechanical stress ability
Ensure the adhesion of copper cash and lead wire welding mat.But, in the lead wire welding mat structure that prior art uses, aluminium down-lead bonding pad
It is the horizontal surface being attached directly to top-level metallic interconnection line by deposition, and between aluminium down-lead bonding pad and metal interconnecting wires
Adhesiveness depend entirely on the size of the contact surface area in both horizontal directions, therefore, carrying out copper routing processing procedure
Time, bigger mechanical stress can be destroyed the adhesion between lead wire welding mat and top-level metallic interconnection line, cause lead wire welding mat
, there is metal peeling, thus cause scrapping of semiconductor chip in breakage.
In prior art, in order to stop phase counterdiffusion between aluminium down-lead bonding pad with copper top-level metallic interconnection line, often draw at aluminum
Forming barrier layer between wire bonding pad and copper top-level metallic interconnection line, barrier layer generally uses metal tantalum or tantalum-nitride material,
Can in a disguised form improve the adhesion characteristics between aluminium down-lead bonding pad and copper top-level metallic interconnection line, but, based on as shown in Figure 1
Existing lead wire welding mat structure, its adhesion is still to be provided by the contact surface in horizontal direction completely, when carrying out copper routing
During processing procedure, still there will be the metal peeling of aluminium down-lead bonding pad, as shown in a-quadrant in Fig. 2.Therefore, offer one is provided badly
Plant new lead wire welding mat structure, to avoid the technical problem occurred in prior art.
Summary of the invention
For solving the problems referred to above, the invention provides a kind of lead wire welding mat structure and forming method, beat realizing copper wiring
While Wiring technology, it is to avoid cause lead wire welding mat metal peeling owing to when using copper wiring routing mechanical stress is excessive,
Cause the problem that semiconductor chip is scrapped.
The invention provides a kind of lead wire welding mat Structure formation method, including:
Thering is provided semiconductor chip, described semiconductor chip has the dielectric layer being positioned at the superiors, in described dielectric layer
It is formed with top-level metallic interconnection line；
In described semiconductor chip surface deposit passivation layer, and formed in described passivation layer and the interconnection of described top-level metallic
The metal wire that line connects；
Etch described passivation layer and form groove, to expose top and the surface of described metal wire；
Deposition of wire bonding pad materials layer in groove, to cover top and the metal line portions side of described metal wire；
Etching described lead wire welding mat material layer and form lead wire welding mat, described metal line portions embeds described lead wire welding mat.
Further, in described semiconductor chip surface deposit passivation layer, and formed and described top layer in described passivation layer
The metal wire that metal interconnecting wires connects includes:
Deposit the first passivation layer in described semiconductor chip surface, formed in described first passivation layer and described top layer gold
Belong to the metal wire that interconnection line connects；
The second passivation layer is deposited at described first passivation layer and described metal wire top.
Further, described first passivation layer forms the metal wire being connected with described top-level metallic interconnection line to include:
The first patterning photoresist layer with the first opening, described first opening is formed in described first passivation layer surface
It is directed at the position of described top-level metallic interconnection line；
With described first patterning photoresist layer as mask, the first passivation layer is performed etching, is formed and expose described top layer
First through hole of metal interconnecting wires；
Metal deposit is carried out, to form the metal wire connecting described top layer interconnection line in described first through hole.
Further, etch described passivation layer and form groove, include with the top and surface exposing described metal wire:
The second patterning photoresist layer with the second opening, described second opening is formed in described second passivation layer surface
It is directed at described metal wire, and the width of described second opening is more than the width of described metal wire；
With described second patterning photoresist as mask, the second passivation layer and the first passivation layer are performed etching, to be formed
Expose the top of described metal wire and the groove of surface.
Further, with described second patterning photoresist as mask, the second passivation layer and the first passivation layer are performed etching,
During to form the groove exposing the top of described metal wire and surface, the described metal line portions side of exposure is long
Degree is less than or equal to the 1/2 of described wire lengths.
Further, the material of described metal wire is copper, carries out metal deposit in described first through hole, to form connection
The metal wire of described top layer interconnection line includes:
Copper seed crystal layer in described first through hole；
Copper is deposited by electroless plating, to fill described first through hole on described copper seed layer surface；
Perform cmp to expose described first passivation layer surface.
Further, etch described lead wire welding mat material layer formation lead wire welding mat and be included in described lead wire welding mat material surface
Form the 3rd patterning photoresist layer, for mask, described lead wire welding mat material layer is carried out with the 3rd patterning photoresist layer
Etching, forms lead wire welding mat.
Present invention also offers a kind of lead wire welding mat structure, including semiconductor chip, described semiconductor chip has and is positioned at
The dielectric layer of the superiors, is formed with top-level metallic interconnection line in described dielectric layer；Wherein, described semiconductor chip
Surface is formed with passivation layer, is formed with the metal wire being connected with described top-level metallic interconnection line in described passivation layer；Described
Being provided with lead wire welding mat on passivation layer, described metal line portions embeds lead wire welding mat.
Further, described passivation layer includes the first passivation layer and the second passivation layer, and described metal wire is positioned at described first blunt
Change among layer, and run through described first passivation layer.
Further, described metal wire embeds the degree of depth of described lead wire welding mat less than or equal to the 1/2 of described wire lengths.
Further, the material of described top-level metallic interconnection line and metal wire is copper, and the material of lead wire welding mat is aluminum.
In the lead wire welding mat structure that the present invention provides, lead wire welding mat covers top and the metal line portions side of metal wire
Face, and be connected with top-level metallic interconnection line by metal wire, thus define the metal wire embedding lead wire welding mat；Therefore,
The edge of lead wire welding mat is formed closes the flange surrounding metal wire top section side, therefore, lead wire welding mat except with its
Exist outside adhesion between the metal wire top end face covered, also suffer from closing the flange surrounding metal wire side surface
Restraint stress, the size of this restraint stress depends on deformation yield stress and/or the stretching yield stress of flange, accordingly
Ground, to make lead wire welding mat tilt from its metal wire end face covered, then, in addition to overcoming above-mentioned adhesion, also needs
The restraint stress that lead wire welding mat is produced by flange to be overcome, thus avoid that mechanical stress is excessive causes lead wire welding mat metal
Peel off, cause the problem that semiconductor chip is scrapped.
Accompanying drawing explanation
Fig. 1 is existing lead wire welding mat structural representation；
Fig. 2 is metal peeling Electronic Speculum figure in prior art；
Fig. 3 is the application lead wire welding mat forming method schematic flow sheet；
Fig. 4 a～4e is the application lead wire welding mat Structure formation method flowage structure schematic diagram.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, develop simultaneously embodiment referring to the drawings,
The present invention is described in further detail.
As it is shown on figure 3, this application provides a kind of lead wire welding mat forming method, including:
Thering is provided semiconductor chip, semiconductor chip has the dielectric layer being positioned at the superiors, is formed with top in dielectric layer
Layer metal interconnecting wires；
In semiconductor chip surface deposit passivation layer, and form the metal being connected with top-level metallic interconnection line in the passivation layer
Line；
Etch Passivation forms groove, with top and the surface of exposing metal line；
Deposition of wire bonding pad materials layer in groove, to cover top and the metal line portions side of metal wire；
Etch lead bonding pad materials layer forms lead wire welding mat, and metal line portions embeds lead wire welding mat.
Below in conjunction with accompanying drawing 4a～4d, said method is described in detail:
As shown in fig. 4 a, first providing semiconductor chip 20, semiconductor chip 20 has the electrolyte being positioned at the superiors
Layer 21, is formed with top-level metallic interconnection line 22 in dielectric layer 21；Wherein, the material of dielectric layer 21 is the lowest
Dielectric constant (low-K) material, the material of top-level metallic interconnection line 22 is preferably copper；
Then, deposit the first passivation layer 23 in semiconductor chip surface, and formed and top layer in the first passivation layer 23
The metal wire 27 that metal connecting line 22 connects；The second passivation layer 28 is deposited at the first passivation layer 23 and metal wire 27 top.
In the present embodiment, concrete implementation mode is with reference to shown in Fig. 4 a～4c:
Deposit the first passivation layer 23 in semiconductor chip surface, and formed on the first passivation layer 23 surface and have first and open
First patterning photoresist layer 24 of mouth 25, the first opening 25 is directed at the position of top-level metallic interconnection line 22；
With reference to Fig. 4 b, with the first patterning photoresist layer 24 as mask, the first passivation layer 23 is performed etching, is formed
First through hole 26 of bottom-exposed top-level metallic interconnection line 22；Wherein, etching technics can use in prior art usual
Wet etching or dry etching, do not limit at this；
As illustrated in fig. 4 c, after the first patterning photoresist layer 24 is removed in ashing, the first through hole 26 carries out metal and sinks
Long-pending, to form the metal wire 27 connecting top layer interconnection line；In the present embodiment, the preferably material of metal wire 27 is copper,
In the first through hole 26, carry out copper formation of deposits copper metal line 27 can use chemical plating process, at the first through hole 26
After middle copper seed crystal layer (not shown), deposit copper on copper seed layer surface by electroless plating, to fill described the
One through hole 26, finally performs cmp to expose the first passivation layer surface 23；It is of course also possible to use chemistry
Other prior aries such as vapour deposition, physical vapour deposition (PVD) form metal wire 27, do not repeat them here；
After forming metal wire 27, with reference to Fig. 4 c, in the present embodiment, at the first passivation layer 23 surface and metal wire 27
Top formation of deposits the second passivation layer 28, now the first passivation layer 23 and the second passivation layer 28 constitute lead wire welding mat knot
The passivation layer of structure.
Continuing technological process, the passivation layer that etching is made up of the first passivation layer 23 and the second passivation layer 28 forms groove,
Top and surface with exposing metal line 27；Concrete, with reference to Fig. 4 c and 4d, at the second passivation layer 28
Surface forms the second patterning photoresist layer 29 with the second opening 30, and the second opening 30 is directed at metal wire 27, and
The width of the second opening 30 is more than the width of metal wire 27；With the second patterning photoresist 29 as mask, blunt to second
Change layer 28 and the first passivation layer 23 performs etching, to form top 27a and the atop part side of exposing metal line 27
The groove 31 of surface 27b；As preferably, the metal wire 27 surface length of exposure is less than or equal to metal wire 27
The 1/2 of length, it is to avoid after exposing too much metal wire 27, metal wire 27 occurs when follow-up routing processing procedure loosening, carries
The fixation of high metal wire 27.
As shown in fig 4e, deposition of wire bonding pad materials layer fills groove 31, with cover the top 27a of metal wire 27 with
And metal wire 27 atop part side surface 27b；Finally, etch lead bonding pad materials layer is to form the lead-in wire of intended shape
Weld pad 32；Wherein, lead wire welding mat material layer is preferably metallic aluminium, and can be by lead wire welding mat material surface shape
Become the 3rd patterning photoresist layer (not shown), for mask, lead wire welding mat material layer is entered with the 3rd patterning photoresist layer
The dry etching of the existing technique of row or wet etching, to form the lead wire welding mat 32 of intended shape, do not repeat them here.
According to the present processes, ultimately constructed go out lead wire welding mat structure as shown in fig 4e, semiconductor chip 20 table
Face be formed passivation layer 23,28 (although passivation layer 23,28 is by twice formation of deposits, but functionally for
Both is the passivation layer as lead wire welding mat structure), passivation layer is formed and is connected with top-level metallic interconnection line 22
Metal wire 27；Being provided with lead wire welding mat 32 on passivation layer, metal wire 27 is partially submerged into lead solder-joint 32.Due to metal
Line 27 is partially submerged into lead solder-joint 32, and lead wire welding mat 32 includes the body 32a covering the top 27a of metal wire 27
And cover metal wire 27 atop part side surface 27b flange 32b, therefore, lead wire welding mat body 32a except with
Exist outside adhesion between its metal wire 27 top 27a end face covered, also suffer from closing and surround metal line side table
The restraint stress of the flange 32b of face 27b, the size of this restraint stress depend on flange 32b deformation yield stress and/
Or stretching yield stress, correspondingly, to make lead wire welding mat 32 tilt from its metal wire 27 end face covered, then remove
Overcome outside above-mentioned adhesion, in addition it is also necessary to overcome the restraint stress that lead wire welding mat body 32a is produced by flange 32b,
Thus avoid that mechanical stress is excessive causes lead wire welding mat metal peeling, cause the problem that semiconductor chip is scrapped.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. done, should be included in the scope of protection of the invention
Within.
Claims (11)
1. a lead wire welding mat Structure formation method, it is characterised in that including:
Thering is provided semiconductor chip, described semiconductor chip has the dielectric layer being positioned at the superiors, in described dielectric layer
It is formed with top-level metallic interconnection line；
In described semiconductor chip surface deposit passivation layer, and formed in described passivation layer and the interconnection of described top-level metallic
The metal wire that line connects；
Etch described passivation layer and form groove, to expose top and the surface of described metal wire；
Deposition of wire bonding pad materials layer in groove, to cover top and the metal line portions side of described metal wire；
Etching described lead wire welding mat material layer and form lead wire welding mat, described metal line portions embeds described lead wire welding mat.
Method the most according to claim 1, it is characterised in that in described semiconductor chip surface deposit passivation layer,
And the metal wire that formation is connected with described top-level metallic interconnection line in described passivation layer includes:
Deposit the first passivation layer in described semiconductor chip surface, formed in described first passivation layer and described top layer gold
Belong to the metal wire that interconnection line connects；
The second passivation layer is deposited at described first passivation layer and described metal wire top.
Method the most according to claim 2, it is characterised in that formed and described top in described first passivation layer
The metal wire that layer metal interconnecting wires connects includes:
The first patterning photoresist layer with the first opening, described first opening is formed in described first passivation layer surface
It is directed at the position of described top-level metallic interconnection line；
With described first patterning photoresist layer as mask, the first passivation layer is performed etching, is formed and expose described top layer
First through hole of metal interconnecting wires；
Metal deposit is carried out, to form the metal wire connecting described top layer interconnection line in described first through hole.
Method the most according to claim 3, it is characterised in that etch described passivation layer and form groove, to expose
Top and the surface of described metal wire include:
The second patterning photoresist layer with the second opening, described second opening is formed in described second passivation layer surface
It is directed at described metal wire, and the width of described second opening is more than the width of described metal wire；
With described second patterning photoresist as mask, the second passivation layer and the first passivation layer are performed etching, to be formed
Expose the top of described metal wire and the groove of surface.
Method the most according to claim 4, it is characterised in that with described second patterning photoresist as mask,
Second passivation layer and the first passivation layer are performed etching, exposes the top of described metal wire and surface to be formed
During groove, the described metal line portions side length of exposure is less than or equal to the 1/2 of described wire lengths.
Method the most according to claim 5, it is characterised in that the material of described metal wire is copper, described
Carrying out metal deposit in one through hole, the metal wire connecting described top layer interconnection line with formation includes:
Copper seed crystal layer in described first through hole；
Copper is deposited by electroless plating, to fill described first through hole on described copper seed layer surface；
Perform cmp to expose described first passivation layer surface.
Method the most according to claim 6, it is characterised in that etch described lead wire welding mat material layer and form lead-in wire
Weld pad is included in described lead wire welding mat material surface and forms the 3rd patterning photoresist layer, with the 3rd patterning photoresist
Described lead wire welding mat material layer is performed etching by layer for mask, forms lead wire welding mat.
8. a lead wire welding mat structure, including semiconductor chip, described semiconductor chip has electricity Jie being positioned at the superiors
Matter layer, is formed with top-level metallic interconnection line in described dielectric layer, it is characterised in that described semiconductor chip surface shape
Become to have passivation layer, described passivation layer is formed the metal wire being connected with described top-level metallic interconnection line；Described passivation layer
On be provided with lead wire welding mat, described metal line portions embeds lead wire welding mat.
Structure the most according to claim 8, it is characterised in that described passivation layer includes the first passivation layer and second
Passivation layer, described metal wire is positioned among described first passivation layer, and runs through described first passivation layer.
Structure the most according to claim 9, it is characterised in that described metal wire embeds described lead wire welding mat
The degree of depth is less than or equal to the 1/2 of described wire lengths.
11. structures according to claim 10, it is characterised in that described top-level metallic interconnection line and metal wire
Material is copper, and the material of lead wire welding mat is aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510019493.8A CN105845659B (en) | 2015-01-15 | 2015-01-15 | Lead wire welding mat structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510019493.8A CN105845659B (en) | 2015-01-15 | 2015-01-15 | Lead wire welding mat structure and forming method thereof |
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| Publication Number | Publication Date |
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| CN105845659A true CN105845659A (en) | 2016-08-10 |
| CN105845659B CN105845659B (en) | 2019-04-26 |
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| CN201510019493.8A Active CN105845659B (en) | 2015-01-15 | 2015-01-15 | Lead wire welding mat structure and forming method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015403A (en) * | 1999-06-28 | 2001-01-19 | Toshiba Corp | Semiconductor device |
| CN101114600A (en) * | 2006-07-27 | 2008-01-30 | 联华电子股份有限公司 | Method and structure for preventing soldering pad stripping |
| CN102931100A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Formation method of semiconductor packaging structure |
| US20140293547A1 (en) * | 2013-03-26 | 2014-10-02 | Via Technologies, Inc. | Circuit substrate, semiconductor package and process for fabricating the same |
-
2015
- 2015-01-15 CN CN201510019493.8A patent/CN105845659B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015403A (en) * | 1999-06-28 | 2001-01-19 | Toshiba Corp | Semiconductor device |
| CN101114600A (en) * | 2006-07-27 | 2008-01-30 | 联华电子股份有限公司 | Method and structure for preventing soldering pad stripping |
| CN102931100A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Formation method of semiconductor packaging structure |
| US20140293547A1 (en) * | 2013-03-26 | 2014-10-02 | Via Technologies, Inc. | Circuit substrate, semiconductor package and process for fabricating the same |
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| Publication number | Publication date |
|---|---|
| CN105845659B (en) | 2019-04-26 |
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