CN105845571B - The manufacturing method of semiconductor devices - Google Patents
The manufacturing method of semiconductor devices Download PDFInfo
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- CN105845571B CN105845571B CN201510019215.2A CN201510019215A CN105845571B CN 105845571 B CN105845571 B CN 105845571B CN 201510019215 A CN201510019215 A CN 201510019215A CN 105845571 B CN105845571 B CN 105845571B
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Abstract
The present invention provides a kind of manufacturing methods of semiconductor devices, gate dielectric layer is first formed on the substrate, then forms patterned photoresist mask layer, ion implanting is carried out by the exposure mask effect of photoresist mask layer, then it removes photoresist mask layer and anneals, form bag-shaped doped region.Later, grid material is formed, then forms photoresist mask layer as hereinbefore in grid material, and etches and forms grid.Since bag-shaped doped region is to make exposure mask progress ion implanting by the lesser photoresist of depth-to-width ratio in early period to be formed, the excessively high and inhibition to bag-shaped injection of grid inter-drain slot depth-to-width ratio is avoided.
Description
Technical field
The present invention relates to semiconductor field more particularly to a kind of manufacturing methods of semiconductor devices.
Background technique
With the development of semiconductor devices Highgrade integration, the grid of metal oxide semiconductor transistor (MOSFET) is long
Just scaled to smaller size is spent, correspondingly, the manufacture craft of semiconductor devices is also in continuous improve, with satisfaction
Requirement of the people to device performance.
In MOS transistor manufacturing process, in order to form the regions such as source/drain, need to carry out high energy high dose from
Son injection, but this frequently can lead to the horizontal proliferation of injection ion, and then cause the problems such as breakdown when subsequent device uses.Grid
Pole two sides can solve this problem by the bag-shaped doped region that bag-shaped (pocket) injection is formed.Bag-shaped injection is with semiconductor device
The reduction of part size and the link closely related with device performance to grow up, square two sides are formed by bag under the gate
Shape doped region not only can solve breakdown problem, but also affect the short-channel effect (short-channel- of device
Effects, SCES), it is closely related with the parameters such as channel mobility and junction capacity, junction leakage.
Currently, bag-shaped injection carries out after being generally formed in grid, bag-shaped method for implanting is in the two sides of grid to tilt
Angle carry out ion implanting, bag-shaped doped region is formed with the partial region below the gap location and grid of grid.However, with
The diminution of device size, after formation of the gate, the distance between grid is also gradually reduced.As shown in Figure 1, shape on the substrate 10
At there is multiple grids 20 being spaced apart, the height of grid 20 is larger and the distance between grid 20 is smaller (by neighboring gates structure
At groove 21 there is biggish depth-to-width ratio), at this point, if carrying out ion implanting to substrate 10 to form bag-shaped doped region,
The ion that then direction inclination as shown by the arrows in Figure 1 is projected can largely be injected into the side of grid 20, not can guarantee and be injected into
Bag-shaped doped region is formed in the substrate of 20 lower section of grid.
Summary of the invention
To solve the above-mentioned problems in the prior art, the present invention provides a kind of manufacturing method of semiconductor devices,
Include:
Substrate is provided, and forms gate dielectric layer in the substrate surface；
The first patterned photoresist mask layer is formed on the gate dielectric layer, to the described first patterned photoresist
The region that mask layer exposes carries out ion implanting, to form bag-shaped doped region；
The described first patterned photoresist mask layer is removed, and deposits grid material on the substrate；
The second patterned photoresist mask layer is formed in the grid material, the second patterned photoresist is covered
Film layer is formed with the first patterned photoresist mask layer using identical mask plate；
Using the described second patterned photoresist mask layer as grid material described in mask etching, multiple grids are formed.
Optionally, it before the step of forming the first patterned photoresist mask layer, is first formed on the gate dielectric layer
Grid material；
After forming bag-shaped doped region and removing photoresist mask layer, grid material is continuously formed to scheduled thickness.
Optionally, before the step of step forms the first patterned photoresist mask layer, first in the gate dielectric layer
In upper formation grid material, the grid material with a thickness of
Optionally, the grid includes floating gate and the control gate above the floating gate, in the floating gate and the control
There is separation layer between grid processed.
Optionally, the separation layer shares three layers, including two layers of silicon oxide layer and between two layers of silica
Silicon nitride layer.
Optionally, the width between the multiple grid isThe depth-to-width ratio of groove is between the multiple grid
5.5。
Optionally, the ion implanting is oblique ion implanting.
Optionally, after forming multiple grids, also it is included in the step of the multiple grid two sides form source electrode and drain electrode.
Optionally, the method for forming source electrode and drain electrode is to continue to inject ion formation heavily doped region in multiple grid two sides
Domain.
The manufacturing method of semiconductor devices of the present invention is first formed on the substrate gate dielectric layer, then forms pattern
The photoresist mask layer of change carries out ion implanting by the exposure mask effect of photoresist mask layer, then removes photoresist mask layer
And anneal, form bag-shaped doped region.Later, grid material is formed, then forms photoresist as hereinbefore in grid material
Mask layer, and etch and form grid.Since bag-shaped doped region is to make exposure mask progress by the lesser photoresist of depth-to-width ratio in early period
Ion implanting and formed, therefore avoid the excessively high and inhibition to bag-shaped injection of grid inter-drain slot depth-to-width ratio.
Detailed description of the invention
Fig. 1 is the ion implanting schematic diagram that the prior art forms bag-shaped doped region in the semiconductor device.
Fig. 2 is the flow chart of the manufacturing method of semiconductor devices described in one embodiment of the invention.
Fig. 3 to Fig. 9 is the side view of each step of manufacturing method of semiconductor devices described in one embodiment of the invention.
Specific embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
As shown in Fig. 2, including the following steps: the present invention provides a kind of manufacturing method of semiconductor devices
S1: substrate is provided, and forms gate dielectric layer in the substrate surface；
S2: the first patterned photoresist mask layer is formed in the grid material, and the first photoresist is covered
The region that film layer is exposed carries out ion implanting, to form bag-shaped doped region；
S3: removal first photoresist mask layer, and continue to deposit grid material to scheduled thickness；
S4: the second patterned photoresist mask layer, the second patterned photoetching are formed in the grid material
Glue mask layer is formed with the first patterned photoresist mask layer using identical mask plate；
S5: using the described second patterned photoresist mask layer as grid material described in mask etching, multiple grids are formed.
In the present embodiment, being illustrated semiconductor devices of the present invention by taking memory device (such as flash memory) as an example
Manufacturing method.Semiconductor devices has multiple memory devices in the horizontal direction, and each memory device has upper and lower vertical distribution
Floating gate and control gate, but the present invention is not limited with memory device, when being related to the ion implanting of other high aspect ratio trench quites, can be made
With method of the present invention.
Below with reference to the manufacturing method of the semiconductor devices of Fig. 3 to Fig. 9 the present invention will be described in detail embodiment.
As shown in figure 3, step S1 is first carried out, substrate 100 is provided, and form gate dielectric layer on 100 surface of substrate
200。
The substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon substrate, be also possible to silicon, germanium, silicon Germanium compound or
The substrate that the materials such as GaAs are formed, the substrate 100 can have epitaxial layer or insulating layer silicon-on, can also be other
Semiconductor material is not listed one by one here.The gate dielectric layer 200 formed in substrate 100 covers the surface of substrate 100, specifically
Forming method can be chemical vapor deposition or thermal oxide.
After forming gate dielectric layer 200, barrier layer is formed on the gate dielectric layer 200.The barrier layer purpose is
Gate dielectric layer 200 is protected, so that gate dielectric layer 200 does not contact in the subsequent process with photoresist layer, photoresist is avoided to be situated between grid
Matter layer 200 pollutes.After subsequent photoetching process terminates, the barrier layer is removed.As shown in figure 3, in the present embodiment,
The barrier layer is grid material 300.Due to being also required to form grid material 300 on gate dielectric layer 200 in subsequent step, because
This directly forms grid material 300 here and is used as barrier layer, can save after photoetching process terminates, remove the barrier layer
The step of.In this step, the grid material 300 of formation with a thickness ofThe grid material 300 is specially
Polysilicon, but invention is not limited thereto.
As shown in Figure 4 and Figure 5, step S2 is then executed, patterned photoresist is formed in the grid material 300 and covers
Film layer 400, and ion implanting is carried out to the region that the photoresist mask layer 400 exposes, to form bag-shaped doped region.Wherein,
The method for forming the first patterned photoresist mask layer 400 is: coating photoresist on the surface of gate dielectric layer 200, then leads to
It crosses a mask plate to be exposed photoresist, finally development removal part photoresist, to form the on the surface of gate dielectric layer 200
One photoresist mask layer 400.
Fig. 5 is referred to, in order to form bag-shaped doped region 110 in substrate 100, the ion implanting is oblique ion implanting
(direction relative to vertical substrates surface has an angle, 30-60 degree, preferably 45 degree is generally selected, such as arrow institute in Fig. 5
Show direction) so that the bag-shaped doped region 110 eventually formed is not only present in the area of the first photoresist mask layer 400 exposing
Domain also diffuses to the two sides in the region of the first photoresist mask layer 400 exposing, i.e. immediately below the first photoresist mask layer 400
Partial region.
As shown in fig. 6, then executing step S3, first photoresist mask layer 400 is removed, and continues to deposit grid material
Matter 300 is to scheduled thickness.
In order to optimize bag-shaped doped region 110, so that the ion of injection has better distribution, the first photoresist exposure mask is being removed
After layer 400, further include the steps that annealing to bag-shaped doped region 110.
In the present embodiment, as shown in fig. 6, due to the material on barrier layer 300 and grid electrode layer that are formed before material
Matter is identical, therefore the thickness of the grid electrode layer formed in step s3 meets in advance with the sum of the thickness on barrier layer being previously formed
Fixed gate.Wherein, finally formed grid is needed comprising floating gate, control gate and is formed in the floating gate and institute
The separation layer 330 between control gate is stated, i.e., is separated floating gate and control gate by the separation layer 330.Specifically, it is first hindering
Floating gate material 310 is formed in barrier 300 to required thickness, then forms separation layer 330 in floating gate material 310, finally every
Control gate material 320 is formed on absciss layer 330.Wherein, separation layer 330 can be ONO structure, that is, include two layers of silicon oxide layer and
Silicon nitride layer between two layers of silica.
As shown in fig. 7, then executing step S4, the second patterned photoresist is formed in the grid material 300 and is covered
Film layer 400 ', the second patterned photoresist mask layer 400 ' use phase with the first patterned photoresist mask layer 400
Same mask plate is formed.Specific method is to coat photoresist on the surface of grid material 300, then by in step S2
Identical mask plate is exposed photoresist, and finally development removal part photoresist is formed with the surface in grid material 300
With the photoresist mask layer of identical patterns in step S2.Formed is with the purpose of the photoresist mask layer of step S2 identical patterns,
Guarantee that the bag-shaped doped region 110 being previously formed is placed exactly in the two sides for the grid being subsequently formed.
As shown in figure 8, step S5 is finally executed, with the described second patterned photoresist mask layer 400 ' for mask etching
The grid material 300, forms multiple grids.In the present embodiment, multiple grids 500 of formation are etched comprising floating gate, control
Grid processed and the separation layer between floating gate, control gate.
With continued reference to Fig. 8, after formation of the gate, the second patterned photoresist mask layer 400 ' is removed.As shown in figure 9,
It also include that shape is distinguished in the substrate 100 of 500 two sides of grid after removing the second patterned photoresist mask layer 400 '
The step of at source electrode and drain electrode.Bag-shaped doped region 110 has been formed in abovementioned steps, is used as lightly doped district；In subsequent difference
When forming source/drain 120, ion implanting is carried out to substrate 100 again, forms heavily doped region, as source/drain 120.Most
Eventually, bag-shaped doped region 110 is located at the two sides of source/drain 120.
It should be noted that above-described embodiment is merely a preferred embodiment of the present invention.It is formed on the surface of the substrate 100
After the step of gate dielectric layer 200, the first patterned photoresist mask layer directly can be formed on the surface of gate dielectric layer 200
400.After forming bag-shaped doped region and removing the first patterned photoresist mask layer 400, property forms predetermined thickness again
The grid material 300 of degree.
The present invention before the gate is formed, first pass through photoresist exposure mask effect to the subsequent grid two sides needed to form into
Row ion implanting forms bag-shaped doped region.Then photoresist exposure mask is removed, then forms multiple grids according to a conventional method.Due to this
Width in embodiment between grid is onlyThe depth-to-width ratio of groove is all larger than 5.5 between multiple grids, and photoresist mask layer
The depth-to-width ratio of middle groove is respectively less than 2, therefore can solve in the prior art when carrying out bag-shaped injection by the method, and inclination is penetrated
Ion out falls on the side of grid, can not the technical issues of square basal region forms bag-shaped doped region under the gate.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the invention is also intended to include including these modification and variations.
Claims (9)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
Substrate is provided, and forms gate dielectric layer in the substrate surface；
The first patterned photoresist mask layer is formed on the gate dielectric layer, to the described first patterned photoresist exposure mask
The region that layer exposes carries out ion implanting, to form bag-shaped doped region；
The described first patterned photoresist mask layer is removed, and deposits grid material on the substrate；
The second patterned photoresist mask layer, the second patterned photoresist mask layer are formed in the grid material
It is formed with the first patterned photoresist mask layer using identical mask plate；
Using the described second patterned photoresist mask layer as grid material described in mask etching, multiple grids are formed.
2. the manufacturing method of semiconductor devices as described in claim 1, it is characterised in that:
Before the step of forming the first patterned photoresist mask layer, grid material is first formed on the gate dielectric layer；
After forming bag-shaped doped region and removing photoresist mask layer, grid material is continuously formed to scheduled thickness.
3. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that it is patterned to form first in step
Before the step of photoresist mask layer, first on the gate dielectric layer formed grid material in, the grid material with a thickness of
4. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the grid includes floating gate and is located at
Control gate above the floating gate has separation layer between the floating gate and the control gate.
5. the manufacturing method of semiconductor devices as claimed in claim 4, which is characterized in that the separation layer shares three layers, packet
Include two layers of silicon oxide layer and the silicon nitride layer between two layers of silica.
6. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the width between the multiple grid
ForThe depth-to-width ratio of groove is 5.5 between the multiple grid.
7. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the ion implanting is oblique ion
Injection.
8. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that after forming multiple grids, also include
In the step of the multiple grid two sides form source electrode and drain electrode.
9. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that the method for forming source electrode and drain electrode is
Continue to inject ion formation heavily doped region in multiple grid two sides.
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| CN201510019215.2A CN105845571B (en) | 2015-01-14 | 2015-01-14 | The manufacturing method of semiconductor devices |
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| CN201510019215.2A CN105845571B (en) | 2015-01-14 | 2015-01-14 | The manufacturing method of semiconductor devices |
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| CN105845571A CN105845571A (en) | 2016-08-10 |
| CN105845571B true CN105845571B (en) | 2019-05-03 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405864A (en) * | 2001-08-14 | 2003-03-26 | 旺宏电子股份有限公司 | Method for manufacturing metal oxide semicondustor transistor |
| CN1947244A (en) * | 2004-01-12 | 2007-04-11 | 斯班逊有限公司 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6282123B1 (en) * | 1998-12-21 | 2001-08-28 | Lattice Semiconductor Corporation | Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell |
| US20020182829A1 (en) * | 2001-05-31 | 2002-12-05 | Chia-Hsing Chen | Method for forming nitride read only memory with indium pocket region |
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2015
- 2015-01-14 CN CN201510019215.2A patent/CN105845571B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405864A (en) * | 2001-08-14 | 2003-03-26 | 旺宏电子股份有限公司 | Method for manufacturing metal oxide semicondustor transistor |
| CN1947244A (en) * | 2004-01-12 | 2007-04-11 | 斯班逊有限公司 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell |
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| CN105845571A (en) | 2016-08-10 |
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