CN105845571A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN105845571A CN105845571A CN201510019215.2A CN201510019215A CN105845571A CN 105845571 A CN105845571 A CN 105845571A CN 201510019215 A CN201510019215 A CN 201510019215A CN 105845571 A CN105845571 A CN 105845571A
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Abstract
The invention provides a semiconductor device manufacturing method, and the method comprises the steps: firstly forming a grid dielectric layer on a substrate; secondly forming a patterned photoresist mask layer, and carrying out ion injection through the mask action of the photoresist mask layer; thirdly removing the photoresist mask layer and carrying out annealing; fourthly forming a bag-shaped doping region; fifthly forming a grid material, forming a photoresist mask layer on the grid material, and carrying out etching to form a grid electrode, wherein the photoresist mask layer is the same as the former photoresist mask layer. Because the bag-shaped doping region is formed by the ion injection of the photoresist mask layer with a smaller depth at an earlier stage, the method reduces the inhibition, caused by the overlarge depth-width ratio of a trench between grid electrodes, on bag-shaped injection.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to the manufacture method of a kind of semiconductor device.
Background technology
Along with the development of semiconductor device Highgrade integration, metal oxide semiconductor transistor (MOSFET)
Grid length the most scaled to less size, correspondingly, the processing technology of semiconductor device also exists
In constantly improving, to meet people's requirement to device performance.
In MOS transistor manufacture process, in order to form the regions such as source/drain, need to carry out high-energy high
The ion implanting of dosage, but this horizontal proliferation that frequently can lead to inject ion, and then use in subsequent device
The problems such as Shi Yinfa punctures.The bag-shaped doped region formed is injected, by bag-shaped (pocket), in grid both sides can solve this
Problem.Bag-shaped injection is as the reduction of dimensions of semiconductor devices and the phase close with device performance that grow up
The link closed, the bag-shaped doped region that its both sides square under the gate are formed can not only solve breakdown problem, and
And have an effect on the short-channel effect (short-channel-effects, SCES) of device, with channel mobility and
The parameter such as junction capacity, junction leakage is closely related.
At present, bag-shaped injection is carried out after being generally formed in grid, and bag-shaped method for implanting is the both sides at grid
Carry out ion implanting at an oblique angle, form bag with the subregion below the gap location and grid of grid
Shape doped region.But, along with reducing of device size, after formation of the gate, the distance between grid also by
Tapered little.As it is shown in figure 1, be formed with multiple grid 20 spaced apart on the substrate 10, grid 20
The biggest and distance of between grid 20 is less that (groove 21 being made up of neighboring gates has bigger deep
Wide ratio), now, if substrate 10 being carried out ion implanting in order to form bag-shaped doped region, then as in Fig. 1
Direction shown in arrow tilts the ion major part penetrated can be injected into the side of grid 20, it is impossible to ensure to be injected into
Substrate below grid 20 is formed bag-shaped doped region.
Summary of the invention
For solving the above-mentioned problems in the prior art, the invention provides the manufacture of a kind of semiconductor device
Method, including:
Substrate is provided, and forms gate dielectric layer at described substrate surface；
Described gate dielectric layer forms the photoresist mask layer of the first patterning, to described first patterning
The region that photoresist mask layer exposes carries out ion implanting, to form bag-shaped doped region；
Remove the photoresist mask layer of described first patterning, and deposition grid material on the substrate；
Described grid material is formed the photoresist mask layer of the second patterning, the light of described second patterning
The photoresist mask layer of photoresist mask layer and the first patterning uses identical mask plate to be formed；
Grid material described in described second photoresist mask layer as mask etching, forms multiple grid.
Optionally, before the step of the photoresist mask layer forming the first patterning, first at described gate dielectric layer
Upper formation grid material；
After forming bag-shaped doped region and removing photoresist mask layer, continuously form grid material to predetermined thickness.
Optionally, the thickness of the grid material of described segment thickness is
Optionally, described grid comprises floating boom and be positioned at the control gate above described floating boom, at described floating boom and
Between described control gate, there is sealing coat.
Optionally, described sealing coat has three layers, including two-layer silicon oxide layer and be positioned at described two-layer oxidation
Silicon nitride layer between silicon.
Optionally, the width between the plurality of grid isBetween the plurality of grid, groove is deep wide
Ratio is 5.5.
Optionally, described ion implanting is oblique ion implanting.
Optionally, after forming multiple grid, also it is included in the plurality of grid both sides and forms source electrode and drain electrode
Step.
Optionally, the method forming source electrode and drain electrode is to continue to inject ion to be formed heavily doped in multiple grid both sides
Miscellaneous region.
The manufacture method of semiconductor device of the present invention, first forms gate dielectric layer, then shape in substrate
Become the photoresist mask layer of patterning, carry out ion implanting by the mask effect of photoresist mask layer, then
Remove photoresist mask layer and anneal, forming bag-shaped doped region.Afterwards, form grid material, then at grid
Form photoresist mask layer as hereinbefore in material, and etch formation grid.Owing to bag-shaped doped region is
Carry out ion implanting by the photoresist that depth-to-width ratio is less as mask in early stage and formed, therefore avoid grid
Interpolar groove depth-to-width ratio is too high and inhibition to bag-shaped injection.
Accompanying drawing explanation
Fig. 1 is the ion implanting schematic diagram that prior art forms bag-shaped doped region in the semiconductor device.
Fig. 2 is the flow chart of the manufacture method of semiconductor device described in one embodiment of the invention.
Fig. 3 to Fig. 9 is the side view of each step of the manufacture method of semiconductor device described in one embodiment of the invention.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.According to following explanation and
Claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all uses the simplest
The form changed and all use non-ratio accurately, only in order to convenient, aid in illustrating the embodiment of the present invention lucidly
Purpose.
As in figure 2 it is shown, the invention provides the manufacture method of a kind of semiconductor device, comprise the steps:
S1: substrate is provided, and forms gate dielectric layer at described substrate surface；
S2: form the photoresist mask layer of the first patterning in described grid material, and to light described in first
The region that photoresist mask layer exposes carries out ion implanting, to form bag-shaped doped region；
S3: remove described first photoresist mask layer, and continue to deposit grid material to predetermined thickness；
S4: form the photoresist mask layer of the second patterning, described second patterning in described grid material
Photoresist mask layer and the photoresist mask layer of the first patterning use identical mask plate to be formed；
S5: grid material described in the described second photoresist mask layer patterned as mask etching, formation is many
Individual grid.
In the present embodiment, illustrate as a example by memory device (such as flash memory) and of the present invention partly lead
The manufacture method of body device.Semiconductor device has multiple memory device, each memory device in the horizontal direction
There is floating boom and the control gate of upper and lower vertical distribution, but the present invention is not limited with memory device, relate to other high
During the ion implanting of aspect ratio trench, all can use method of the present invention.
The manufacture method of the semiconductor device of one embodiment of the invention is described in detail below in conjunction with Fig. 3 to Fig. 9.
As it is shown on figure 3, step S1 is first carried out, it is provided that substrate 100, and in described substrate 100 surface shape
Become gate dielectric layer 200.
Described substrate 100 can be monocrystal silicon, polysilicon or amorphous silicon substrate, it is also possible to is silicon, germanium, silicon
The substrate that the material such as germanium compound or GaAs is formed, described substrate 100 can have epitaxial layer or insulating barrier
Silicon-on, it is also possible to be other semi-conducting materials, do not enumerate.Substrate 100 is formed
Gate dielectric layer 200 covers the surface of substrate 100, concrete forming method can be chemical vapor deposition or
Thermal oxide.
After forming gate dielectric layer 200, described gate dielectric layer 200 forms barrier layer.Described barrier layer
Purpose is to protect gate dielectric layer 200 so that gate dielectric layer 200 does not contacts with photoresist layer in subsequent technique,
Avoid photoresist that gate dielectric layer 200 is polluted.After subsequent optical carving technology terminates, remove described resistance
Barrier.As it is shown on figure 3, in the present embodiment, described barrier layer is grid material 300.Due to subsequent step
In be also required on gate dielectric layer 200 formed grid material 300, therefore the most directly formed grid material
300 as barrier layer, can save after photoetching process terminates, remove the step on described barrier layer.Walk at this
In Zhou, the thickness of the grid material 300 of formation isDescribed grid material 300 is specially many
Crystal silicon, but the present invention is not limited.
As shown in Figure 4 and Figure 5, then perform step S2, described grid material 300 is formed patterning
Photoresist mask layer 400, and the region exposing described photoresist mask layer 400 carries out ion implanting, with
Form bag-shaped doped region.Wherein, the method for the photoresist mask layer 400 forming the first patterning is: at grid
The surface-coated photoresist of dielectric layer 200, is then exposed photoresist by a mask plate, finally shows
Shadow removes part photoresist, forms the first photoresist mask layer 400 with the surface at gate dielectric layer 200..
Referring to Fig. 5, in order to form bag-shaped doped region 110 in substrate 100, described ion implanting is oblique
Ion implanting (has an angle relative to the direction on vertical substrates surface, is generally selected 30-60 degree, be preferably
45 degree, direction as shown by the arrows in Figure 5) so that the described bag-shaped doped region 110 eventually formed does not only exists
In the region that the first photoresist mask layer 400 exposes, also diffuse to what the first photoresist mask layer 400 exposed
The both sides in region, the subregion immediately below the i.e. first photoresist mask layer 400.
As shown in Figure 6, then perform step S3, remove described first photoresist mask layer 400, and continue
Deposition grid material 300 is to predetermined thickness.
In order to optimize bag-shaped doped region 110 so that the ion of injection has preferably distribution, removing the first photoetching
After glue mask layer 400, also include the step that bag-shaped doped region 110 is annealed.
In the present embodiment, as shown in Figure 6, the material on the barrier layer 300 owing to being formed before is electric with grid
The material of pole layer is identical, the thickness of the grid electrode layer formed the most in step s3 and the stop being previously formed
The thickness sum of layer meets predetermined gate.Wherein it is desired to the grid ultimately formed comprise floating boom,
Control gate and the sealing coat 330 being formed between described floating boom and described control gate, i.e. by described sealing coat
Floating boom and control gate are separated by 330.Specifically, first formation floating boom material 310 to institute on barrier layer 300
Need thickness, in floating boom material 310, then form sealing coat 330, finally formed on sealing coat 330 and control
Grid material 320.Wherein, sealing coat 330 can be ONO structure, i.e. includes two-layer silicon oxide layer and position
Silicon nitride layer between described two-layer silicon oxide.
As it is shown in fig. 7, then perform step S4, described grid material 300 forms the second patterning
Photoresist mask layer 400 ', the photoresist mask layer 400 ' of described second patterning and the photoetching of the first patterning
Glue mask layer 400 uses identical mask plate to be formed.Concrete method is, on the surface of grid material 300
Coating photoresist, is then exposed photoresist by the mask plate identical with step S2, finally develops
Remove part photoresist, to be formed on the surface of grid material 300 and the photoresist of identical patterns in step S2
Mask layer.Forming the purpose with the photoresist mask layer of step S2 identical patterns is, it is ensured that the bag being previously formed
Shape doped region 110 is placed exactly in the both sides of the grid being subsequently formed.
As shown in Figure 8, finally perform step S5, with the photoresist mask layer 400 ' of described second patterning be
Grid material 300 described in mask etching, forms multiple grid.In the present embodiment, multiple grid that etching is formed
Pole 500 all comprises floating boom, control gate and the sealing coat between floating boom, control gate.
With continued reference to Fig. 8, after formation of the gate, the photoresist mask layer 400 ' of the second patterning is removed.Such as figure
Shown in 9, after removing the photoresist mask layer 400 ' of the second patterning, also it is included in described grid 500 both sides
Substrate 100 in form the step of source electrode and drain electrode respectively.Abovementioned steps has been formed bag-shaped doped region 110,
It is as district is lightly doped；When the follow-up source/drain 120 of formation respectively, substrate 100 is carried out again ion note
Enter, form heavily doped region, be source/drain 120.Finally, bag-shaped doped region 110 is positioned at source/drain 120
Both sides.
It should be noted that above-described embodiment is only the preferred embodiments of the present invention.In described substrate 100
After surface forms the step of gate dielectric layer 200, directly can form first on the surface of gate dielectric layer 200
The photoresist mask layer 400 of patterning.Form bag-shaped doped region and remove the photoresist mask of the first patterning
After layer 400, property forms the grid material 300 of predetermined thickness again.
The present invention before the gate is formed, first passes through the mask effect of photoresist to the follow-up grid needing and being formed
Both sides carry out ion implanting, form bag-shaped doped region.Then photoresist mask, then shape according to a conventional method are removed
Become multiple grid.Owing in the present embodiment, width between grid is onlyBetween multiple grids, groove is deep
Wide ratio is all higher than 5.5, and in photoresist mask layer, the depth-to-width ratio of groove is respectively less than 2, therefore by the method energy
Solving in prior art when carrying out bag-shaped injection, the ion tilting injection falls the side of grid, it is impossible to
The basal region of side forms the technical problem of bag-shaped doped region under the gate.
Obviously, those skilled in the art can carry out various change and modification without deviating from the present invention to invention
Spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of equivalent technologies, then the present invention is also intended to change and including modification include these.
Claims (9)
1. the manufacture method of a semiconductor device, it is characterised in that including:
Substrate is provided, and forms gate dielectric layer at described substrate surface；
Described gate dielectric layer forms the photoresist mask layer of the first patterning, to described first patterning
The region that photoresist mask layer exposes carries out ion implanting, to form bag-shaped doped region；
Remove the photoresist mask layer of described first patterning, and deposition grid material on the substrate；
Described grid material is formed the photoresist mask layer of the second patterning, the light of described second patterning
The photoresist mask layer of photoresist mask layer and the first patterning uses identical mask plate to be formed；
Grid material described in described second photoresist mask layer as mask etching, forms multiple grid.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that:
Before the step of the photoresist mask layer forming the first patterning, on described gate dielectric layer, first form grid
Pole material；
After forming bag-shaped doped region and removing photoresist mask layer, continuously form grid material to predetermined thickness.
3. the manufacture method of semiconductor device as claimed in claim 2, it is characterised in that described part is thick
The thickness of the grid material of degree is
4. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described grid bag
Containing floating boom and be positioned at the control gate above described floating boom, between described floating boom and described control gate, there is isolation
Layer.
5. the manufacture method of semiconductor device as claimed in claim 4, it is characterised in that described sealing coat
Have three layers, including two-layer silicon oxide layer and the silicon nitride layer between described two-layer silicon oxide.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that the plurality of grid
Width between pole isBetween the plurality of grid, the depth-to-width ratio of groove is 5.5.
7. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that described ion is noted
Enter for oblique ion implanting.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterised in that form multiple grid
After extremely, also it is included in the plurality of grid both sides and forms source electrode and the step of drain electrode.
9. the manufacture method of semiconductor device as claimed in claim 8, it is characterised in that formed source electrode and
The method of drain electrode is to continue to inject ion to form heavily doped region in multiple grid both sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510019215.2A CN105845571B (en) | 2015-01-14 | 2015-01-14 | The manufacturing method of semiconductor devices |
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| CN201510019215.2A CN105845571B (en) | 2015-01-14 | 2015-01-14 | The manufacturing method of semiconductor devices |
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| CN105845571A true CN105845571A (en) | 2016-08-10 |
| CN105845571B CN105845571B (en) | 2019-05-03 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000038245A1 (en) * | 1998-12-21 | 2000-06-29 | Lattice Semiconductor Corporation | Dual pocket, two sided program/erase non-volatile memory cell |
| US20020182829A1 (en) * | 2001-05-31 | 2002-12-05 | Chia-Hsing Chen | Method for forming nitride read only memory with indium pocket region |
| CN1405864A (en) * | 2001-08-14 | 2003-03-26 | 旺宏电子股份有限公司 | Method for manufacturing metal oxide semicondustor transistor |
| CN1947244A (en) * | 2004-01-12 | 2007-04-11 | 斯班逊有限公司 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell |
-
2015
- 2015-01-14 CN CN201510019215.2A patent/CN105845571B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000038245A1 (en) * | 1998-12-21 | 2000-06-29 | Lattice Semiconductor Corporation | Dual pocket, two sided program/erase non-volatile memory cell |
| US20020182829A1 (en) * | 2001-05-31 | 2002-12-05 | Chia-Hsing Chen | Method for forming nitride read only memory with indium pocket region |
| CN1405864A (en) * | 2001-08-14 | 2003-03-26 | 旺宏电子股份有限公司 | Method for manufacturing metal oxide semicondustor transistor |
| CN1947244A (en) * | 2004-01-12 | 2007-04-11 | 斯班逊有限公司 | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell |
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| CN105845571B (en) | 2019-05-03 |
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