US20160211321A1 - Buried Trench Isolation in Integrated Circuits - Google Patents
Buried Trench Isolation in Integrated Circuits Download PDFInfo
- Publication number
- US20160211321A1 US20160211321A1 US15/012,644 US201615012644A US2016211321A1 US 20160211321 A1 US20160211321 A1 US 20160211321A1 US 201615012644 A US201615012644 A US 201615012644A US 2016211321 A1 US2016211321 A1 US 2016211321A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- trench
- devices
- buried
- isolator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 239000003989 dielectric material Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 55
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000000034 method Methods 0.000 description 63
- 230000008569 process Effects 0.000 description 34
- 238000004519 manufacturing process Methods 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 230000000977 initiatory effect Effects 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000011343 solid material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
Definitions
- FIGS. 4A-4C illustrates a cross-sectional view of an IC including a including a buried trench at select stages of its fabrication process, according to an embodiment.
- FIG. 7 illustrates a flowchart for a method of fabricating an IC, according to a second embodiment.
- devices 101 a and 101 b may each represent a field-effect transistor (FET) including doped regions and a gate structure (not shown).
- FET field-effect transistor
- Devices 101 a and 101 b may be similar in structure and function.
- devices 101 a and 101 b may be two distinct devices.
- devices 101 may be positioned on a top surface 102 a of substrate 102 .
- buried trench 104 may provide electrical isolation between the electronic processes of devices 101 a and 101 b within substrate 102 , according to an embodiment.
- FIG. 1B illustrates a cross-sectional view of an IC 100 b according to an embodiment.
- IC 100 b is similar to IC 100 a as described above, therefore only differences between IC 100 a and 100 b are described herein.
- buried trenches 106 are cavities empty of any solid material.
- the buried trenches 104 may, for example, contain air.
- the formation of the buried trench 104 may comprise a filling process followed by an etch-back process.
- the filling process may be performed by depositing a layer 206 of dielectric material over the partially fabricated IC 100 a of FIG. 2A such that at least trench 202 may be filled, as shown in FIG. 2B .
- the deposition of layer 206 may be performed using any conventional deposition methods suitable for dielectric materials. For example, dielectric materials such as silicon oxide or silicon nitride may be deposited for layer 206 using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. Following the deposition of layer 206 , an etch-back process may be performed to remove layer 206 from all areas except for a portion 212 , as shown in FIG. 2C .
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the reshaping of the substrate may include using hydrogen annealing to cause the substrate material to flow.
- the hydrogen annealing comprises annealing in temperature range of approximately 600° C. to approximately 1150° C.
- the hydrogen annealing comprises annealing in pressure range of approximately 0.1 Pa to approximately 100 kPa.
- seed layers 304 a and 304 b are formed before initiating reshaping of the substrate material surrounding portion 210 of the trench 104 .
- Seed layers 304 a may be formed on the dielectric layer 208 according to an embodiment.
- Seed layer 304 b may be formed on the surface 102 a of substrate 102 outside trench 104 .
- Forming the buried trench 105 may include reshaping portion of the substrate surrounding the open end 204 of the trench 202 in FIG. 2A .
- Reshaping may include causing the portion of substrate material surrounding the open end 204 of the trench 202 to flow such that the opening 204 is closed.
- hydrogen annealing is used to cause the substrate material to flow.
- FIG. 4C illustrates cross-sectional views of partially fabricated IC 100 b after formation of buried trench 104 during an embodiment.
- FIG. 6 illustrates a flowchart for a method 600 of fabricating an IC, e.g., IC 100 a shown in FIG. 1A , according to an embodiment. Solely for illustrative purposes, the steps illustrated in FIG. 6 will be described with reference to example fabrication process illustrated in FIGS. 2A-2E . It is to be appreciate not all steps may be required, nor occur in the order shown.
- trench 202 may be filled by depositing a layer 206 of dielectric material such as silicon oxide or silicon nitride.
- the deposition of layer 206 may be performed using, for example, a CVD or an ALD process.
- an etch-back process is used to remove a layer from all areas except for portion 208 , as described above with reference to FIG. 2C .
- step 608 the open portion 204 of the trench is closed by causing the substrate material surrounding it to flow by, for example, Hydrogen annealing.
- the above method 600 may additionally or alternatively include any of the steps or sub-steps described above with respect to FIGS. 2A-2E , as well as any of their modifications. Further, the above description of the example method 600 should not be construed to limit the description of IC 100 a described above.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
- This application is a divisional application of U.S. application Ser. No. 14/207,303, filed Mar. 12, 2014, which is related to U.S. application Ser. Nos. 14/048,527, and 14/048,863, all of which are incorporated by reference herein in their entireties.
- 1. Field
- The present application relates to the fabrication of trenches buried in substrates of integrated circuits.
- 2. Background
- With the advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, and high speed communication systems. To meet these demands, the semiconductor industry continues to scale down dimension of devices, and also increase packing density of devices on an integrated circuit (IC) to accommodate a larger number of devices on an IC. However, scaling down of devices to smaller dimensions can introduce short channel effects in the devices due to the short channel lengths (about approximately 100 nm or less) of the scaled down devices. In addition, closely spaced devices may suffer from disturbances such as electron leakage, noise coupling, or electrostatic coupling. These drawbacks can degrade the operating characteristics and performance of the devices over time. Thus, it is desirable to improve performance of devices in such high density ICs.
- According to an embodiment, an IC includes a substrate, a first device and a second device, that may exist next to each other, and are formed on a surface of the substrate. Each of the first and the second devices include a gate structure. The IC further includes an isolator formed within the substrate and positioned space-wise between the first and the second device. The isolator includes one or more cavities buried under the substrate to isolate the two devices. In an embodiment the one or more cavities comprises one cavity and the one cavity is filled with a dielectric material.
- According to another embodiment, a method for fabricating an integrated circuit (IC) is provided. The method includes forming a trench in a substrate. The trench having a closed end within the substrate and an open end adjacent a surface of the substrate. The method further includes initiating a reshaping of portion of the substrate surrounding the open end of the trench. The method further includes closing the open end of the trench with substrate martial to form an isolation region within the substrate. The method further includes creating first and second devices on the surface of the substrate on opposite sides of the isolation region.
- According to another embodiment, a method for fabricating an IC is provided. The method includes forming a trench in a substrate. The method further includes depositing dielectric material in the trench such that the layer of dielectric material substantially fills the trench. The method further includes removing the dielectric material from a top portion of the trench. The method further includes closing the open end of the trench such that the substrate material fills the top portion of the trench.
- Further features and advantages of the present disclosure, as well as the structure and operation of various embodiments of the present disclosure, are described in detail below with reference to the accompanying drawings. It is noted that the present disclosure is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.
- The accompanying drawings illustrate the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the pertinent art to make and use the disclosure.
-
FIGS. 1A-1C each illustrate a cross-sectional view of an IC, according to an embodiment. -
FIGS. 2A-2E illustrates a cross-sectional view of an IC including a buried trench at select stages of its fabrication process, according to an embodiment. -
FIGS. 3A-3C illustrates a cross-sectional view of an IC including a buried trench at select stages of its fabrication process, according to an embodiment. -
FIGS. 4A-4C illustrates a cross-sectional view of an IC including a including a buried trench at select stages of its fabrication process, according to an embodiment. -
FIGS. 5A-5E illustrate cross-sectional views of an IC including one or more buried trenches at select stages of its fabrication process, according to an embodiment. -
FIG. 6 illustrates a flowchart for a method of fabricating an IC, according to a first embodiment. -
FIG. 7 illustrates a flowchart for a method of fabricating an IC, according to a second embodiment. - The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical or similar elements. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
- The following Detailed Description refers to accompanying drawings to illustrate embodiments consistent with the disclosure. The embodiment(s) described, and references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- The embodiments described herein are provided for illustrative purposes, and are not limiting. Other embodiments are possible, and modifications may be made to the embodiments within the spirit and scope of the disclosure. Therefore, the Detailed Description is not meant to limit the present disclosure. Rather, the scope of the present disclosure is defined only in accordance with the following claims and their equivalents.
- The following Detailed Description of the embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge of those skilled in relevant art(s), readily modify and/or adapt for various applications such exemplary embodiments, without undue experimentation, without departing from the spirit and scope of the disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and plurality of equivalents of the exemplary embodiments based upon the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
- Those skilled in the relevant art(s) will recognize that this description may be applicable to many various semiconductor devices, and should not be limited to any particular type of semiconductor devices. Before describing the various embodiments in more detail, further explanation shall be given regarding certain terms that may be used throughout the descriptions.
- In embodiments, the term “etch” or “etching” or “etch-back” generally describes a fabrication process of patterning a material, such that at least a portion of the material remains after the etch is completed. For example, generally the process of etching a semiconductor material involves the steps of patterning a masking layer (e.g., photoresist or a hard mask) over the semiconductor material, subsequently removing areas of the semiconductor material that are no longer protected by the mask layer, and optionally removing remaining portions of the mask layer. Generally, the removing step is conducted using an “etchant” that has a “selectivity” that is higher to the semiconductor material than to the mask layer. As such, the areas of semiconductor material protected by the mask would remain after the etch process is complete. However, the above is provided for purposes of illustration, and is not limiting. In another example, etching may also refer to a process that does not use a mask, but still leaves behind at least a portion of the material after the etch process is complete.
- The above description serves to distinguish the term “etching” from “removing.” In an embodiment, when etching a material, at least a portion of the material remains behind after the process is completed. In contrast, when removing a material, substantially all of the material is removed in the process. However, in other embodiments, ‘removing’ may incorporate etching.
- In an embodiment, the terms “deposit” or “dispose” describe the act of applying a layer of material to the substrate. Such terms are meant to describe any possible layer-forming technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, atomic layer deposition, electroplating, etc.
- In an embodiment, the term “substrate” describes a material onto which subsequent material layers are added. In embodiments, the substrate itself may be patterned and materials added on top of it may also be patterned, or may remain without patterning. Furthermore, “substrate” may be any of a wide array of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive such as a glass or sapphire wafer.
- In an embodiment, the term “substantially perpendicular,” in reference to a topographical feature's sidewall, generally describes a sidewall disposed at an angle ranging between about 85 degrees and 90 degrees with respect to the substrate.
- In an embodiment, the term “substantially in contact” means the elements or structures in substantial contact can be in physical contact with each other with only a slight separation from each other.
- In an embodiment, devices fabricated in and/or on the substrate may be in several regions of the substrate, and these regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap.
- An Integrated Circuit According to a First Embodiment
-
FIG. 1A illustrates a cross-sectional view of anIC 100 a according to an embodiment. In one example,IC 100 a may include asubstrate 102, one ormore devices 101, and a trench 104 (e.g., a buried trench).Devices 101 as shown inFIG. 1 include only twodevices devices 101 may include any number of devices. -
Substrate 102 may be a silicon (Si) substrate implanted with p-type carriers to be a p-type Si substrate, according to an example embodiment. The p-type carriers may be provided by p-type materials, such as, but not limited to, boron. Alternatively,substrate 102 may be a p-type well formed in an n-type Si substrate or well (not shown). The N-type Si substrate is formed by implanting n-type carriers that are provided by n-type materials, such as, but not limited to, phosphorus. - In an example,
devices Devices devices devices 101 may be positioned on atop surface 102 a ofsubstrate 102. - In one example, buried
trench 104 may be filled with a dielectric material. The dielectric material may be, for example, oxide or nitride. - In accordance with an embodiment, buried
trench 104 may be positioned insubstrate 102 betweendevices trench 104 is shown inFIG. 1A —to comprise a vertical cross-section having a rectangular perimeter. In alternate embodiments buriedtrench 104 may comprise vertical cross-sections having any geometric shaped perimeters (e.g., trapezoidal). -
Buried trench 104 may run parallel to a bitline or thesubstrate surface 102, and it may have a greater depth than width, in an embodiment. In an example, buriedtrench 104 may comprise a vertical dimension of about 100 nm-400 nm and it may be positioned about 100 nm or less under thesurface 102 a ofsubstrate 102. - During operation of
devices 101, electronic processes may be carried out within a region ofsubstrate 102. These electronic processes ofdevice 101 a may create disturbances such as, but not limited to, current leakage, noise coupling, or electrostatic coupling that may negatively affect the electronic processes and as a result the performance ofadjacent device 101 b in instances wheredevices 101 are closely spaced onsubstrate 102. In such instances, buriedtrench 104 may provide electrical isolation between the electronic processes ofdevices substrate 102, according to an embodiment. - It should be noted that IC 100 is shown in
FIG. 1A as including only one arrangement of buriedtrench 104 interposed betweenadjacent devices devices 101 and buriedtrench 104, respectively. In addition, IC 100 may include other devices and functional units that are not shown for the sake of simplicity. - An Integrated Circuit According to a Second Embodiment
-
FIG. 1B illustrates a cross-sectional view of anIC 100 b according to an embodiment.IC 100 b is similar toIC 100 a as described above, therefore only differences betweenIC -
IC 100 b may include buriedtrench 105.Buried trench 105 may be a cavity that is empty, i.e., without any solid material. The buriedtrench 105 may, for example, contain air. - An Integrated Circuit According to a Third Embodiment
-
FIG. 1C illustrates a cross-sectional view of anIC 100 c according to an embodiment.IC 100 c is similar toIC 100 a as described above, therefore only differences betweenIC - In one example,
IC 100 c may include multiple buriedtrenches 106. In the example embodiment shown inFIG. 1C , buriedtrenches 106 includescavities trenches 106 as shown inFIG. 1C include three cavities for the sake of simplicity. However, as would be understood by a person of skilled in the art based on the description herein, buriedtrenches 106 may include any number of cavities. - In an embodiment, buried
trenches 106 are cavities empty of any solid material. The buriedtrenches 104 may, for example, contain air. - An Example Method for Fabricating an Integrated Circuit According to a First Embodiment
-
FIGS. 2A-2E illustrate cross-sectional views of partially fabricatedIC 100 a during formation of buriedtrench 104, according to an embodiment. For the sake of simplicity,devices 101 are not shown in the figures for illustrating example methods of forming a buried trench. In some embodiments,devices 101 may be fabricated before forming a buried trench. In some other embodiments,devices 101 may be fabricated after forming a buried trench. -
FIG. 2A illustrates a cross-sectional view of a partially fabricatedIC 100 a after formation oftrench 202 insubstrate 102. Trench 202 may be formed by any conventional etching methods suitable for etching the material ofsubstrate 102. For example, a dry etch process such as, but not limited to, reactive ion etching (RIE) may be performed to remove the material ofsubstrate 102 for the formation oftrench 202. In an embodiment,trench 202 has a closed end within the substrate and anopen end 204 adjacent asurface 102 a of thesubstrate 102. - The formation of the buried
trench 104 may comprise a filling process followed by an etch-back process. The filling process may be performed by depositing alayer 206 of dielectric material over the partially fabricatedIC 100 a ofFIG. 2A such that atleast trench 202 may be filled, as shown inFIG. 2B . The deposition oflayer 206 may be performed using any conventional deposition methods suitable for dielectric materials. For example, dielectric materials such as silicon oxide or silicon nitride may be deposited forlayer 206 using a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. Following the deposition oflayer 206, an etch-back process may be performed to removelayer 206 from all areas except for aportion 212, as shown inFIG. 2C . - The formation of filled
portion 212 may be followed by initiating a reshaping ofportion 210 of the substrate that surrounds theopen end 204 of the trench. Initiating the reshaping ofportion 210 may include causing the substratematerial surrounding portion 210 to flow and cover the dielectric layer in theportion 212 and to create the buriedtrench 104 as shown in the example embodiment ofFIG. 2D . The reshaping process may continue to close thesubstrate area 214 on top of the buriedtrench 104. The reshaping of thesubstrate area 214 may continue until thesurface 102 a of thesubstrate 102 is substantially even over the buriedtrench 104, as shown in example embodiment ofFIG. 2E . - In an embodiment, the reshaping of the substrate may include using hydrogen annealing to cause the substrate material to flow. In an embodiment, the hydrogen annealing comprises annealing in temperature range of approximately 600° C. to approximately 1150° C. In an embodiment, the hydrogen annealing comprises annealing in pressure range of approximately 0.1 Pa to approximately 100 kPa.
- It should be understood that the various layers illustrated during the example fabrication process of
IC 100 a are not necessarily drawn to scale. In addition, the above description is meant to provide a general overview of select steps involved in formingIC 100 a shown inFIG. 1A and that, in actual practice, more features and/or fabrication steps may be performed additionally or alternatively to that described herein to formIC 100 a, as would be understood by one skilled in the art given the description herein. - An Example Method for Fabricating an Integrated Circuit According to a Second Embodiment
-
FIGS. 3A-3C illustrate cross-sectional views of partially fabricatedIC 100 a during formation of buriedtrench 104, according to an embodiment. According to the embodiment, before initiating the reshaping of the substratematerial surrounding portion 210 of thetrench 104, aseed layer 302 may be formed on thedielectric layer 208. - In an example, embodiment shown in
FIG. 3B , seed layers 304 a and 304 b are formed before initiating reshaping of the substratematerial surrounding portion 210 of thetrench 104. Seed layers 304 a may be formed on thedielectric layer 208 according to an embodiment.Seed layer 304 b may be formed on thesurface 102 a ofsubstrate 102outside trench 104. - In an example embodiment shown in
FIG. 3C ,seed layer 306 may be formed before initiating reshaping of the substratematerial surrounding portion 210 oftrench 104.Seed layer 306 may be formed such that it covers top of thedielectric layer 208, and sidewall ofportion 210 oftrench 104 andtop surface 102 a ofsubstrate 102. - A seed layer may comprise a material that helps smooth reshaping or flow of the substrate
material surrounding section 210 and closing of opening 204 oftrench 104. A seed layer may comprise materials containing Silicon or Germanium which won't produce dielectric material. In an embodiment, a seed layer comprises same material as the substrate material. - It should be understood that the various layers illustrated during the example fabrication process of
IC 100 a are not necessarily drawn to scale. In addition, the above description is meant to provide a general overview of select steps involved in formingIC 100 a shown inFIG. 1A and that, in actual practice, more features and/or fabrication steps may be performed additionally or alternatively to that described herein to formIC 100 a, as would be understood by one skilled in the art given the description herein. - An Example Method for Fabricating an Integrated Circuit According to a Third Embodiment
-
FIGS. 4A-C illustrate an example fabrication process for formingIC 100 b shown inFIG. 1B , according to an embodiment. For the sake of simplicity,devices 101 are not shown in the figures for illustrating example methods of forming a buried trench. In some embodiments,devices 101 may be fabricated before forming a buried trench. In some other embodiments,devices 101 may be fabricated after forming a buried trench. -
FIG. 4A illustrates a cross-sectional view of a partially fabricatedIC 100 b after formation oftrench 202 insubstrate 102. Trench 202 may be formed by methods described with respect toFIG. 2A . - Forming the buried
trench 105 may include reshaping portion of the substrate surrounding theopen end 204 of thetrench 202 inFIG. 2A . Reshaping may include causing the portion of substrate material surrounding theopen end 204 of thetrench 202 to flow such that theopening 204 is closed. In an embodiment, hydrogen annealing is used to cause the substrate material to flow. -
FIG. 4B illustrates cross-sectional views of partially fabricatedIC 100 b during formation of buriedtrench 105 during an embodiment. After causing thesubstrate material 404 to flow, the embodiment will close the opening of the trench, such thatarea 402 is enclosed bysubstrate material 404. -
FIG. 4C illustrates cross-sectional views of partially fabricatedIC 100 b after formation of buriedtrench 104 during an embodiment. - An Example Method for Fabricating an Integrated Circuit According to a Fourth Embodiment
-
FIGS. 5A-5E illustrate an example fabrication process for formingIC 100 c, according to an embodiment. In an embodiment, the process shown inFIGS. 5A-5D is used before devices 100 are formed. In another embodiment, the process shown inFIGS. 5A-5D is used after devices 100 are formed. -
FIG. 5A illustrates a cross-sectional view of a partially fabricatedIC 100 c after formation oftrench 202 insubstrate 102. Trench 202 may be formed by methods described with respect toFIG. 2A . - Forming the buried
trenches 106 may include reshaping portions of the substrate at more than one location along thetrench 202 shown inFIG. 5A . Reshaping may include causing the portion of substrate material surrounding a section of thetrench 202, forexample section 502 shown inFIG. 5B , to flow such that thetrench 202 is closed in that portion. - The reshaping of the substrate
material surrounding portion 502 of thetrench 202 may continue until buriedtrench 106 a is formed, as shown, for example, inFIG. 5C . In an embodiment, another buried trench above the buriedtrench 106 a may be created by reshaping substrate material for example aroundportion 504 of thetrench 202. The reshaping of the substrate material may continue until the buriedtrench 106 b is formed, as shown, for example, inFIG. 5D . - Another buried trench above the buried
trench 106 b may also be formed by closing theopening 204 of thetrench 202 in a manner similar to the process explained inFIGS. 4A-C above, as shown, for example, inFIG. 5D . The reshaping of the substrate material may continue until the buriedtrench 106 c is formed, as shown, for example, inFIG. 5E . - In an embodiment, hydrogen annealing is used to cause the substrate material to flow. In another embodiment, buried
trenches 106 may be empty of any solid material. The buriedtrenches 106 may, for example, contain air. - It should be understood that the various layers illustrated during the example fabrication process of
IC 100 c are not necessarily drawn to scale. In addition, the above description is meant to provide a general overview of select steps involved in formingIC 100 c shown inFIG. 1C and that, in actual practice, more features and/or fabrication steps may be performed additionally or alternatively to that described herein to formIC 100 c, as would be understood by one skilled in the art given the description herein. -
FIG. 6 illustrates a flowchart for amethod 600 of fabricating an IC, e.g.,IC 100 a shown inFIG. 1A , according to an embodiment. Solely for illustrative purposes, the steps illustrated inFIG. 6 will be described with reference to example fabrication process illustrated inFIGS. 2A-2E . It is to be appreciate not all steps may be required, nor occur in the order shown. - In
step 602,trench 202 may be formed in thesubstrate 102, as shown inFIG. 2A , by a dry etch process such as, but not limited to, reactive ion etching (RIE) to remove the material ofsubstrate 102, according to an embodiment. - In
step 604,trench 202 may be filled by depositing alayer 206 of dielectric material such as silicon oxide or silicon nitride. The deposition oflayer 206 may be performed using, for example, a CVD or an ALD process. Instep 606 an etch-back process is used to remove a layer from all areas except forportion 208, as described above with reference toFIG. 2C . - In
step 608 theopen portion 204 of the trench is closed by causing the substrate material surrounding it to flow by, for example, Hydrogen annealing. - It should be noted that, although the above method description and related figures describe fabricating only one arrangement of buried
trench 104 interposed betweenadjacent devices 101 for the sake of simplicity. However, as would be understood by a person of skilled in the art based on the description herein, the above steps may be applied to fabricate any number of such arrangements with devices and trenches similar todevices 101 andtrench 104, respectively. - Those skilled in the relevant art(s) will recognize that the
above method 600 may additionally or alternatively include any of the steps or sub-steps described above with respect toFIGS. 2A-2E , as well as any of their modifications. Further, the above description of theexample method 600 should not be construed to limit the description ofIC 100 a described above. - Example Steps for Fabricating an Integrated Circuit According to a Second Embodiment
-
FIG. 7 illustrates a flowchart for amethod 700 of fabricating an IC, e.g.,IC 100 b shown inFIG. 1B , according to an embodiment. Solely for illustrative purposes, the steps illustrated inFIG. 7 will be described with reference to example fabrication process illustrated inFIGS. 4A-4C . It is to be appreciate not all steps may be required, nor occur in the order shown. - In
step 702,trench 202 may be formed in thesubstrate 102, as shown inFIG. 2 , by a dry etch process such as, but not limited to, reactive ion etching (RIE) to remove the material ofsubstrate 102, according to an embodiment. Instep 704 theopen end 204 of the trench is closed to form buriedtrench 105. Closing of the open end of the trench may be done by causing the substrate material surrounding it to flow, for example by Hydrogen annealing. - At
step 706,memory cell devices 101 are formed on both sides of thetrench 202. - It should be noted that, although the above method description and related figures describe fabricating only one arrangement of buried
trench 104 interposed betweenadjacent devices 101 for the sake of simplicity. However, as would be understood by a person of skilled in the art based on the description herein, the above steps may be applied to fabricate any number of such arrangements with devices and trenches similar todevices 101 andtrench 105, respectively. - Those skilled in the relevant art(s) will recognize that the
above method 700 may additionally or alternatively include any of the steps or sub-steps described above with respect toFIGS. 4A-4C , as well as any of their modifications. Further, the above description of theexample method 700 should not be construed to limit the description ofIC 100 b described above. - It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections (if any), is intended to be used to interpret the claims. The Summary and Abstract sections (if any) may set forth one or more but not all embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure or the appended claims in any way.
- Embodiments have been described herein with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined as long as the specified functions and relationships (or equivalents thereof) are appropriately performed. Also, alternative embodiments may perform functional blocks, steps, operations, methods, etc. using orderings different than those described herein.
- The breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (21)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/012,644 US20160211321A1 (en) | 2014-03-12 | 2016-02-01 | Buried Trench Isolation in Integrated Circuits |
US16/226,389 US20190198611A1 (en) | 2014-03-12 | 2018-12-19 | Buried Trench Isolation in Integrated Circuits |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/207,303 US9252026B2 (en) | 2014-03-12 | 2014-03-12 | Buried trench isolation in integrated circuits |
US15/012,644 US20160211321A1 (en) | 2014-03-12 | 2016-02-01 | Buried Trench Isolation in Integrated Circuits |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/207,303 Division US9252026B2 (en) | 2014-03-12 | 2014-03-12 | Buried trench isolation in integrated circuits |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/226,389 Continuation US20190198611A1 (en) | 2014-03-12 | 2018-12-19 | Buried Trench Isolation in Integrated Circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160211321A1 true US20160211321A1 (en) | 2016-07-21 |
Family
ID=54069643
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/207,303 Active US9252026B2 (en) | 2014-03-12 | 2014-03-12 | Buried trench isolation in integrated circuits |
US15/012,644 Abandoned US20160211321A1 (en) | 2014-03-12 | 2016-02-01 | Buried Trench Isolation in Integrated Circuits |
US16/226,389 Abandoned US20190198611A1 (en) | 2014-03-12 | 2018-12-19 | Buried Trench Isolation in Integrated Circuits |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/207,303 Active US9252026B2 (en) | 2014-03-12 | 2014-03-12 | Buried trench isolation in integrated circuits |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/226,389 Abandoned US20190198611A1 (en) | 2014-03-12 | 2018-12-19 | Buried Trench Isolation in Integrated Circuits |
Country Status (1)
Country | Link |
---|---|
US (3) | US9252026B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230050255A1 (en) * | 2021-08-13 | 2023-02-16 | Applied Materials, Inc. | Seam removal in high aspect ratio gap-fill |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6268637B1 (en) * | 1998-10-22 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication |
US6570217B1 (en) * | 1998-04-24 | 2003-05-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US7019364B1 (en) * | 1999-08-31 | 2006-03-28 | Kabushiki Kaisha Toshiba | Semiconductor substrate having pillars within a closed empty space |
US8975684B2 (en) * | 2012-07-18 | 2015-03-10 | Samsung Electronics Co., Ltd. | Methods of forming non-volatile memory devices having air gaps |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6630714B2 (en) | 2001-12-27 | 2003-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer |
JP4031329B2 (en) | 2002-09-19 | 2008-01-09 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP4000087B2 (en) | 2003-05-07 | 2007-10-31 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
EP2327659B1 (en) * | 2009-11-30 | 2018-07-11 | IMEC vzw | Method of manufacturing a semiconductor device and semiconductor devices resulting therefrom |
KR101910500B1 (en) * | 2012-07-04 | 2018-10-22 | 에스케이하이닉스 주식회사 | Semiconductor device with vertical channel tranasistor and method of manufacturing semiconductor device |
US9437470B2 (en) * | 2013-10-08 | 2016-09-06 | Cypress Semiconductor Corporation | Self-aligned trench isolation in integrated circuits |
-
2014
- 2014-03-12 US US14/207,303 patent/US9252026B2/en active Active
-
2016
- 2016-02-01 US US15/012,644 patent/US20160211321A1/en not_active Abandoned
-
2018
- 2018-12-19 US US16/226,389 patent/US20190198611A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6570217B1 (en) * | 1998-04-24 | 2003-05-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6268637B1 (en) * | 1998-10-22 | 2001-07-31 | Advanced Micro Devices, Inc. | Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication |
US7019364B1 (en) * | 1999-08-31 | 2006-03-28 | Kabushiki Kaisha Toshiba | Semiconductor substrate having pillars within a closed empty space |
US8975684B2 (en) * | 2012-07-18 | 2015-03-10 | Samsung Electronics Co., Ltd. | Methods of forming non-volatile memory devices having air gaps |
Also Published As
Publication number | Publication date |
---|---|
US9252026B2 (en) | 2016-02-02 |
US20150262838A1 (en) | 2015-09-17 |
US20190198611A1 (en) | 2019-06-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9773708B1 (en) | Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI | |
US9741626B1 (en) | Vertical transistor with uniform bottom spacer formed by selective oxidation | |
US9741716B1 (en) | Forming vertical and horizontal field effect transistors on the same substrate | |
US8603893B1 (en) | Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates | |
US10236214B2 (en) | Vertical transistor with variable gate length | |
US11688784B2 (en) | Transistor layout to reduce kink effect | |
US10388747B1 (en) | Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure | |
US9917020B2 (en) | Methods for fabricating an integrated circuit having vertically overlapping short and long channel FinFETs | |
US9379104B1 (en) | Method to make gate-to-body contact to release plasma induced charging | |
US9590059B2 (en) | Interdigitated capacitor to integrate with flash memory | |
CN104766886A (en) | Finfet device and method | |
CN107492542A (en) | The manufacture method of semiconductor subassembly | |
US10256137B2 (en) | Self-aligned trench isolation in integrated circuits | |
US10475904B2 (en) | Methods of forming merged source/drain regions on integrated circuit products | |
US10037998B2 (en) | Semiconductor structures with deep trench capacitor and methods of manufacture | |
US10593688B2 (en) | Split-gate semiconductor device with L-shaped gate | |
US11810959B2 (en) | Transistor layout to reduce kink effect | |
US11233137B2 (en) | Transistors and methods of forming transistors using vertical nanowires | |
US10290712B1 (en) | LDMOS finFET structures with shallow trench isolation inside the fin | |
US20190198611A1 (en) | Buried Trench Isolation in Integrated Circuits | |
CN110571193B (en) | Method for manufacturing single diffusion blocking structure and method for manufacturing semiconductor device | |
CN105405890B (en) | Include the semiconductor devices and its manufacturing method of electrically charged side wall | |
US9391170B2 (en) | Three-dimensional field-effect transistor on bulk silicon substrate | |
US20150097224A1 (en) | Buried trench isolation in integrated circuits | |
CN113964036B (en) | Manufacturing method of semiconductor structure and electronic equipment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., NEW YORK Free format text: SECURITY INTEREST;ASSIGNOR:CYPRESS SEMICONDUCTOR CORPORATION;REEL/FRAME:039676/0237 Effective date: 20160805 |
|
AS | Assignment |
Owner name: SPANSION LLC, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUGINO, RINJI;XUE, LEI;LU, CHING-HUANG;AND OTHERS;SIGNING DATES FROM 20140311 TO 20140312;REEL/FRAME:042966/0242 |
|
AS | Assignment |
Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SPANSION LLC;REEL/FRAME:043184/0417 Effective date: 20150601 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, NEW YORK Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:CYPRESS SEMICONDUCTOR CORPORATION;REEL/FRAME:047797/0854 Effective date: 20171229 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: MUFG UNION BANK, N.A., CALIFORNIA Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:051209/0721 Effective date: 20191204 |
|
AS | Assignment |
Owner name: SPANSION LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MUFG UNION BANK, N.A.;REEL/FRAME:059410/0438 Effective date: 20200416 Owner name: CYPRESS SEMICONDUCTOR CORPORATION, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MUFG UNION BANK, N.A.;REEL/FRAME:059410/0438 Effective date: 20200416 |