CN105842264B - The localization method of failpoint and the failure analysis method of chip - Google Patents
The localization method of failpoint and the failure analysis method of chip Download PDFInfo
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- CN105842264B CN105842264B CN201510020474.7A CN201510020474A CN105842264B CN 105842264 B CN105842264 B CN 105842264B CN 201510020474 A CN201510020474 A CN 201510020474A CN 105842264 B CN105842264 B CN 105842264B
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Abstract
This application provides a kind of localization method of failpoint and the failure analysis methods of chip.Wherein, chip includes substrate and the device positioned at substrate, which includes：Reduction processing is carried out to close to device to the back side of chip；Ion beam bombardment is carried out to the back side of the chip after reduction processing, so that ion beam passes through device；And electronics beam scanning is carried out to the front of ion beam bombardment treated chip, with the position of the failpoint in positioning chip.The localization method carries out ion beam bombardment by the back side to the chip after reduction processing, so that ion beam passes through device and makes to generate breakdown area in device, to when being scanned to the surface to be measured of chip using electron beam, the surface charge generated on surface to be measured can be released from device surface along breakdown area, reduce influence of the surface charge to device surface potential, and then can accurately obtain the position of failpoint in device.
Description
Technical field
This application involves semiconductor integrated circuit technology fields, a kind of localization method in particular to failpoint and
The failure analysis method of chip.
Background technology
For chip failure analysis, the positioning of failpoint is very crucial, is generally determined by determining failpoint
The specific location of failpoint in chip, to analyze the failure mechanism of chip.In the localization method of failpoint, potential
It is a kind of accurate positioning method being widely used to compare positioning mode, it is scanned to sample surface to be measured using electron beam
To obtain failpoint position.
It is using the step of potential of scanning electron microscope (SEM) comparison positioning mode in the prior art：Sample treatment is arrived first
Current layer to be observed；Then utilizing in SEM has the once electron beam of 1~2kV accelerating potentials to current layer (table i.e. to be measured
Face) it is scanned；The position of failpoint is determined finally by the different weights shown on the SEM image of scanning.It is positioned
Principle is：It under the scanning of once electron beam, is led since its various structure is different to ground resistance in SEM on sample surface to be measured
Cause its surface potential different, to show different weights on SEM image, and then by the weight of SEM image come
Determine the position of failpoint.
However, when using electronics beam scanning sample, sample surfaces are bound to add up charge (generally positive charge).It is right
It is 55nm/65nm or the chip of dimensions above in size, a small amount of surface charge will not generate the positioning of failpoint very big
It influences, can still determine the position of failpoint.But with the diminution of device size (especially size be 28nm/32nm or
Following size), the enhancing of closeness and the complication of device architecture and doping process, sample surfaces can add up this of charge
A problem being amplified, can accumulate more charges (as shown in Figure 1) so as to cause the sample surfaces after scanning, can not be effective
Ground navigates to the position of failpoint.
For example, in using the potential of scanning electron microscope (SEM) comparison positioning mode, since surface charge has no idea to guide,
To which the surface potential of sample can be seriously affected, and the weight that SEM image is shown further is influenced, and then led to not effectively
Ground navigates to the position of failpoint.Fig. 2 shows the SEM figures obtained using the potential comparison positioning mode provided in the prior art
Picture figure it is seen that having multiple bright spots in SEM image, therefore can not determine the position of failpoint in device by bright spot
It sets.In view of the above-mentioned problems, there is presently no effective solution methods.
Invention content
The main purpose of the application is to provide a kind of localization method of failpoint and the failure analysis method of chip, with essence
Really obtain the position of failpoint in chip.
To achieve the goals above, according to the one side of the application, a kind of localization method of failpoint is provided, is used for
The position of failpoint in positioning chip, chip include substrate and the device in substrate, and localization method includes the following steps：It is right
The back side of chip carries out reduction processing to close to device；Ion beam bombardment is carried out to the back side of the chip after reduction processing, so that
It obtains ion beam and passes through device；And electronics beam scanning is carried out to the front of ion beam bombardment treated chip, with positioning chip
In failpoint position.
Further, after carrying out reduction processing to the back side of chip, the thickness of substrate is 200nm~300nm.
Further, in the ion beam bombardment the step of, ion beam voltage is 150kV~200kV.
Further, in the ion beam bombardment the step of, projectile is boron ion, phosphonium ion or ar atmo, when bombardment
Between be 10s~60s.
Further, device includes the trap being located in substrate and the source-drain electrode in trap, and the conduction type of trap and source
The conduction type of drain electrode is opposite；The ion beam bombardment the step of, ion beam passes through trap and enters in source-drain electrode.
Further, include to the step of front progress electronics beam scanning of chip：The front of chip is carried out at stripping
Reason is to close to the failpoint in chip；The front of chip is scanned to obtain SEM image using the electron beam of scanning electron microscope；
And the position of the failpoint in chip is determined using the bright-dark degree in SEM image.
Further, the accelerating potential of the electron beam of scanning electron microscope is 1~2kV.
Further, before the ion beam bombardment the step of, localization method further includes the back of the body to the chip after reduction processing
The step of face starts the cleaning processing.
Further, the step of cleaning treatment includes：Concussion processing is carried out to the back side of chip using ultrasonic wave；Using going
Ionized water is rinsed processing to the back side of concussion treated chip；And using air gun to rinsing the back of the body of treated chip
Processing is dried in face.
Further, the time for shaking processing is 60s~300s.
According to the another aspect of the application, the failure analysis method of chip is provided, includes to the failpoint in chip
Position is positioned, and the step of obtaining the feature image of failpoint in chip, to the position of the failpoint in chip into
The method of row positioning is above-mentioned localization method.
Using the technical solution of the application, the application carries out ion beam by the back side to the chip after reduction processing and bangs
It hits, so that ion beam passes through device and makes to generate breakdown area in device, in the table to be measured using electron beam to chip
When face is scanned, the surface charge generated on surface to be measured can be released from device surface along breakdown area, be reduced
Influence of the surface charge to device surface potential, and then can accurately obtain the position of failpoint in device.
Description of the drawings
The accompanying drawings which form a part of this application are used for providing further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 shows that the matrix after being scanned to sample using the potential comparison positioning mode provided in the prior art is cutd open
Face structural schematic diagram；
Fig. 2 shows the SEM images obtained using the potential comparison positioning mode provided in the prior art；
Fig. 3 is shown in the localization method for the failpoint that the application embodiment is provided, and is carried out to the back side of chip
Reduction processing is to close to the matrix cross-sectional view after device；
Fig. 4 is shown carries out ion beam bombardment to the back side of the chip after reduction processing shown in Fig. 3, so that ion beam
Matrix cross-sectional view after device；
Fig. 5 is shown carries out electronics beam scanning to the front of ion beam bombardment shown in Fig. 4 treated chip, with positioning
Matrix cross-sectional view behind the position of failpoint in chip；
Fig. 6 shows the SEM image that the localization method using the failpoint provided in the embodiment of the present application 1 obtains；With
And
Fig. 7 shows the failpoint that the failure analysis method using the chip provided in the embodiment of the present application 1 obtains
Feature image.
Specific implementation mode
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
It should be noted that term used herein above is merely to describe specific implementation mode, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is also intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or combination thereof.
For ease of description, herein can with use space relative terms, as " ... on ", " in ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, if the device in attached drawing is squeezed, it is described as " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also other different modes positioning (be rotated by 90 ° or be in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As described in background technology, when using electronics beam scanning sample, the sample surfaces after scanning can tire out
Accumulated charge, and charge has no idea to guide, and to seriously affect the surface potential of sample, and then causes to compare using potential
Positioning mode can not efficiently locate the position of failpoint.Present inventor studies regarding to the issue above, it is proposed that
A kind of localization method of failpoint, for the position of failpoint in positioning chip, chips include substrate and are located in substrate
Device.The localization method includes：Reduction processing is carried out to close to device to the back side of chip；To the chip after reduction processing
The back side carries out ion beam bombardment, so that ion beam passes through device；And to the front of ion beam bombardment treated chip into
Row electronics beam scanning, with the position of the failpoint in positioning chip.
Since ion beam bombardment can pass through device and make to generate breakdown area in device in above-mentioned localization method, thus
When being scanned to chip surface to be measured using electron beam, the surface charge that is generated on surface to be measured can from device surface along
Breakdown area is released, and reduces influence of the surface charge to device surface potential, and then can accurately obtain in device
The position of failpoint.
The illustrative embodiments of the localization method according to failpoint provided by the present application are described in more detail below.So
And these illustrative embodiments can be implemented by many different forms, and should not be construed to be limited solely to here
The embodiment illustrated.It should be understood that thesing embodiments are provided so that disclosure herein is thorough and complete
It is whole, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, in order to clear
Chu Qijian, expands the thickness of layer and region, and makes that identical device is presented with like reference characters, thus will omission pair
Their description.
Fig. 3 to Fig. 5 shows in the localization method of failpoint provided by the present application, the matrix obtained after each step
Cross-sectional view.Below in conjunction with Fig. 3 to Fig. 5, the localization method of failpoint provided herein is further illustrated.
First, reduction processing is carried out to close to device to the back side of chip, and then forms basal body structure as shown in Figure 3.
Above-mentioned reduction processing can reduce the energy that the ion beam bombardment in subsequent technique penetrates device, make Subsequent electronic beam scanning step
The surface charge of middle generation can be discharged more from device surface along substrate 10, to be conducive to the control of ion beam bombardment
System reduces the damage brought to device.
The thickness of reduction processing back substrate 10 can be set according to actual process demand.Preferably, to the back of the body of chip
After face carries out reduction processing, the thickness of substrate 10 is 200nm~300nm.At this point, bombarding energy in subsequent technique intermediate ion beam
Device is enough penetrated by smaller energy, enables the surface charge generated in Subsequent electronic beam scanning step more easily from device
Part surface is discharged along substrate 10, and to be more advantageous to the control of ion beam bombardment, further decreasing may be to device band
The damage come.Also, certain thickness substrate 10 is remained after reduction processing, so as to avoid since subsequent processes are to device
Failpoint can not position caused by part structural damage.
Above-mentioned substrate 10 can be monocrystalline silicon (Si) or silicon-on-insulator (SOI) etc., can also be other materials certainly,
Such as III-V compound such as GaAs etc..It can be chemical mechanical grinding to carry out the technique of reduction processing to the back side of chip
(CMP) or etch etc..Above-mentioned technique is state of the art, and details are not described herein.
It completes to carry out reduction processing to close to after the step of device, to the chip after reduction processing to the back side of chip
The back side carries out ion beam bombardment, so that ion beam passes through device, structure as shown in Figure 4.Due to ion beam to chip
The back side is bombarded, and so as to destroy the internal structure of chip, generates breakdown area 40, and then Subsequent electronic beam scanning is made to walk
The surface charge generated in rapid can easily be discharged from device surface along the breakdown area 40 for the device inside being destroyed
Fall.
In a preferred embodiment, device includes the trap 20 being located in substrate 10 and the source-drain electrode in trap 20
30, and the conduction type of the conduction type of trap 20 and source-drain electrode 30 is opposite；The ion beam bombardment the step of, ion beam passes through trap 20
And enter in source-drain electrode 30, structure is as shown in Figure 4.Specifically, semiconductor device structure can be applied to IGBT or MOSFET.
Since ion beam passes through trap 20 and enters in source-drain electrode 30, so as to destroy the source-drain area and trap of the devices such as MOSFET, IGBT
The PN junction of 20 compositions so that PN junction will not generate barrier effect to the surface charge generated in Subsequent electronic beam scanning step, into
And surface charge is enable to be easy to be discharged into ground from device surface along the breakdown area 40 for the device inside being destroyed.
In the above-mentioned ion beam bombardment the step of, it is suitable that those skilled in the art can select according to actual process demand
Accelerating potential technological parameter, it is preferable that ion beam voltage be 150kV~200kV.At this point, when projectile and its bombardment
Between can also be set according to actual process demand.Preferably, projectile is boron ion, phosphonium ion or ar atmo, bombardment
Time is 10s~60s.The ion beam of the energy of 150kV~200kV can penetrate the substrate 10 of above-mentioned preferred 200nm thickness, from
And the doped region of source-drain area can be reached；Above-mentioned preferred projectile not only has very strong penetrability, but also destructive
It is small, so as to destroy source-drain area and 20 district's groups of trap at PN junction while, reduce the damage brought to other regions of device.
Preferably, before the ion beam bombardment the step of, localization method provided by the present application further includes to after reduction processing
The back side of chip the step of starting the cleaning processing.Above-mentioned cleaning treatment can reduce the foreign particle on the back side of chip, from
And prevent foreign particle from influencing subsequent ion beam bombardment technique.
There are many kinds of the methods of cleaning treatment, and in a preferred embodiment, the step of cleaning treatment includes：It utilizes
Ultrasonic wave carries out concussion processing to the back side of chip；Place is rinsed to the back side of concussion treated chip using deionized water
Reason；And processing is dried to the back side for rinsing treated chip using air gun.The process conditions of above-mentioned cleaning treatment can
To be set according to actual process demand.Preferably, the time for shaking processing is 60s~300s.In above-mentioned preferred implementation
In mode, the foreign particle of chip lower surface can be removed as far as possible, to avoid foreign particle as far as possible to rear
The influence of continuous technique intermediate ion beam bombardment chip back.
It completes to carry out ion beam bombardment to the back side of the chip after reduction processing, so that the step of ion beam passes through device
Later, electronics beam scanning is carried out to the front of ion beam bombardment treated chip, with the position of the failpoint in positioning chip,
Its structure is as shown in Figure 5.The surface charge of chip surface can be from device surface along the device inside being destroyed when due to scanning
Breakdown area 40 discharge, so as to avoid surface charge to fail point location influence.
There are many kinds of the methods that electronics beam scanning is carried out to the front of ion beam bombardment treated chip, it is a kind of preferably
Embodiment in, the step of carrying out electronics beam scanning to the front of ion beam bombardment treated chip includes：To chip
Front carries out lift-off processing to close to the failpoint in chip；The front of chip is scanned using the electron beam of scanning electron microscope
To obtain SEM image；And the position of the failpoint in chip is determined using the bright-dark degree in SEM image.Preferably, it scans
The accelerating potential of the electron beam of Electronic Speculum is 1~2kV.
In this step, since scanning electron microscope is determined in chip using the bright-dark degree in the SEM image scanned
The position of failpoint, and to chip front carry out electronics beam scanning when chip surface surface charge can be from device surface edge
The breakdown area 40 for the device inside being destroyed discharges.Therefore the above-mentioned mode that is preferably carried out can avoid surface charge pair
The influence of SEM image makes obtained SEM image have apparent bright-dark degree, so as to spread widely and rapidly realize mistake
The positioning of point is imitated, and then easily finds out the bright spot in SEM image (i.e. failpoint).
Meanwhile present invention also provides a kind of failure analysis methods of chip.The failure analysis method includes in chip
The position of failpoint positioned, and the step of obtaining the feature image of failpoint in chip, to the failure in chip
The method that the position of point is positioned is the above-mentioned localization method of the application.In the failure analysis method, due to in chip
The method that the position of failpoint is positioned is the above-mentioned localization method of the application, so as to by electronics beam scanning accurately
The position of failpoint is obtained, then further obtains the feature image of failpoint by scanning electron microscope, and then analyzes and obtains failpoint
The reason of failure.
The localization method of failpoint provided by the present application is further illustrated below in conjunction with embodiment.
Embodiment 1
A kind of localization method of failpoint is present embodiments provided, is included the following steps：
First, chemical mechanical grinding is carried out to the back side of chip, it is 200nm to make the thickness of substrate in chip；Then, to changing
The back side for learning the chip after mechanical lapping carries out ion beam bombardment, and ion beam voltage 150kV, projectile is boron ion, Hong
It is 10s to hit the time, so that ion beam passes through the device in chip；Finally, lift-off processing is carried out to be measured to the front of chip
Surface is scanned the front of chip followed by the electron beam that accelerating potential in scanning electron microscope is 1kV to obtain SEM figures
Picture, and determine using the bright-dark degree in SEM image the position of the failpoint in chip.
Embodiment 2
A kind of localization method of failpoint is present embodiments provided, is included the following steps：
First, chemical mechanical grinding is carried out to the back side of chip, it is 300nm to make the thickness of substrate in chip；Later, it utilizes
Ultrasonic wave carries out concussion processing to the back side of chip, and the time for shaking processing is 60s, is handled concussion followed by deionized water
The back side of chip afterwards is rinsed processing, and processing is dried to the back side for the chip that rinses that treated using air gun；
Then, ion beam bombardment, ion beam voltage 200kV are carried out to the back side of the chip after chemical mechanical grinding, projectile is
Phosphonium ion, bombardment time 60s, so that ion beam passes through the device in chip；Finally, the front of chip is carried out at stripping
Reason to surface to be measured, followed by the electron beam that accelerating potential in scanning electron microscope is 1.5kV to the front of chip be scanned with
SEM image is obtained, and determines the position of the failpoint in chip using the bright-dark degree in SEM image.
Embodiment 3
A kind of localization method of failpoint is present embodiments provided, is included the following steps：
First, chemical mechanical grinding is carried out to the back side of chip, it is 310nm to make the thickness of substrate in chip；Later, it utilizes
Ultrasonic wave carries out concussion processing to the back side of chip, shake processing time be 300s, followed by deionized water to concussion at
The back side of chip after reason is rinsed processing, and place is dried to the back side for the chip that rinses that treated using air gun
Reason；Then, ion beam bombardment, ion beam voltage 210kV, projectile are carried out to the back side of the chip after chemical mechanical grinding
For ar atmo, bombardment time 65s, so that device of the ion beam in chip；Finally, the front of chip is removed
Processing to surface to be measured, followed by the electron beam that accelerating potential in scanning electron microscope is 2kV to the front of chip be scanned with
SEM image is obtained, and determines the position of the failpoint in chip using the bright-dark degree in SEM image.
Comparative example 1
This comparative example provides a kind of localization method of failpoint, includes the following steps：
First, lift-off processing is carried out to surface to be measured to the front of chip；Then, it is using accelerating potential in scanning electron microscope
The electron beam of 1kV is scanned to obtain SEM image the front of chip；Finally, using the bright-dark degree in SEM image come really
Determine the position of the failpoint in chip.
The SEM image obtained using scanning electron microscope in above-mentioned comparative example 1 is as shown in Fig. 2, utilize scanning in above-described embodiment 1
The SEM image that Electronic Speculum obtains is as shown in fig. 6, and recycle the feature image of failpoint that scanning electron microscope further obtains as schemed
Shown in 7.It can be seen from the figure that having multiple bright spots irregularly disperseed in the SEM image of comparative example 1, therefore can not determine
The position of surface failure point to be measured；And only there is unique irregular bright spot in the SEM image of embodiment 1, it is easy to distinguish
As the bright spot of failpoint, the region as shown in the A in Fig. 6.Further, according in the feature image of the failpoint of embodiment 1
See the specific pattern of failpoint, the region as shown in the B in Fig. 7, and then can be former to failure according to the specific pattern of failpoint
Because being analyzed.It should be noted that the SEM image obtained using scanning electron microscope in embodiment 2 and 3 is similar to Fig. 6, also only have
There is unique irregular bright spot.
It can be seen from the above description that the application the above embodiments realize following technique effect：The application is logical
It crosses and ion beam bombardment is carried out to the back side of the chip after reduction processing, hit so that ion beam passes through device and makes to generate in device
Region is worn, to which when being scanned to the surface to be measured of chip using electron beam, the surface charge that surface to be measured generates can
It is released from device surface along breakdown area, reduces influence of the surface charge to device surface potential, and then being capable of essence
Really obtain the position of failpoint in device.
The preferred embodiment that these are only the application, is not intended to limit this application, for those skilled in the art
For member, the application can have various modifications and variations.Any modification made by within the spirit and principles of this application,
Equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (11)
1. a kind of localization method of failpoint, for the position of failpoint in positioning chip, the chip include substrate (10) and
Device in the substrate, which is characterized in that the localization method includes the following steps：
Reduction processing is carried out to close to the device to the back side of the chip；
Ion beam bombardment is carried out to the back side of the chip after the reduction processing, so that ion beam passes through the device；
And
Electronics beam scanning is carried out to the front of the ion beam bombardment treated the chip, to position the mistake in the chip
Imitate the position of point.
2. localization method according to claim 1, which is characterized in that carry out the reduction processing to the back side of the chip
Later, the thickness of the substrate is 200nm~300nm.
3. localization method according to claim 1, which is characterized in that in the ion beam bombardment the step of, ion beam
Voltage is 150kV~200kV.
4. localization method according to claim 3, which is characterized in that in the ion beam bombardment the step of, bombard grain
Son is boron ion, phosphonium ion or ar atmo, and bombardment time is 10s~60s.
5. localization method according to claim 1, which is characterized in that
The device include be located at the substrate in trap and the source-drain electrode in the trap, and the conduction type of the trap and
The conduction type of the source-drain electrode is opposite；
The ion beam bombardment the step of, the ion beam passes through the trap and enters in the source-drain electrode.
6. localization method according to claim 1, which is characterized in that carry out electronics beam scanning to the front of the chip
Step includes：
Lift-off processing is carried out to close to the failpoint in the chip to the front of the chip；
The front of the chip is scanned to obtain SEM image using the electron beam of scanning electron microscope；And
The position of the failpoint in the chip is determined using the bright-dark degree in the SEM image.
7. localization method according to claim 6, which is characterized in that the accelerating potential of the electron beam of the scanning electron microscope is
1~2kV.
8. localization method according to any one of claim 1 to 7, which is characterized in that in the step of the ion beam bombardment
Before rapid, the localization method further includes the steps that being started the cleaning processing to the back side of the chip after the reduction processing.
9. localization method according to claim 8, which is characterized in that the step of cleaning treatment includes：
Concussion processing is carried out to the back side of the chip using ultrasonic wave；
Processing is rinsed to the back side of concussion treated the chip using deionized water；And
Processing is dried to the back side for rinsing treated the chip using air gun.
10. localization method according to claim 9, which is characterized in that the time of the concussion processing is 60s~300s.
11. a kind of failure analysis method of chip includes being positioned to the position of the failpoint in the chip, and obtain
The step of feature image of failpoint in the chip, which is characterized in that the position of the failpoint in the chip is carried out
The method of positioning is the localization method described in any one of claims 1 to 10.
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| CN109342920A (en) * | 2018-09-30 | 2019-02-15 | 上海华力集成电路制造有限公司 | IC chip failure independent positioning method |
| CN109406555B (en) * | 2018-10-15 | 2021-12-07 | 上海华力微电子有限公司 | Sample layering removing method |
| DE102018218673A1 (en) * | 2018-10-31 | 2020-04-30 | Zf Friedrichshafen Ag | Sensor arrangement |
| CN110706728B (en) * | 2019-09-29 | 2021-08-31 | 长江存储科技有限责任公司 | Method and device for confirming physical position of failure address in chip storage area |
| CN111370347A (en) * | 2020-03-24 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Failure analysis method of power device |
| CN113075522A (en) * | 2021-03-22 | 2021-07-06 | 苏试宜特(上海)检测技术有限公司 | GaAs chip failure analysis sample and preparation method thereof |
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