CN113075522A - GaAs chip failure analysis sample and preparation method thereof - Google Patents
GaAs chip failure analysis sample and preparation method thereof Download PDFInfo
- Publication number
- CN113075522A CN113075522A CN202110303325.7A CN202110303325A CN113075522A CN 113075522 A CN113075522 A CN 113075522A CN 202110303325 A CN202110303325 A CN 202110303325A CN 113075522 A CN113075522 A CN 113075522A
- Authority
- CN
- China
- Prior art keywords
- gaas chip
- analysis sample
- failure analysis
- failure
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 105
- 238000002360 preparation method Methods 0.000 title abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000005520 cutting process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000013078 crystal Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005464 sample preparation method Methods 0.000 claims description 12
- 238000010884 ion-beam technique Methods 0.000 claims description 6
- 238000012790 confirmation Methods 0.000 claims description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 73
- 238000005498 polishing Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000002474 experimental method Methods 0.000 description 4
- 235000001892 vitamin D2 Nutrition 0.000 description 3
- 230000032683 aging Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000010420 art technique Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
Abstract
The invention relates to a GaAs chip failure analysis sample and a preparation method thereof, wherein the preparation method comprises the following steps: grinding a substrate of the GaAs chip to enable the GaAs chip to be exposed out of a crystal back; carrying out hot spot positioning on the GaAs chip exposed out of the wafer back, and confirming a failure position; physically thinning the crystal back of the GaAs chip to enable the thinned thickness to meet the cutting operation thickness; scanning the thinned GaAs chip by using an infrared microscope and confirming the failure position again; and cutting the thinned GaAs chip according to the failure position to form a failure analysis sample. The method of the invention cancels the traditional chemical method for unsealing the plastic package body, avoids the damage to the metal wiring of the GaAs chip, improves the success rate of sample preparation and ensures the subsequent failure analysis effect.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a GaAs chip failure analysis sample and a preparation method thereof.
Background
Since the material of the GaAs (gallium arsenide) chip is easy to react with the chemical reagent, the preparation method of the GaAs chip failure analysis sample is limited, and usually, a chemical Decap method is used only when the plastic package is decapsulated, but care should be taken to avoid damaging the metal trace of the GaAs chip as much as possible. For the GaAs chip after HAST (accelerated aging) experiment, the metal wiring on the chip surface is affected due to the influence of HAST experiment conditions, and when the plastic package body is unsealed by using a chemical Decap method, the metal wiring on the chip surface is more easily damaged, which affects the subsequent failure analysis effect, or even fails to complete the preparation of the sample.
Disclosure of Invention
In order to solve the problems, the invention provides a GaAs chip failure analysis sample and a preparation method thereof, and the preparation method cancels the traditional chemical method for unsealing a plastic package body, avoids the damage to metal wiring of a GaAs chip, improves the success rate of sample preparation and ensures the subsequent failure analysis effect.
The invention is realized by the following scheme: a GaAs chip failure analysis sample preparation method comprises the following steps:
grinding a substrate of the GaAs chip to enable the GaAs chip to be exposed out of a crystal back;
carrying out hot spot positioning on the GaAs chip exposed out of the wafer back, and confirming a failure position;
physically thinning the crystal back of the GaAs chip to enable the thinned thickness to meet the cutting operation thickness;
scanning the thinned GaAs chip by using an infrared microscope and confirming the failure position again;
and cutting the thinned GaAs chip according to the failure position to form a failure analysis sample.
The invention changes the conventional mode of front deblocking, takes the back as the reference, and carries out the sample preparation before the hot spot positioning by removing the substrate by a grinding method, thereby canceling the traditional chemical deblocking plastic package body and avoiding the damage to the metal wiring of the GaAs chip caused by deblocking. Through carrying out the mode of attenuate to the back of the body of crystal after the hot spot location, when having satisfied cutting operation thickness, the secondary of being convenient for confirms the failure position, and more importantly has effectively guaranteed that the metal is walked the line and has not destroyed, has promoted the system appearance success rate and has guaranteed follow-up failure analysis effect.
The GaAs chip failure analysis sample preparation method is further improved in that the cutting operation thickness is not more than 30 microns.
The preparation method of the GaAs chip failure analysis sample is further improved in that a grinding disc is adopted to physically thin the crystal back of the GaAs chip.
The GaAs chip failure analysis sample preparation method is further improved in that when the crystal back of the GaAs chip is physically thinned, the area outside the failure position is ground with higher strength, the failure position is ground with lower strength, and the grinding is stopped when the metal wiring is exposed in the area outside the failure position.
The preparation method of the GaAs chip failure analysis sample is further improved in that the GaAs chip is electrically confirmed, and when the GaAs chip is confirmed to have an electrical fault, the substrate of the GaAs chip is ground.
The GaAs chip failure analysis sample preparation method is further improved in that proper hot spot positioning equipment is selected for hot spot positioning according to the electrical property confirmation condition.
The preparation method of the GaAs chip failure analysis sample is further improved in that OBIRCH/InGaAs EMMI/Thermal EMMI equipment is used for carrying out hot spot positioning, an infrared microscope on the OBIRCH equipment is used for scanning the thinned GaAs chip, and the failure position is confirmed again.
The preparation method of the GaAs chip failure analysis sample is further improved in that the thinned GaAs chip is cut by adopting a double-beam type focused ion beam to form the failure analysis sample.
The invention also provides a GaAs chip failure analysis sample which is prepared by the preparation method of the GaAs chip failure analysis sample.
Drawings
FIG. 1 shows a flow chart of a GaAs chip failure analysis sample preparation method in a conventional manner and in a comparative manner.
Fig. 2 shows a diagram of the state of the GaAs die before and after the plastic encapsulant is unsealed by conventional chemical methods.
FIG. 3 shows a diagram of the state of the GaAs chip after and after being changed when the substrate is removed by grinding.
FIG. 4 is a diagram showing the front-back variation state of a GaAs chip when the back of the crystal is physically thinned.
Detailed Description
Referring to fig. 1 and 2, fig. 1 is a flow chart showing a comparison of the preparation method of a GaAs chip failure analysis sample according to the conventional method and the GaAs chip failure analysis sample according to the present invention, and fig. 2 is a diagram showing the state of the GaAs chip before and after the plastic package is unsealed by the conventional chemical method.
The GaAs chip mainly includes a substrate 1 (usually a PCB substrate) at the bottom, a wafer 2 fixed on the substrate 1, and a plastic package 3 packaged on the top and around the wafer 2. Since the wafer 2 of GaAs chips is very thin, and the thickness is usually only about 200 μm, the conventional method for preparing a GaAs chip failure analysis sample usually uses a chemical method to unseal the plastic package, and performs hot spot positioning and dicing inspection on the front surface of the wafer 2, specifically, as shown in flow 1 in fig. 1, including the steps of:
And 2, carrying out hot spot positioning on the deblocked GaAs chip 2 and confirming a failure position.
And 3, carrying out slice inspection according to the failure position.
In the method, the phenomenon that the metal wiring is damaged easily occurs when the step 1 is performed, and particularly for the GaAs chip after HAST (accelerated aging) experiment, the metal wiring on the surface of the chip is influenced due to the influence of HAST experiment conditions, so that when the plastic package body is unsealed by using a chemical method Decap, the metal wiring on the surface of the chip is easily damaged, the subsequent failure analysis effect is influenced, and even the preparation of a sample cannot be completed.
In order to solve the problems, the invention provides a preparation method of a GaAs chip failure analysis sample and the GaAs chip failure analysis sample prepared by the preparation method.
The preparation method of the GaAs chip failure analysis sample is further described below with reference to the accompanying drawings.
Referring to fig. 1, 3 and 4, fig. 3 shows a front-back change state diagram of a GaAs chip when a substrate is removed by grinding, and fig. 4 shows a front-back change state diagram of a GaAs chip when a back-side is physically thinned.
A GaAs chip failure analysis sample preparation method comprises the following steps:
And 2, carrying out hot spot positioning on the chip 2 with the exposed wafer back to find out a failure position.
Specifically, a hotspot locating mode on the back side is selected by hotspot locating equipment to locate hotspots, and the failure position is excited by power-on.
And 3, physically thinning the crystal back of the chip 2 to ensure that the thinned thickness meets the slicing operation thickness.
Specifically, since the thickness of the back of the crystal (i.e., the GaAs substrate layer 22 on the back of the wafer 2 in fig. 4) of the GaAs chip is about 200 μm, and the thickness is thicker than the thickness of the slicing operation device, if the slicing operation is performed from the back, the back of the crystal cannot be cut to the metal routing layer 21 on the front of the wafer 2, and the purpose of analyzing the failure position cannot be achieved, therefore, the back of the crystal in step 3 is thinned, so that the thinned thickness meets the slicing operation thickness, and the requirement of the cutting depth is met. By physically thinning the wafer back, the metal routing layer 21 on the front side of the wafer 2 is effectively protected, and the electrical damage to the failure position is avoided.
And 4, scanning the thinned GaAs chip 2 by using an infrared microscope and confirming the failure position again.
Specifically, since the metal wiring layer 21 on the front surface of the wafer 2 cannot be directly observed from the back side (i.e., the GaAs substrate layer 22 on which the wafer 2 is exposed), it is necessary to scan the image of the metal wiring layer 21 again by using an infrared microscope after thinning, and at the same time, to locate the failure position again and mark the cutting operation position by using the infrared microscope.
And 5, cutting the thinned GaAs chip 2 according to the failure position to form a failure analysis sample.
Specifically, in this embodiment, a DBI-FIB dual-beam focused ion beam is used to cut the thinned GaAs chip and form a failure analysis sample, and for the case where the cutting operation position is marked, the DBI-FIB dual-beam focused ion beam cuts according to the mark. The cutting operation position needs to meet the cutting depth requirement of the DBI-FIB dual-beam type focused ion beam.
The invention changes the conventional mode of front deblocking, takes the back as the reference, and carries out the sample preparation before the hot spot positioning by removing the substrate by a grinding method, thereby canceling the traditional chemical deblocking plastic package body and avoiding the damage to the metal wiring of the GaAs chip caused by deblocking. Through carrying out the mode of attenuate to the back of the body of crystal after the hot spot location, when having satisfied cutting operation thickness, the secondary of being convenient for confirms the failure position, and more importantly has effectively guaranteed that the metal is walked the line and has not destroyed, has promoted the system appearance success rate and has guaranteed follow-up failure analysis effect.
As a preferred embodiment, the thickness of the cutting operation is preferably not more than 30 μm, depending on the cutting depth requirements of the conventional cutting operation equipment (e.g., DB-FIB dual-beam focused ion beam, etc.).
As a preferred implementation mode, the back of the GaAs chip is physically thinned by using a grinding disc. Carry out the physics attenuate through the artifical grinding form with the help of the grinding disk, be favorable to controlling the attenuate thickness, be applicable to and attenuate thinner back of a crystal.
In a preferred embodiment, when the back side of the GaAs chip is physically thinned, the region other than the failure position is polished with a higher strength, the failure position is polished with a lower strength, and the polishing is stopped when the metal trace is exposed in the region other than the failure position.
Specifically, the present embodiment controls the polishing intensity of the regions other than the failure position and the failure position by manually controlling the stay position and the stay time of the regions other than the failure position and the failure position on the polishing disk. Specifically, since the polishing disc has a characteristic that the polishing strength at the edge is slightly greater than the polishing strength at the middle, the polishing strength of the region outside the failure position can be controlled to be greater than the polishing strength at the failure position by staying the region outside the failure position at the edge of the polishing disc for a relatively long time, so as to ensure that the metal trace is not exposed at the failure position when the region outside the failure position is polished to expose the metal trace. Of course, other prior art techniques may be used to control the magnitude of the grinding intensity.
The back of the wafer is thinned through the grinding mode, the difficulty that the thinning thickness of the back of the wafer is difficult to control due to the fact that the thickness of the wafer 2 is thin is overcome, and the electrical property of a failure position is not damaged while the thinned thickness meets the slicing operation thickness.
In a preferred embodiment, the GaAs chip is electrically verified, and when the GaAs chip is verified to have an electrical failure, the substrate of the GaAs chip is polished.
Specifically, the electrical confirmation can generally determine whether the metal trace of the GaAs chip has a fault, that is, determine whether the GaAs chip has an electrical fault, and if so, prepare a failure analysis sample, thereby avoiding useless work.
As a preferred embodiment, a suitable hotspot locating device is selected for the hotspot locating according to the electrical confirmation.
In particular, the hotspot locating device may be an OBIRCH device, an InGaAs EMMI device, a Thermal EMMI device, or the like.
As a preferred embodiment, the present embodiment preferably scans the thinned GaAs chip with an OBIRCH device to confirm the failure location again, because the OBIRCH device has a higher precision infrared microscope function than other positioning devices.
The invention also provides a GaAs chip failure analysis sample which is prepared by the preparation method of the GaAs chip failure analysis sample. The GaAs chip failure analysis sample keeps the electrical property of the GaAs chip, so that the subsequent failure analysis effect is better.
While the present invention has been described in detail and with reference to the embodiments thereof as illustrated in the accompanying drawings, it will be apparent to one skilled in the art that various changes and modifications can be made therein. Therefore, certain details of the embodiments are not to be interpreted as limiting, and the scope of the invention is to be determined by the appended claims.
Claims (9)
1. A GaAs chip failure analysis sample preparation method is characterized by comprising the following steps:
grinding a substrate of the GaAs chip to enable the GaAs chip to be exposed out of a crystal back;
carrying out hot spot positioning on the GaAs chip exposed out of the wafer back, and confirming a failure position;
physically thinning the crystal back of the GaAs chip to enable the thinned thickness to meet the cutting operation thickness;
scanning the thinned GaAs chip by using an infrared microscope and confirming the failure position again;
and cutting the thinned GaAs chip according to the failure position to form a failure analysis sample.
2. The GaAs chip failure analysis sample preparation method of claim 1, wherein the dicing thickness does not exceed 30 microns.
3. The GaAs chip failure analysis sample preparation method of claim 1, wherein a back side of the GaAs chip is physically thinned using a grinding disk.
4. The GaAs chip failure analysis sample preparation method of claim 3, wherein when a back side of the GaAs chip is physically thinned, a region other than the failure position is ground with a higher strength, the failure position is ground with a lower strength, and grinding is stopped when a metal trace is exposed in the region other than the failure position.
5. The method for preparing a GaAs chip failure analysis sample according to claim 1, wherein the GaAs chip is electrically verified, and when it is verified that the GaAs chip has an electrical failure, the substrate of the GaAs chip is ground.
6. The GaAs chip failure analysis sample preparation method of claim 5, wherein a suitable hotspot locating device is selected for hotspot locating based on the electrical confirmation.
7. The GaAs chip failure analysis sample preparation method of claim 1, wherein the hot spot location is performed using an OBIRCH/InGaAs EMMI/ThermalEMMI device, the thinned GaAs chip is scanned using an infrared microscope on the OBIRCH device and the failure location is confirmed again.
8. The method for preparing a GaAs chip failure analysis sample according to claim 1, wherein the thinned GaAs chip is cut by a dual-beam type focused ion beam to form a failure analysis sample.
9. A GaAs chip failure analysis sample prepared by the method for preparing the GaAs chip failure analysis sample according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110303325.7A CN113075522A (en) | 2021-03-22 | 2021-03-22 | GaAs chip failure analysis sample and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110303325.7A CN113075522A (en) | 2021-03-22 | 2021-03-22 | GaAs chip failure analysis sample and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113075522A true CN113075522A (en) | 2021-07-06 |
Family
ID=76613965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110303325.7A Pending CN113075522A (en) | 2021-03-22 | 2021-03-22 | GaAs chip failure analysis sample and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113075522A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114252319A (en) * | 2022-03-01 | 2022-03-29 | 江山季丰电子科技有限公司 | Fault analysis method of semiconductor laser, preparation method of sample and system |
| CN114441598A (en) * | 2022-04-11 | 2022-05-06 | 胜科纳米(苏州)股份有限公司 | 3D stacked and packaged integrated circuit chip and failure positioning method and device thereof |
| CN114486926A (en) * | 2021-12-30 | 2022-05-13 | 深圳瑞波光电子有限公司 | Semiconductor laser chip failure analysis method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103278357A (en) * | 2013-04-28 | 2013-09-04 | 上海华力微电子有限公司 | Preparation method of fixed-point planar-view TEM sample |
| CN103913358A (en) * | 2014-04-10 | 2014-07-09 | 武汉新芯集成电路制造有限公司 | Preparation method and failure analysis method for transmission electron microscope (TEM) sample |
| CN103969569A (en) * | 2013-01-25 | 2014-08-06 | 上海华虹宏力半导体制造有限公司 | Preparation method and analytical method for back optical failure positioning sample of integrated circuit |
| CN105206546A (en) * | 2015-09-10 | 2015-12-30 | 宜特(上海)检测技术有限公司 | Flip chip failure analysis method and preparation method of detection sample in electric property positioning |
| CN105301475A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | Packaging chip back surface failure point locating method |
| CN105842264A (en) * | 2015-01-15 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Failure point positioning method and chip failure analysis method |
| CN107894359A (en) * | 2017-12-13 | 2018-04-10 | 武汉电信器件有限公司 | Chip of laser failure positioning analysis sample preparation methods and middleware |
-
2021
- 2021-03-22 CN CN202110303325.7A patent/CN113075522A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103969569A (en) * | 2013-01-25 | 2014-08-06 | 上海华虹宏力半导体制造有限公司 | Preparation method and analytical method for back optical failure positioning sample of integrated circuit |
| CN103278357A (en) * | 2013-04-28 | 2013-09-04 | 上海华力微电子有限公司 | Preparation method of fixed-point planar-view TEM sample |
| CN103913358A (en) * | 2014-04-10 | 2014-07-09 | 武汉新芯集成电路制造有限公司 | Preparation method and failure analysis method for transmission electron microscope (TEM) sample |
| CN105842264A (en) * | 2015-01-15 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Failure point positioning method and chip failure analysis method |
| CN105206546A (en) * | 2015-09-10 | 2015-12-30 | 宜特(上海)检测技术有限公司 | Flip chip failure analysis method and preparation method of detection sample in electric property positioning |
| CN105301475A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | Packaging chip back surface failure point locating method |
| CN107894359A (en) * | 2017-12-13 | 2018-04-10 | 武汉电信器件有限公司 | Chip of laser failure positioning analysis sample preparation methods and middleware |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114486926A (en) * | 2021-12-30 | 2022-05-13 | 深圳瑞波光电子有限公司 | Semiconductor laser chip failure analysis method |
| CN114486926B (en) * | 2021-12-30 | 2024-03-26 | 深圳瑞波光电子有限公司 | Failure analysis method for semiconductor laser chip |
| CN114252319A (en) * | 2022-03-01 | 2022-03-29 | 江山季丰电子科技有限公司 | Fault analysis method of semiconductor laser, preparation method of sample and system |
| CN114441598A (en) * | 2022-04-11 | 2022-05-06 | 胜科纳米(苏州)股份有限公司 | 3D stacked and packaged integrated circuit chip and failure positioning method and device thereof |
| CN114441598B (en) * | 2022-04-11 | 2022-07-08 | 胜科纳米(苏州)股份有限公司 | 3D stacked and packaged integrated circuit chip and failure positioning method and device thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113075522A (en) | GaAs chip failure analysis sample and preparation method thereof | |
| KR101914146B1 (en) | Chip manufacturing method | |
| US7554211B2 (en) | Semiconductor wafer and manufacturing process for semiconductor device | |
| JP3530158B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20060220183A1 (en) | Semiconductor wafer having multiple semiconductor elements and method for dicing the same | |
| KR102399929B1 (en) | Die bonder | |
| CN108630601B (en) | Method for manufacturing semiconductor device | |
| KR20130111994A (en) | Forming method of chip with die attach film | |
| CN110323182A (en) | The processing method of plate object | |
| US20180015569A1 (en) | Chip and method of manufacturing chips | |
| US8415233B2 (en) | Wafer processing | |
| CN105551945B (en) | Reduce the method for interfacial stress in wafer bonding technique | |
| KR20040086869A (en) | Wafer dicing method for making the semiconductor chip having various shape | |
| US10748801B2 (en) | Carrier arrangement and method for processing a carrier by generating a crack structure | |
| US20180351324A1 (en) | Method of producing an optoelectronic component | |
| KR20220144780A (en) | Method of processing a substrate and system for processing a substrate | |
| TW202018792A (en) | Method and apparatus for dividing substrate having devices formed thereon into individual chips | |
| KR20110017728A (en) | Method for wafer sawing preventing a bond pad oxidation | |
| JP2021182622A (en) | Method of producing substrate and system for producing substrate | |
| CN111128879A (en) | Wafer and cutting method thereof | |
| CN111430304A (en) | Plasma die dicing system and related method | |
| JP2007207871A (en) | Semiconductor wafer equipped witt plural semiconductor devices | |
| TW200902209A (en) | Laser processing method | |
| CN115871116A (en) | Dicing of silicon carbide semiconductor wafers | |
| US20240079242A1 (en) | Semiconductor apparatus and manufacturing method of semiconductor apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: Room C101, building 8, 1618 Yishan Road, Minhang District, Shanghai 201100 Applicant after: Su shiyite (Shanghai) Testing Technology Co.,Ltd. Address before: 201103 room C101, building 8, 1618 Yishan Road, Minhang District, Shanghai Applicant before: Suzhou Yite (Shanghai) Testing Technology Co.,Ltd. |