CN105826383A - 具有空腔的半导体器件 - Google Patents

具有空腔的半导体器件 Download PDF

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Publication number
CN105826383A
CN105826383A CN201511036214.5A CN201511036214A CN105826383A CN 105826383 A CN105826383 A CN 105826383A CN 201511036214 A CN201511036214 A CN 201511036214A CN 105826383 A CN105826383 A CN 105826383A
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Prior art keywords
cavity
wafer
semiconductor element
region
semiconductor
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CN201511036214.5A
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P·M·谢伊
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Great Wall Semiconductor Corp
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Great Wall Semiconductor Corp
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Abstract

本申请公开了一种具有空腔的半导体器件。半导体器件包括第一半导体晶片，该第一半导体晶片包括形成在第一半导体管芯中的空腔。第二半导体管芯在该空腔之上被键合到第一半导体管芯。第一晶体管包括形成在空腔之上的该第一晶体管的一部分。

Description

具有空腔的半导体器件
本国优先权
本申请要求2014年12月17日提交的美国临时申请号62/092,903的权益，该申请通过引用结合于此。
背景技术
半导体器件通常存在于现代电子产品中。半导体器件在电气部件的数量和密度上变化。分立的半导体器件通常包含一种类型的电气部件，例如，发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器，以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件典型地包含数百至数百万的电气部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。
半导体器件执行大范围的功能，诸如信号处理、高速运算、发射和接收电磁信号、控制电子器件、将太阳光转换为电、以及为电视显示器创建视觉投射。半导体器件存在于娱乐、通信、功率变换、网络、计算机、以及消耗品领域中。半导体器件还存在于军事应用、航空、汽车、工业控制器、以及办公设备中。尤其，功率MOSFET常用于电子电路(诸如通信系统和电源)中，作为用于启用及禁用在例如直流到直流电压转换器、电源和电机控制器中的相对较大电流的传导的电开关。
功率MOSFET器件包括并联连接且横跨半导体管芯(die)的表面上分布的大量的MOSFET单元或者独立晶体管。功率MOSFET器件典型地用作用于控制到电路的功率流的电子开关。在功率MOSFET的栅极处的控制信号控制电流是否在MOSFET的漏极端子和源极端子之间流过MOSFET。MOSFET的漏极端子和源极端子之间的传导路径与待开关的电路串联连线，使得当MOSFET截止时，即，该MOSFET限制源极端子和漏极端子之间的电流，电流被限制通过开关电路。当MOSFET开启时，电流串联流过MOSFET和开关电路，以给该开关电路供电。
功率MOSFET的一个规范是MOSFET的寄生电容。寄生电容是由于导电元件彼此接近而存在于电子部件或器件的导电部分之间的电容。寄生电容通常在MOSFET的栅极和源极之间、栅极和漏极之间、以及漏极和源极之间存在于功率MOSFET中。当功率MOSFET以较高频率操作时，寄生电容变成更显著的因素。
发明内容
相应地，在一个实施例中，本发明是一种制作半导体器件的方法，该方法包括：提供第一半导体晶片；在第一半导体晶片中形成空腔(cavity)；在该空腔之上将第二半导体晶片键合(bond)到该第一半导体晶片；以及形成晶体管，该晶体管包括在该空腔之上的该晶体管的一部分。
在另一个实施例中，本发明是一种制作半导体器件的方法，该方法包括：提供第一半导体管芯；在该第一半导体管芯中形成空腔；在该空腔之上将第二半导体管芯键合到该第一半导体管芯；以及形成晶体管，该晶体管包括形成在该空腔之上的该晶体管的栅极。
在另一个实施例中，本发明是一种半导体器件，该半导体器件包括第一半导体管芯，该第一半导体管芯包括形成在该第一半导体管芯中的空腔。第二半导体管芯在该空腔之上被键合至该第一半导体管芯。第一晶体管包括形成在该空腔之上的该第一晶体管的一部分。
附图说明
图1a-1c示出了空腔晶片的形成；
图2a-2c示出了替代实施例中的空腔晶片的形成；
图3a-3c示出了另一替代实施例中的空腔晶片的形成；
图4a-4c示出了第三替代实施例中的空腔晶片的形成；
图5a-5c示出了器件晶片的掺杂以及掺杂区域到空腔的对准；
图6示出了包括空腔晶片的完成的准横向功率MOSFET；
图7a-7c示出了形成具有空腔晶片的横向MOSFET；
图8a-8d示出了形成具有空腔晶片的垂直沟槽MOSFET；以及
图9a-9d示出了形成具有空腔晶片的垂直平面栅MOSFET。
具体实施方式
在下文中的一个或多个实施例中参照附图描述本发明，其中同样的数字符号代表相同或相似的元件。虽然依据用于实现本发明的目标的最佳模式描述本发明，但本领域技术人员将理解本公布旨在覆盖如可被包括在本发明的精神和范围内的替代、变型、以及等价物，本发明的精神和范围由如由下面公开和附图所支持的所附权利要求和权利要求等价物限定。
通常使用两个复合制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上的多个管芯的形成。晶片上的每个管芯包含有源电气部件和无源电气部件，这些有源电气部件和无源电气部件电连接以形成功能电子电路。有源电气部件(诸如晶体管和二极管)具有控制电流的流动的能力。无源电气部件(诸如电容器、电感器、和电阻)创建执行电路功能必需的电压和电流之间的关系。
通过一系列工艺步骤(包括掺杂、沉积、光刻、蚀刻、以及平面化)在半导体晶片的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散之类的技术将杂质引入到半导体材料中。掺杂工艺通过动态地改变响应于电场或基极电流的半导体材料传导性来修改有源器件中的半导体材料的导电性。晶体管包含使晶体管能够促进或限制在施加电场或基极电流时的电流流动所必需的配置的变化的掺杂类型和程度的区域。
半导体晶片的区域可以是负掺杂的或者正掺杂的。负掺杂或N掺杂区域利用诸如磷、锑、或砷之类的负掺杂剂或N型掺杂剂掺杂。N型掺杂剂的每个分子向半导体晶片贡献附加的负电荷载流子，即，电子。正掺杂或P掺杂区域利用诸如硼、铝或镓之类的正掺杂剂或P型掺杂剂掺杂。P型掺杂剂的每个分子向半导体晶片贡献附加的正电荷载流子，即，电子空穴。一种掺杂类型的区域通过添加超过现有掺杂浓度的第二种类型的掺杂剂可被制成其它掺杂类型的区域。N型和P型区域被相反地掺杂。
通过具有不同电性质的材料层形成有源和无源部件。通过部分地由正被沉积的材料的类型确定的各种沉积技术来形成这些层。例如，薄膜沉积可包括化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀、以及化学镀工艺。通常图案化每层以形成有源部件、无源部件或者部件之间的电连接的各部分。
后端制造涉及将完成的晶片切割或单一化成单独的半导体管芯以及封装半导体管芯以用于结构支撑、电互连和环境隔离。为了单一化半导体管芯，沿着被称为锯道(sawstreet)或划片线的晶片的非功能区域刻痕和折断晶片。使用激光切割工具或锯条单一化晶片。在单一化后，单独的半导体管芯被安装到包括用于与其它系统部件互连的引脚或接触垫的封装衬底。半导体管芯上形成的接触垫随后被连接到该封装内的接触垫。可利用导电层、凸块、纽扣凸块、导电胶、或接合线进行电连接。密封剂或其他模制材料被沉积在封装上以提供物理支撑和电隔离。完成的封装随后被插入到电系统中并且半导体器件的功能被集成到该系统中。
图1a示出了操作晶片(handlewafer)10的一部分的截面图。操作晶片10是由基础衬底材料(诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅、或其它体半导体材料)形成的半导体晶片。在一个实施例中，操作晶片10具有200-300毫米(mm)的宽度或直径。在另一个实施例中，操作晶片10具有100-450mm的宽度或直径。
操作晶片10被掺杂有N型掺杂剂(诸如磷、锑、或者砷)，以形成N+掺杂衬底。N+掺杂指示操作晶片10中相对强的浓度的N型掺杂剂。在生长从中切割操作晶片10的半导体晶锭(boule)时添加掺杂剂以提供贯穿晶片的大致均匀的初始掺杂。在其他实施例中，使用扩散、离子注入、或其他合适的工艺将操作晶片10掺杂至N+衬底。操作晶片10变为随后形成的MOSFET的漏极接触。操作晶片10是负掺杂的，因为操作晶片10被耦合到N沟道MOSFET器件的漏极。如果正形成P沟道器件，则操作晶片10被掺杂有P型掺杂剂。在一个实施例中，操作晶片10被设置于临时或牺牲载体之上以供处理。
通过使用掩膜16的蚀刻工艺移除操作晶片10的一部分以形成空腔20，掩膜16在某些实施例中是光刻胶层。掩膜16在蚀刻工艺移除未被掩膜16覆盖的晶片的材料时保护操作晶片10的部分。各种湿法和干法蚀刻技术可用于形成空腔20。在一个实施例中，反应离子蚀刻被用于形成空腔20。随着蚀刻工艺移除掩膜16的占位外的操作晶片10的基础衬底材料，形成空腔20。
空腔20包括侧壁22。侧壁22被示为远离空腔20倾斜的，但在其他实施例中，包括不同于线性的其他斜率和形状。斜率和形状部分地由所使用的特定蚀刻方法的各向同性所确定。在各种实施例中，侧壁22倾斜到空腔20中、倾斜至空腔20外，或者垂直于操作晶片10的表面。在其他实施例中，侧壁22是线性的、圆形的，或包括其他形状。
空腔20被成形为延伸进入和离开图1b的条纹(stripe)。空腔20在垂直于图1b的页面的方向上在操作晶片10上延伸，因为最终形成的MOSFET被形成为操作晶片10上的条纹。然而，在其他实施例中，当以其他形状和图案形成MOSFET时，空腔20根据需要被成形以提供在后续形成的MOSFET的栅极下延伸的空腔20。在一个实施例中，空腔20被形成断裂成操作晶片10或器件晶片30上的分立的线段，而不是不中断的条纹。在一些实施例中，空腔20进入操作晶片10的深度在1和10微米(μm)之间并且空腔20的宽度大约是后续形成的漂移区的长度的两倍。由于漂移长度随击穿电压(BVdss)缩放，因而600伏特的BVdss导致空腔20的宽度在大约60μm和100μm之间。较低电压器件可利用较薄和较浅的空腔20。
在空腔20的蚀刻完成之后，使用化学机械抛光(CMP)、机械平面化或其他合适的方法清洁操作晶片10以移除掩膜16的剩余部分。清洁工艺的结果是如图1b中所示的N+掺杂且包括空腔20的操作晶片10。
在于操作晶片10中形成空腔20且抛光操作晶片10之后，器件晶片30被设置于操作晶片10之上。器件晶片30是半导体材料的未掺杂或轻掺杂的晶片。使用直接晶片至晶片键合(bonding)将器件晶片30键合到操作晶片10。在升高的温度下使操作晶片10和器件晶片30退火，使得半导体原子的晶格结构结合。在操作晶片10和器件晶片30由Si形成的情况中，在操作晶片10和器件晶片30的相对表面之间建立共价Si-Si键。
键合到器件晶片30的操作晶片10与操作晶片10和器件晶片30之间的空腔20构成空腔晶片32。在一个实施例中，将器件晶片30提供为具有与操作晶片10基本上相同的直径和厚度的晶片。在键合后使用背面研磨或抛光工艺薄化器件晶片30以减少器件晶片30的厚度。器件晶片30的厚度被减少至期望的厚度以用于形成MOSFET的各种掺杂区域。
图2a-2c示出了形成空腔晶片34的替代实施例。在操作晶片10上生长外延层12。外延层12包括具有比操作晶片10中低的掺杂剂浓度的N型掺杂。通过在外延层12的形成期间添加杂质来掺杂外延层12。掩膜16被用于在外延层12中形成空腔20，如图2b中所示。
移除掩膜16的剩余部分，留下作为横跨操作晶片10的条纹垂直于页面延伸的空腔20。外延层12的部分保持在空腔20周围。在某些实施例中，外延层12的一部分保持在空腔20的底部。在其他实施例中，空腔20延伸到操作晶片10中。在图2c中，器件晶片30在操作晶片10和空腔20之上被键合到外延层12以形成空腔晶片34。在某些实施例中，在器件晶片30被键合到外延层12之后，器件晶片30被薄化至期望的厚度。图2c中的空腔晶片34类似于图1c中的空腔晶片32，除了空腔晶片34包括外延层12。外延层12提供操作晶片10和器件晶片30之间相对轻掺杂的区域。
外延层12的使用增加了操作晶片10和器件晶片30之间的键合工艺的热预算。在键合期间，所使用的热量使掺杂剂从操作晶片10扩散并进入器件晶片30中。外延层12创建操作晶片10和器件晶片30之间的分离以减少退火工艺期间被转移到器件晶片30中的掺杂剂的量。
图3a-3c示出了形成空腔晶片36的第三实施例。在图3a中，在器件晶片30上生长外延层12。使用掩膜16将空腔20蚀刻到外延层12中，其中外延层12在器件晶片30上。在于外延层12中形成空腔20之后，移除掩膜16的剩余部分。图3b示出了在移除掩膜16的剩余部分之后包括空腔20的器件晶片30和外延层12。
在图3c中，在某些实施例中操作晶片10被提供在临时载体上作为衬底。器件晶片30和外延层12被翻转并被置于操作晶片10之上。执行热退火以将外延层12键合到操作晶片10。器件晶片30经由外延层12被键合到操作晶片10连同设置在操作晶片10和器件晶片30之间的空腔20形成空腔晶片36。空腔晶片36类似于空腔晶片34，其中外延层12在操作晶片10和器件晶片30之间。然而，在器件晶片30上而不是操作晶片10上生长外延层12。由于外延层12在对面晶片上的生长，空腔20的侧壁22被示为在图2c和3c之间相反方向上倾斜，但实践中其他空腔晶片实施例可具有任意合适斜率的空腔侧壁。
在图4a-4c中所示的形成空腔晶片的第四实施例中，空腔20直接形成在器件晶片30中而没有使用外延层12。器件晶片30被设置为足够厚以适应空腔20的形成，如果需要接着是器件晶片30的薄化。在器件晶片30中的空腔20的形成之后，器件晶片30被键合到操作晶片10以形成空腔晶片38，如图4c中所示。
图5a示出了具有被掺杂以用于一个MOSFET实施例中的器件晶片30的空腔晶片32。器件晶片30包括P沟道区域50、P+体接触(bodycontact)54、N+源极区域60、N+漏极区域64、以及漂移区域70。虽然图示了N沟道MOSFET，但通过利用相反类型的掺杂剂掺杂每个区域来形成P沟道MOSFET。另外，在其他空腔晶片实施例中类似地掺杂器件晶片30以形成基于例如空腔晶片34、36、或38的MOSFET器件。
使用类似于掩膜16的相应的光刻胶掩膜来形成掺杂区域50、54、60、64、和70中的每一个。掺杂区域50、54、60、64、和70每个与空腔20平行地在空腔晶片32上延伸，例如，作为进入和离开页面的条纹，如图5b中所示。光刻胶层形成在器件晶片30的基本上整个顶表面上，并且在待掺杂的区域上蚀刻掉光刻胶层。例如，为了掺杂P+体接触54，在P+体接触54的期望的位置上形成光刻胶层中的开口。随着掺杂剂从上面被注入到器件晶片30中，掺杂剂被成功地注入到光刻胶层中的开口所位于的器件晶片30中。在光刻胶层保持的地方，掺杂剂被光刻胶层阻挡免于被大量注入到器件晶片30中。在某些实施例中，对每个掺杂区使用多个注入步骤。改变掺杂剂注入的能量导致将掺杂剂沉积到器件晶片30中的变化的深度。
在掺杂器件晶片30中的第一区域后，移除光刻胶掩膜，并施加另一光刻胶掩膜以掺杂器件晶片30的另一个区域。在某些实施例中，使用单个掩膜来掺杂在单个注入步骤中类似地掺杂的器件晶片30的每个区域。以任意适当的顺序掺杂器件晶片30的各个区域。在一个实施例中，器件晶片30被初始提供为具有最终掺杂区域中的一个的期望的掺杂浓度，并且随后不需要特定掩膜来掺杂讨论中的该区域。
以相对高的浓度掺杂P+体接触54和N+源极区域60以便提供与金属层的良好欧姆接触，该金属层随后将被形成在P+体接触54和N+源极区域60上。由P+体接触54提供的源极金属层和P沟道区域50之间的接触偏置由N+源极区域60、P沟道区域50和漂移区域70形成的寄生NPNBJT晶体管。寄生NPNBJT晶体管的偏置降低了闩锁效应(latch-up)发生的可能性。以较高浓度的掺杂剂掺杂N+源极区域60降低了接触电阻以及从漏极到源极穿过MOSFET器件的电流的整体电阻。N+源极区域60作为MOSFET的源极操作并提供良好的欧姆接触。以相对高的浓度掺杂N+漏极区域64以提供与操作晶片10的良好电接触。N+漏极区域64至少部分地形成在空腔20的占位外以接触操作晶片10，或形成在操作晶片10上的外延层12。操作晶片10用作MOSFET单元的漏极接触。
以N型掺杂剂掺杂漂移区域70。通常相对轻地掺杂漂移区域70以支持从漏极至源极的较高的击穿电压。漂移区域70和N+源极区域60两者都以负掺杂剂掺杂，而P沟道区域50以正掺杂剂形成在N+源极区域60和漂移区域70之间。由于P沟道区域50包括与漂移区域70和P+体接触54相反的多数载流子，因而通常电流不从漏极向源极流过MOSFET。随后形成在P沟道区域50上的栅极，例如，图5中的栅极74，被提供有正电荷，这产生电场，该电场将电子(即，负载流子)吸引到漂移区域70和N+源极区域60之间的P沟道区域50的区。当足够的电荷被施加到栅极，并且足够的电子聚集在N+源极区域60和漂移区域70之间时，电流经由漂移区域70、P沟道区域50和N+源极区域60从漏极流到源极。
在其它实施例中，使用其它类型的漂移区域。在一个实施例中，以线性或其他梯度掺杂漂移区域70以形成降低表面场(RESURF)漂移区域。将漂移区域70形成为RESURF漂移区域通过贯穿漂移区域70展开电场来降低漂移区域70和P沟道区域50之间的结处的电场。展开电场允许漂移区域70中的较高掺杂浓度，这降低了通过MOSFET的电流的电阻。在另一个实施例中，漂移区域70是超级结，如图5b中所示。将漂移区域70形成为超级结包括形成在漏极电压相对于源极电压增加时耗尽的电荷平衡的N条纹70a和P条纹70b。漂移区域70的N条纹70a和P条纹70b中的每个从N+漏极区域64延伸到P沟道区域50。在一个实施例中，使用两个单独的掩膜形成漂移区域70的超级结的N条纹70a和P条纹70b。
掺杂区域50、54、60、64和70相对于空腔20的对准的精度的改进提供准横向(quasi-lateral)MOSFET100的操作上的优势。图5a示出了理想的对准，其中操作晶片10和器件晶片30之间的接触的宽度是与漏极区域64精确相同的宽度并且在漏极区域64上精确对准。在实践中，操作晶片10和器件晶片30之间的接触相对于N+漏极区域64通常将是偏移的。空腔20不易于透过器件晶片30可见，因此基于掺杂剂沉积的公差和准确记起空腔20位于空腔晶片32内何处的能力，对准是有限的。图5c-5e示出了改进器件晶片30或操作晶片10的掺杂相对于空腔20的对准的方法。
在图5c中，N+漏极区域64的宽度被增加至至少相邻空腔20之间的距离和所涉及的任何对准公差的总和。利用加宽的N+漏极区域64，操作晶片10和器件晶片30之间的物理接触完全地发生在N+漏极区域64的占位内，甚至在最大的预期未对准下。漂移区域70完全地保持在空腔20的占位内。
图5d示出了设置在操作晶片10的顶表面中且在空腔20外的基准标记72。在空腔晶片32的形成期间薄化器件晶片30。在薄化后，器件晶片30透过有限量的光。允许一些光穿过器件晶片30，虽然透过器件晶片30直接观察空腔20是个挑战。基准标记72提供与操作晶片10显著的光学对比。使用可见光谱或其它频率的电磁辐射，基准标记72可透过器件晶片30看见，从而允许掺杂相对于空腔20的准确对准。在于外延层12中形成空腔20的实施例中，基准标记72被设置在外延层12内。
在图5e中，漂移区域70完全地延伸在两个相邻的P沟道区域50之间。在图5e的实施例中，较低精确的对准是可接受的，因为操作晶片10和器件晶片30之间的接触发生在漂移区域70内，即使具有大的未对准。在其中物理接触被设置在漂移区域70和围绕空腔20的区之间的一些实施例中，使用外延层12而不是操作晶片10和器件晶片30之间的直接物理接触。外延层12的较低的掺杂浓度降低了器件晶片30的表面附近的电场强度以降低雪崩击穿的可能性。
图6示出了基于空腔晶片32的完成的准横向MOSFET100。在其他实施例中使用类似的互连结构以形成基于其他空腔晶片实施例(例如，空腔晶片34、36或38)的完成的MOSFET器件。
图6中的准横向MOSFET100开始于如图5a中所示的掺杂的空腔晶片32。包括栅极74和栅介质76的栅极结构形成在P沟道区域50上且部分形成在N+源极区域60和漂移区域70上。栅极74是导电的，并且当被充电时，提供在P沟道区域50中创建载流子沟道所必需的电场，该载流子沟道电连接漂移区域70和N+源极区域60。在一个实施例中栅极74由多晶硅形成。在某些实施例中，硅化物层形成在栅极74的多晶硅上以降低电阻。栅介质76提供栅极74和器件晶片30之间的电隔离。在一个实施例中，两个栅极74完全地位于单个空腔20的占位内，即，空腔20的每一侧延伸越过栅极74的外边缘。在某些实施例中，在形成栅极74之后掺杂漂移区域70，并且栅极74被用于自对准漂移区域70。
绝缘层78被施加在器件晶片30和栅极74上。绝缘层78包含一层或多层的预浸材料、光敏低固化温度介电抗蚀剂、光敏复合抗蚀剂、液晶聚合物(LCP)、层压复合膜、含填料的绝缘胶、焊接掩膜抗蚀膜、液体模塑料、粒状模塑料、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、二氧化铪(HfO2)、二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、焊料抗蚀剂、或具有类似的绝缘和结构性质的其他材料。使用印刷、旋涂、喷涂、层压、和其它合适工艺沉积绝缘层78。
通过蚀刻或激光直接消融移除绝缘层78的一部分以形成绝缘层78中的开口并暴露P+体接触54和N+源极区域60的部分。导电层80形成在绝缘层78的开口中以电接触P+体接触54和N+源极区域60。使用PVD、CVD、电解电镀、化学镀工艺、或其他合适的金属沉积工艺利用铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)、钛(Ti)、钨(W)、或其他合适的导电材料或其组合填充穿过绝缘层78的开口，以形成导电层80。在某些实施例中，通过合适的电镀工艺在形成绝缘层78之前在空腔晶片32上形成导电层80。在某些实施例中，在绝缘层78和导电层80的形成之后执行例如使用研磨机或CMP工艺的平面化工艺。
绝缘层82形成在绝缘层78和导电层80上。绝缘层82由与绝缘层78类似的材料并以与绝缘层78类似的工艺形成。移除绝缘层82的一部分以暴露导电层80。以与导电层80类似的方式利用导电材料填充穿过绝缘层82的开口以形成导电层84。在其中导电层84在绝缘层82之前形成的实施例中，使用诸如PVD、CVD、溅射、电解电镀或化学镀之类的图案化和金属沉积工艺，并且在沉积绝缘层82之前移除导电层84的一部分。在某些实施例中平面化导电层84和绝缘层82。绝缘层86和导电层88分别类似于绝缘层78和导电层80。
导电层96形成在空腔晶片32的基本上整个宽度上作为源极接触。当最终封装准横向MOSFET100时，导电层96向准横向MOSFET100提供外部接触。导电层96的一部分97是电隔离的并且电耦合至栅极74以提供外部栅极接触。在一个实施例中，导电层96，包括部分97，从准横向MOSFET100的封装中直接暴露以被焊接到PCB或其他衬底。在其他实施例中，附加的互连结构(例如，焊料凸块、纽扣凸块、或接合线)作为封装工艺的一部分形成在导电层96上。接合线101是形成在准横向MOSFET100上用于外部互连的互连结构的一个实施例。
导电层80、84、88和96构成形成在空腔晶片32上的互连结构，并提供至准横向MOSFET100的源极端子的电连接。导电层98类似于导电层96并提供准横向MOSFET100的外部漏极接触。在某些实施例中，不使用绝缘层82和86，以及导电层84和88。导电层96直接形成在绝缘层78和导电层80中。在其他实施例中，其他数量的绝缘层和导电层形成在空腔晶片32上。使用导电层84和88来增加导电层96和操作晶片10之间的距离降低了漏极至源极电容。
具有空腔20的准横向MOSFET100在准横向MOSFET100的漏极和源极之间具有减少的寄生电容。空腔20增加了准横向MOSFET100的最大开关频率并降低了切换准横向MOSFET100所需的能量的量。另外，为真空或气体填充的，而不是固体绝缘材料的空腔20允许类似于绝缘体上硅器件的RESURF设计，同时降低热载流子和氧化物电荷俘获效应。降低热载流子效应提高了准横向MOSFET100的可靠性，因为空腔20不包括其中电荷可变得俘获的固体绝缘材料。
直接晶片至晶片键合被用于形成嵌入在空腔晶片32、34、36、或38中的空腔20。操作晶片10和器件晶片30之间的键合位于空腔20的底部或顶部处。在任一种情况中，可使用或可不使用外延层12来降低操作晶片10和器件晶片30之间的结处的掺杂浓度。通过将漏极区域扩展至包括任何对准公差、通过注入透过器件晶片30可见的高对比度基准标记、或者通过在操作晶片10与器件晶片30的接触区上充分延伸漂移区域70来在操作晶片10和器件晶片30之间提供对准。在各种实施例中，漂移区域70是超级结、绝缘体上硅(SOI)RESURF、或简单RESURF漂移区域。
准横向MOSFET100包括并联连线的多个MOSFET单元。图6示出了并联连接的两个MOSFET单元100a和100b，每个单元包括空腔20。在其他实施例中，很多2个以上的MOSFET单元并联连线以形成MOSFET器件。准横向MOSFET100与设计用于垂直功率MOSFET的标准功率MOSFET封装技术兼容，其中金属漏极接触98位于封装的底部，且金属源极接触96和金属栅极接触97位于封装的顶部。在某些实施例中，空腔晶片32上的互连结构包括提供从N+漏极区域64处的准横向MOSFET100的漏极到器件的顶表面的连接的金属层。
后续附图示出了各种其它MOSFET实施例中所使用的空腔。除了MOSFET之外，当用于其它类型的半导体器件(例如，二极管或双极结型晶体管)时，类似的空腔结构可潜在地具有优势。
图7a-7c示出了横向(lateral)空腔MOSFET200的形成。横向空腔MOSFET200是基于具有空腔120的操作晶片110。器件晶片130在空腔120之上被键合到操作晶片110以形成图7a中所示的空腔晶片132。操作晶片110类似于准横向MOSFET100的操作晶片10。然而，操作晶片110包括P+掺杂，该P+掺杂是图6中的操作晶片10的相反的掺杂。操作晶片110被耦合到器件晶片130中随后形成的源极区域，而操作晶片10被耦合到器件晶片30中的漏极区域。器件晶片130类似于器件晶片30。类似于空腔20，空腔120在不同实施例中形成在操作晶片110或器件晶片130中。在其他实施例中，空腔120形成在于操作晶片110或器件晶片130上生长的相对轻掺杂的外延层中。操作晶片110通过直接晶片至晶片键合被键合到器件晶片130。空腔120被形成为与空腔20近似相同的尺寸，并且可以是基本上完全横跨操作晶片10或器件晶片30伸展的条纹，或者形成为一系列的线段。
在图7b中，器件晶片130被掺杂有形成MOSFET单元200a和200b所必需的区域。P沟道区域150类似于P沟道区域50。P+体接触154类似于P+体接触54。N+源极区域160类似于N+源极区域60。N+漏极区域164类似于N+漏极区域64。漂移区域170类似于漂移区域70。器件晶片130的掺杂区域类似于器件晶片30的掺杂区域，除了器件晶片130的掺杂区域具有在空腔120之上居中的N+漏极区域164，而器件晶片30的P+体接触54在空腔20之上居中。操作晶片110接触P+体接触154，而操作晶片10接触N+漏极区域64。类似于漂移区域70，在各种实施例中，漂移区域170是超级结、SOIRESURF、或简单RESURF漂移区域。必要时使用多个掩模来将适当的掺杂浓度沉积到器件晶片130的各种掺杂区域中。
使用与空腔晶片32、34、36和38类似的方法对准空腔晶片132。在一个实施例中，设计P沟道区域150和P+体接触154的尺寸，使得在最大的预期未对准下操作晶片110和器件晶片130之间的接触区完全落在P沟道区域150和P+体接触154的占位内。在另一个实施例中，基准标记被设置在操作晶片110中且透过器件晶片130可见。
在图7c中，包括栅极174和栅极介质176的栅极结构形成在P沟道区域150之上。在一个实施例中，在栅极174之后且与栅极174自对准地掺杂漂移区域170。用于外部互连的互连结构形成在空腔晶片132之上。导电层180形成在N+源极区域160和P+体接触154上以创建金属源极接触。导电层181形成在N+漏极区域164上以创建金属漏极接触。在一个实施例中，导电层180和导电层181形成在绝缘层178的开口中，类似于图6中导电层80的形成。绝缘层182、186、190和194类似于绝缘层82和86。导电层184、185、188、189、192、193和195类似于导电层84和88。导电层196被形成为图7c中从左到右取向的条纹。导电层196提供到P+体接触154和N+源极区域160的外部连接。横向空腔MOSFET200包括形成为多个条纹的导电层196，每个条纹连接到P+体接触154和N+源极区域160。导电层196的条纹与通过导电层195的部分耦合到N+漏极区域164的条纹197交错。
在某些实施例中，围绕空腔120且接触器件晶片130的操作晶片110的部分被设计成提供类似于场板(fieldplates)的效应。在P沟道150附近的操作晶片110屏蔽栅极174免于横向空腔MOSFET200的源极电场的影响。通过减少栅极174处所经历的电场，在漂移区域170中较高的掺杂浓度是可能的，这降低了横向空腔MOSFET200的导通电阻。另外，从操作晶片110横跨空腔120的电场帮助耗尽漂移区域170，从而允许漂移区域170的掺杂中的进一步增加。
导电层180、184、188、192、195和196提供从横向空腔MOSFET200的P+体接触154和N+源极区域160到外部PCB或其他衬底的互连。导电层181、185、189、193、195和197提供到横向空腔MOSFET200的N+漏极区域164的外部互连。导电层197被形成为与导电层196的条纹交错的条纹，并且提供经由导电层195的部分从导电层193到横向空腔MOSFET200的顶表面的互连。在其他实施例中，任意数量的导电层和绝缘层形成在空腔晶片132之上以提供外部互连。在某些实施例中，可选的导电层198形成在操作晶片110的与空腔120相对的表面上作为源极接触。
横向空腔MOSFET200包括空腔120以降低从漏极到源极的电容。横向空腔MOSFET200与设计用于横向功率MOSFET的功率MOSFET封装技术(包括连接盘网格阵列、球栅阵列和铜柱封装)兼容。源极、漏极和栅极接触都位于横向空腔MOSFET200的顶表面上。图7c示出了并联连接的两个MOSFET单元200a和200b，但在其他实施例中并联连线任意数量的MOSFET单元。每个MOSFET单元垂直于图7c的页面延伸，并且具有被定制为特定实施例的要求的长度。
图8a-8d示出了垂直沟槽MOSFET单元300的形成。在图8a中，提供操作晶片210。空腔220形成在操作晶片210中。空腔220类似于空腔20和120，但垂直地取向而不是水平地取向。形成多个平行的空腔220，其中每个空腔包括垂直于图8a的页面延伸的垂直沟槽。形成在操作晶片210上的每个垂直沟槽MOSFET单元300包括单个空腔220。使用成角的注入在操作晶片210中毗邻于空腔220形成掺杂区域222和224，并且掺杂区域222和224形成电荷平衡超级结漂移区域。在一个实施例中，使用简单的轻掺杂漂移(LDD)区域代替电荷平衡超级结。在某些实施例中，通过在操作晶片210上相继地生长且随后掺杂一个或多个外延层来将掺杂区域222和224形成为超级结。
在一个实施例中，空腔220的宽度在一和两μm之间。空腔220的深度取决于能够支撑垂直沟槽MOSFET300的结构的区域222和224的机械约束。空腔220可被形成为横跨整个操作晶片210的长条纹，或者断裂成线段阵列。
在图8b中，器件晶片230被设置于操作晶片210和空腔220之上。使用直接晶片至晶片键合将器件晶片230键合到操作晶片210以封围空腔220。在某些实施例中，空腔220被形成在器件晶片230中或之上，并且掺杂区域222和224被形成在器件晶片30中。随后包括空腔220和掺杂区域222及224的器件晶片230被设置于操作晶片210之上并被键合至操作晶片210。
图8c示出了形成在器件晶片230中的MOSFET的功能区域。区域232连同掺杂区域222和224形成漂移区域的一部分。P沟道区域250阻挡电流通过垂直沟槽MOSFET300直到栅极274上的足够的电荷创建通过P沟道区域250的多数载流子沟道。N+源极区域260和P+体接触254分别类似于N+源极区域60和P+体接触54操作，并且提供与后续形成的导电层的良好欧姆接触。通过在空腔220之上的沟槽中沉积导电材料并与图8c的页面垂直地延伸来形成栅极274。栅介质276将栅极274与器件晶片230电隔离。
使用与空腔晶片32、34、36和38类似的方法对准垂直沟槽MOSFET300的掺杂区域。在一个实施例中，空腔220足够大到在最大的预期未对准下栅极274完全落在空腔220的占位内。在另一个实施例中，基准标记被设置于操作晶片210或掺杂区域222和224中，并且透过器件晶片230可见以用于对准。
在图8d中，金属层288和296形成在器件晶片230之上以提供到P+体接触254和N+源极区域260的外部互连。介电层286提供金属层296和栅极274之间的附加的隔离，从而降低栅极至源极电容。导电层298形成在操作晶片210之上作为外部漏极接触。
垂直沟槽MOSFET300是垂直MOSFET。相比准横向空腔MOSFET100和横向空腔MOSFET200的横向设计，由掺杂区域222、224和232形成的垂直漂移区域提供较低的特定区域(area-specific)导通电阻但较高的特定区域电容。空腔220帮助降低垂直沟槽MOSFET300的寄生电容。垂直沟槽MOSFET300被切割成包括创建具有期望特性的最终封装器件所需的任意数量的相邻空腔220以及任意必要长度的空腔220。图8d示出了单个MOSFET单元，但每个相邻的空腔220包括并联耦合的围绕空腔220的类似的MOSFET单元。
图9a-9d示出了垂直平面栅MOSFET400的形成。操作晶片310包括形成在操作晶片10上作为漂移区域的相对轻N掺杂区域312和P掺杂区域314。区域312和314形成电荷平衡超级结，并且通过相继地形成并随后掺杂一个或多个外延层中的区域来形成。
在图9b中，空腔320形成在掺杂区域312和314中。类似于空腔20地形成空腔320。使用直接晶片至晶片键合将器件晶片330设置在区域312和314之上并将其键合到区域312和314。在一个实施例中，空腔320是4和12μm之间宽且1和10μm之间深。空腔320可以是横跨基本上整个操作晶片310垂直地延伸的条纹或者断裂为线段阵列。
在图9c中，垂直平面栅MOSFET400的可操作区域被掺杂到器件晶片330中。P+体接触354和N+源极区域360分别类似于P+体接触54和N+源极区域60地形成和操作。P沟道区域350类似于P沟道区域50。N+漏极区域364类似于N+漏极区域64。
图9d示出了形成在P沟道区域350之上的栅极374和栅介质376。栅极374类似于栅极74。绝缘层378形成在栅极374之上，并且导电层380形成在绝缘层378的开口中。在一个实施例中，每个栅极374完全地位于相应的空腔320的占位内。绝缘层382和导电层384形成在绝缘层378之上。绝缘层386和导电层388形成在绝缘层382和导电层384之上。导电层396形成在导电层388和绝缘层386的基本上整个顶表面上作为源极接触。导电层396的一部分与导电层396的剩余部分电隔离并被用作到栅极374的接触。导电层396的剩余部分经由导电层380、384和388耦合到P+体接触354和N+源极区域360。导电层398形成在操作晶片310的基本上整个底表面之上作为漏极接触。垂直平面栅MOSFET400在导电层396和398的形成之后被切割和封装。图9d中示出了一个MOSFET单元，但任意数量的MOSFET单元形成在操作晶片310上并被并联耦合。
使用与空腔晶片32-38类似的方法将器件晶片330的掺杂对准至空腔320。设计栅极374的尺寸并定位栅极374使得即使在最高的预期未对准下，栅极374仍在空腔320之上。在另一个实施例中，基准标记被设置于区域312和314中并且透过器件晶片330可见。
基于与晶片或衬底的常规平面或工作表面平行的平面来限定如本申请中所使用的相对位置的术语，而不管晶片或衬底的取向。如本申请中所使用的术语“水平的”或“横向的”被定义为与晶片或衬底的常规平面或工作表面平行的平面，而不管晶片或衬底的取向。术语“垂直的”指的是与水平的垂直的方向。关于在晶片或衬底的顶表面上的常规平面或工作表面限定诸如“在...上(on)”、“侧”(如在“侧壁”中)、“较高”、“较低”、“在...之上(over)”、“顶部”和“之下”之类的术语，而不管晶片或衬底的取向。
虽然已经详细地示出了本发明的一个或多个实施例，但是本领域技术人员将理解，可对这些实施例作出修改和改变，而没有背离如在下面权利要求书中所阐述的本发明的范围。

Claims (20)

1.一种制作半导体器件的方法，包括：
提供第一半导体晶片；
在所述第一半导体晶片中形成空腔；
在所述空腔之上将第二半导体晶片键合到所述第一半导体晶片；以及
形成晶体管，所述晶体管包括设置在所述空腔之上的所述晶体管的一部分。
2.如权利要求1所述的方法，其特征在于，形成所述晶体管进一步包括：
在所述空腔之上形成P沟道区域；
在所述空腔的占位外形成漏极区域；以及
在所述P沟道区域和漏极区域之间形成漂移区域。
3.如权利要求1所述的方法，其特征在于，进一步包括在所述第一半导体晶片或第二半导体晶片中在所述空腔之上形成超级结。
4.如权利要求3所述的方法，其特征在于，进一步包括毗邻于所述超级结形成沟道区域。
5.如权利要求1所述的方法，其特征在于，进一步包括在所述第一半导体晶片中形成基准标记。
6.如权利要求1所述的方法，其特征在于，进一步包括在形成所述空腔之前在所述第一半导体晶片上形成外延层。
7.一种制作半导体器件的方法，包括：
提供第一半导体管芯；
在所述第一半导体管芯中形成空腔；
在所述空腔之上将第二半导体管芯键合到所述第一半导体管芯；以及
形成晶体管，所述晶体管包括形成在所述空腔之上的所述晶体管的栅极。
8.如权利要求7所述的方法，其特征在于，进一步包括在沟槽中形成所述栅极。
9.如权利要求7所述的方法，其特征在于，进一步包括完全地在所述空腔的占位内形成漂移区域。
10.如权利要求7所述的方法，其特征在于，进一步包括在所述第一半导体管芯或第二半导体管芯中形成超级结。
11.如权利要求7所述的方法，其特征在于，进一步包括在所述第一半导体管芯之上形成所述栅极。
12.如权利要求7所述的方法，其特征在于，进一步包括在所述第二半导体管芯之上形成所述栅极。
13.如权利要求7所述的方法，其特征在于，进一步包括在所述栅极之上形成互连结构。
14.一种半导体器件，包括：
第一半导体管芯，所述第一半导体管芯包括形成在所述第一半导体管芯中的空腔；
第二半导体管芯，所述第二半导体管芯在所述空腔之上被键合到所述第一半导体管芯；以及
第一晶体管，所述第一晶体管包括形成在所述空腔之上的所述第一晶体管的一部分。
15.如权利要求14所述的半导体器件，其特征在于，进一步包括围绕所述空腔设置的外延层。
16.如权利要求14所述的半导体器件，其特征在于，进一步包括设置在所述第一半导体管芯和第二半导体管芯之间的基准标记。
17.如权利要求14所述的半导体器件，其特征在于，进一步包括形成在所述第一半导体管芯或第二半导体管芯中的超级结。
18.如权利要求14所述的半导体器件，其特征在于，进一步包括形成在所述第一半导体管芯或第二半导体管芯中的降低表面场(RESURF)漂移区域。
19.如权利要求14所述的半导体器件，其特征在于，进一步包括第二晶体管，所述第二晶体管包括形成在所述空腔之上的所述第二晶体管的一部分。
20.如权利要求14所述的半导体器件，其特征在于，进一步包括：
设置在所述第一半导体管芯之上的第一导电层；以及
设置在所述第二半导体管芯之上的第二导电层。
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