CN105826380A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN105826380A CN105826380A CN201510011208.8A CN201510011208A CN105826380A CN 105826380 A CN105826380 A CN 105826380A CN 201510011208 A CN201510011208 A CN 201510011208A CN 105826380 A CN105826380 A CN 105826380A
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, a semiconductor layer, a first well, a second well, a first isolation element, a second isolation element, a gate structure, a first doping area and a second doping area, wherein the semiconductor layer is arranged on the semiconductor substrate; the first well is arranged inside the semiconductor layer and the semiconductor substrate; the second well is arranged in the semiconductor layer; the first isolation element is arranged inside the first well; the second isolation element is arranged inside the second well; the gate structure is arranged in the semiconductor layer between the first isolation element and the second isolation element; the first doping area is arranged in the first well; the second doping area is arranged in the second well; and the bottom surface of the gate structure is higher, lower than or basically in the same level as that of the first isolation element. According to the semiconductor device and the manufacturing method thereof, reduced or avoided unexpected current crowding effects and disruptive voltage reduction can be realized.
Description
Technical field
The present invention is about IC apparatus, and especially with regard to a kind of semiconductor device and manufacture method thereof.
Background technology
In recent years, due to the fast development of the communication device such as device for mobile communication, personal communication device, significantly grow up including as the radio communication product such as mobile phone, base station the most all presents.In the middle of radio communication product, frequently with the high voltage devices of lateral diffusion metal-oxide-semiconductor (LDMOS) device using the element relevant as radio frequency (900MHz-2.4GHz) circuit.
Lateral diffusion metal-oxide-semiconductor device not only has high operation frequency range, simultaneously because can bear relatively high breakdown voltage and have high-output power, thus is suitable as the use of the power amplifier of radio communication product.Additionally, formed owing to lateral diffusion metal-oxide-semiconductor (LDMOS) device may utilize conventional complementary type metal-oxide-semiconductor (MOS) (CMOS) Technology, therefore its manufacturing technology aspect is more ripe and can use made by cost silicon substrate inexpensively.
Summary of the invention
According to an embodiment, the invention provides a kind of semiconductor device, including: semiconductor substrate；Semi-conductor layer, is arranged on this semiconductor substrate；One first trap (well), is arranged in this semiconductor layer and this semiconductor substrate；One second trap, in being arranged at this semiconductor layer and adjacent to this first trap；One first isolation element, is arranged in this first trap；One second isolation element, is arranged in this second trap；One grid structure, is arranged in this semiconductor layer between this first isolation element and this second isolation element；One first doped region, is arranged in this first trap；And one second doped region, it is arranged in this second trap, wherein this semiconductor substrate, this semiconductor layer, this second trap have one first conduction type, and this first trap, this first doped region and this second doped region have one second conduction type in contrast to this first conduction type, and a bottom surface of this grid structure is higher than, be less than or general horizontal is in a bottom surface of this first isolation element.
According to another embodiment, the invention provides the manufacture method of a kind of semiconductor device, including: semiconductor substrate is provided；Form semi-conductor layer on this semiconductor substrate；Form one first trap in this semiconductor layer with this semiconductor substrate；Form one second trap in this semiconductor layer and adjacent to this first trap；In this first trap and one second isolation element is in this second trap to form one first isolation element；Formed in a grid structure this semiconductor layer between this first isolation element and this second isolation element；And in this first trap and one second doped region is in this second trap to form one first doped region, wherein this semiconductor substrate, this semiconductor layer, this second trap have one first conduction type, and this first trap, this first doped region and this second doped region have one second conduction type in contrast to this first conduction type, and a bottom surface of this grid structure is higher than, be less than or general horizontal is in a bottom surface of this first isolation element.
The semiconductor device that the semiconductor device of the present invention and manufacture method thereof provide achieves and less desirable current-crowding effect and the generation of breakdown voltage reduction situation is reduced or avoided.
For the above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and coordinate appended by graphic, be described in detail below.
Accompanying drawing explanation
Fig. 1 is a generalized section, it is shown that according to a kind of semiconductor device of one embodiment of the invention；
Fig. 2-5 is a series of generalized section, it is shown that according to the manufacture method of a kind of semiconductor device of one embodiment of the invention；
Fig. 6-8 is a series of generalized section, it is shown that according to the manufacture method of a kind of semiconductor device of another embodiment of the present invention；
Fig. 9 is a generalized section, it is shown that according to a kind of semiconductor device of further embodiment of this invention；
Figure 10 is a generalized section, it is shown that according to a kind of semiconductor device of another embodiment of the present invention；
Figure 11 is a generalized section, it is shown that according to a kind of semiconductor device of further embodiment of this invention；
Figure 12 is a generalized section, it is shown that according to a kind of semiconductor device of another embodiment of the present invention；
Figure 13 is a generalized section, it is shown that according to a kind of semiconductor device of further embodiment of this invention；
Figure 14 is a generalized section, it is shown that according to a kind of semiconductor device of another embodiment of the present invention；And
Figure 15 is a generalized section, it is shown that according to a kind of semiconductor device of further embodiment of this invention.
Drawing reference numeral illustrates:
10～semiconductor device；
12～semiconductor substrate；
14～semiconductor layer；
16～first trap；
18～second trap；
20～first isolate element；
22～second isolate element；
26～gate insulation layer；
28～conductive layer；
30～doped region；
32～doped region；
34～path；
36～corner；
100,200,300,400,500,600,700,800～semiconductor device；
102～semiconductor substrate；
104～semiconductor layer；
106～trap；
108～trap；
110,110 ', 112～isolation element；
114,114 '～recess；
116～gate insulation layer；
118～conductive layer；
120～doped region；
122～doped region；
130～path；
132～corner；
G～grid structure；
D1～distance；
D2～distance；
D3～depth difference；
D4～depth difference.
Detailed description of the invention
Refer to Fig. 1, it is shown that according to the generalized section of a kind of semiconductor device 10 of one embodiment of the invention.At this, semiconductor device that semiconductor device 10 is known by inventor and being used as a comparative example, it is schematically shown as a lateral diffusion metal-oxide-semiconductor (LDMOS) device, uses the problems such as the experience current-crowding effect of semiconductor device 10 and breakdown voltage reduction that explanation inventor found.But, the enforcement situation of the semiconductor device 10 shown in Fig. 1 is not intended to limit scope of the invention.
As it is shown in figure 1, semiconductor device 10 includes: semiconductor substrate 12；Semi-conductor layer 14, is arranged on semiconductor substrate 12；One first trap 16, is arranged in semiconductor layer 14 and semiconductor substrate 12；One second trap 18, is arranged at 14 the most neighbouring first traps 16 in semiconductor layer；One first isolation element 20, is arranged in the first trap 16；One second isolation element 22, is arranged in the second trap 18；One grid structure G, is arranged on the semiconductor layer 16 between the first isolation element 20 and the second isolation element 22 and part covers the first isolation element 20；One first doped region 32, is arranged in the first trap 16；And one second doped region 30, it is arranged in the second trap 18.
As it is shown in figure 1, a semiconductor substrate 12 for example, silicon substrate, and the epitaxial semiconductor layer that semiconductor layer 14 is formed on semiconductor substrate 12 such as epitaxy method for employing, for example, one silicon epitaxial layers.Semiconductor substrate 12, semiconductor layer 14 and the second trap 18 can have one first conduction type such as N-type or p-type, and first trap the 16, first doped region 30 and the second doped region 32 then have one second conduction type in contrast to the first conduction type such as p-type or N-type.At this, grid structure G is shown as plane grid (planargate) structure, it includes gate insulation layer 26 and the conductive layer 28 being sequentially arranged on semiconductor layer 14, first isolation element 20 and the second isolation element 22 are then shown as shallow trench isolation (shallowtrenchisolation, STI) element, its bottom surface has the end face away from semiconductor layer 14 and is about distance D1 of 0.1-2 micron.
So, the semiconductor device 10 shown in Fig. 1 can be used as the high voltage devices such as lateral diffusion metal-oxide-semiconductor (LDMOS) device.At this, first trap 16 can be used as a drift region (driftregion), in semiconductor layer that second doped region 32 is arranged between the second isolation element 22 and grid structure G 14 and be positioned at one of the second trap 18 to be used as source region (sourceregion), and the first doped region 30 is arranged at the first isolation element 20 not close in the semiconductor layer 14 of the side of grid structure G and be positioned at one of the first trap 16 to be used as a drain region (drainregion).Can apply suitably to bias (not shown) at grid structure G and the first doped region 30 doped region and the second doped region 32 in time operating semiconductor device 10, therefore the carrier (not shown) such as electronics or hole (hole) just can be circulated at the first doped region 30 along a path 34 at the second doped region 32.But, carrier is in the process of circulation along this path 34, Yi Yin at a corner 36 of the first isolation element 20 near at this corner 36, create current-crowding effect because the wide-angle in path 34 changes situation, thus have impact on the reliability of semiconductor device 10.It addition, when semiconductor device 10 operates, it is possible to it is found to associate power line distribution scenario (not shown) and also can produce electric field crowding effect at this corner 36 of the first isolation element 20, thus reduce the breakdown voltage performance of semiconductor device 10.
Therefore, the invention provides a kind of semiconductor device and manufacture method thereof, can be as a kind of semiconductor device being used such as the high voltage devices of lateral diffusion metal-oxide-semiconductor (LDMOS) device using offer, to aforementioned less desirable current-crowding effect and the generation of breakdown voltage reduction situation are reduced or avoided, and provide tool relatively reliable and a kind of semiconductor device of better electrical sex expression.
Refer to Fig. 2-5, it is shown that a series of generalized sections of the manufacture method of a kind of semiconductor device 100 of foundation one embodiment of the invention.
Refer to Fig. 2, first provide such as the semiconductor substrate 102 of silicon substrate.In an embodiment, semiconductor substrate 102 has the first conduction type such as p-type (p-type) and the resistivity (resistivity) between 0.001 to 1000 ohm-cm (Ω-cm).Then by if the method for epitaxial growth is to be formed such as the semi-conductor layer 104 of silicon layer (siliconlayer) on semiconductor substrate 102.This semiconductor layer 104 can adulterate when participating in the cintest just like the admixture of the first conduction type of p-type, and has the resistivity (resistivity) of about 0.001 to 1000 ohm-cm (Ω-cm).In an embodiment, the resistivity of semiconductor layer 104 is more than the resistivity of semiconductor substrate 102.Then, by use and the execution (all not showing) of an ion implantation technology of a patterned mask layer, in semiconductor base 102 one of semiconductor layer 104, a trap 106 is formed.Doped with the admixture in contrast to semiconductor layer 104 with the second conduction type of the first conduction type of semiconductor base 102 in trap 106, for example, N-type admixture, and there is the resistivity (resistivity) of about 0.01 to 100 ohm-cm (Ω-cm).
Refer to Fig. 3, after removing the patterned mask layer for forming trap 106, then pass through the use of another patterned mask layer and the execution (all not showing) of another ion implantation technology, in of the semiconductor layer 104 of adjacent trap 106, form a trap 108.Doped with the admixture of the first conduction type being same as semiconductor layer 104 and semiconductor base 102, for example, p-type admixture in trap 108, and there is the resistivity (resistivity) of about 0.01 to 100 ohm-cm (Ω-cm).Then, in of trap 106, form an isolation element 110 and in of trap 108, form an isolation element 112.This isolates element 110 and 112 a bit and here it is shown that as shallow trench isolation (shallowtrenchisolation, STI) element, it can be formed by the technique of conventional shallow trench isolation element and included the insulant just like silicon oxide, isolates distance D2 of the bottom surface of element 110 and 112 end face about 0.1 2 microns then away from semiconductor layer 104.
Refer to Fig. 4, after removing the patterned mask layer for forming trap 108, then pass through the use of another patterned mask layer and the execution (all not showing) of another etch process, in of the semiconductor layer 104 of adjacent trap 106 and 108, form a recess 114.During forming recess 114, of the isolation element 110 being selectively removed in trap 106, and then it is formed with the recess 114 with class U-shaped (U-likeshape).It should be noted that the bottom surface general horizontal at this recess 114 in the bottom surface of isolation element 110 and 112, the therefore bottom surface of recess 114 and isolate, between element 110 and the bottom surface of 112, the most not there is depth difference.It is subsequently formed a grid structure G of patterning on the semiconductor layer 104 exposed by recess 114 with the surface of isolation element 110 and on the surface of the semiconductor layer 104 of recess 114.Here, the grid structure G of patterning is adjacent to isolate element 110 and part covers the end face isolating element 110.The grid structure G of patterning can include gate insulation layer 116 and the conductive layer 118 sequentially arranged.Based on the purpose simplified, the grid structure G of patterning can be formed by conventional gate technique, and in it, gate insulation layer 116 and conductive layer 118 then can include conventional gate structural material, therefore are not described in detail it at this and implement situation and relative production situation.Here, the bottom surface general horizontal of the part of the grid structure G of patterning is in the bottom surface of isolation element 110 and 112 in the recess 114 being arranged in semiconductor layer 104, and the most not there is depth difference.
Refer to Fig. 5, after removing the patterned mask layer for forming recess 114, then pass through the use of patterned mask layer and the execution (all not showing) of ion implantation technology, a doped region 122 is formed in forming a doped region 120, and of the trap 108 between isolation element 112 and grid structure G in neighbouring isolation element 110 is not in contact with one of the trap 106 of grid structure G.And the admixture of interior one second conduction type doped with the first conduction type in contrast to semiconductor layer 104, semiconductor base 102 and trap 108 of doped region 120 and 122, for example, N-type admixture, and there is the resistivity (resistivity) of about 0.1 to 10 ohm-cm (Ω-cm).
Technique so far, the most substantially completes the making of semiconductor device 100.Semiconductor device 100 as shown in Figure 5 can be used as the high voltage devices such as lateral diffusion metal-oxide-semiconductor (LDMOS) device.Trap 106 can be used as a drift region (driftregion), and doped region 122 can be used as source region (sourceregion), and doped region 120 can be used as a drain region (drainregion).Can apply suitably to bias (not shown) at grid structure G with doped region 120 and 122 in time operating semiconductor device 100, therefore the carrier (not shown) such as electronics or hole just can be circulated at doped region 120 along a path 130 at auto-dope district 122.At this, carrier is in the process of circulation along path 130, in being arranged at semiconductor layer 104 due to of grid structure G herein and its bottom surface general horizontal is in the bottom surface with neighbouring isolation element 110, therefore carrier can't produce current-crowding effect as semiconductor device 10 as shown in Figure 1 at a corner 132 of isolation element 130 at this corner 132 because of the angle change situation in path 130, and then just can ensure that the reliability of semiconductor device 100.Additionally, by as shown in Figure 5 situation is set, when semiconductor device 100 operates, it is also seen that electric field crowding effect can't be produced at this corner 132 of isolation element 110 to associate power line distribution scenario (not shown), and then the breakdown voltage performance of semiconductor device 100 can't be reduced.
Therefore, by the manufacture method shown in Fig. 2-5, just can provide a kind of semiconductor device 100 with the generation reducing or not having aforementioned less desirable current-crowding effect and breakdown voltage reduction situation, its high voltage devices being applicable to such as lateral diffusion metal-oxide-semiconductor (LDMOS) device is used.
Refer to Fig. 6-8, it is shown that a series of generalized sections of the manufacture method of a kind of semiconductor device of foundation another embodiment of the present invention.At this, obtained by the manufacture method of the semiconductor device shown in Fig. 6-8 is the manufacture method by the semiconductor device revised as shown in Figure 2-5, the most only explain orally at the difference between the manufacture method of the semiconductor device shown in Fig. 6-8 and Fig. 2-5, and identical label is to represent similar elements in graphic.
Refer to Fig. 6, by similar in appearance to the manufacture method shown in Fig. 2-3, to provide the structure similar in appearance to Fig. 3 structure shown in Fig. 6.But, in Fig. 6, the isolation element 110 ' formed is in addition to including the part of isolation element 110 as shown in Figure 2, and it further includes towards trap 108 along stretching and be arranged in trap 108 one.
Refer to Fig. 7, then pass through the use of patterned mask layer and the execution (all not showing) of etch process, in of the semiconductor layer 104 of adjacent trap 106 and 108, form a recess 114 '.During forming recess 114 ', it is selectively removed of the isolation element 110 ' crossing over trap 108 and 106, and then forms the recess 114 ' with class U-shaped (U-likeshape).It should be noted that the bottom surface general horizontal of recess 114 ' in the bottom surface of isolation element 110 and 112, therefore the bottom surface of recess 114 ' and the bottom surface isolating element 110 and 112 do not have depth difference.
Refer to Fig. 8, be subsequently formed a grid structure G on the surface of the semiconductor layer 104 exposed by recess 114 ' and the surface of isolation element 110 ' and the semiconductor layer 104 of neighbouring recess 114 ' and isolation element 110 '.Here, the grid structure G of patterning is adjacent to isolate element 110 ' and part covers the end face isolating element 110.Patterned gate structure G can include gate insulation layer 116 and the conductive layer 118 sequentially arranged.Based on the purpose simplified, the grid structure G of patterning can be formed by conventional gate technique, and in it, gate insulation layer 116 and conductive layer 118 then can include conventional gate structural material, therefore are not described in detail it at this and implement situation and relative production situation.Here, the bottom surface general horizontal of the part of the grid structure G of patterning is in the bottom surface of isolation element 110 and 112 in the recess 114 ' being arranged in semiconductor layer 104, and the most not there is depth difference.
Refer to Fig. 8, then pass through and be same as the execution of technique shown in earlier figures 5 and substantially complete the making of semiconductor device 100.Semiconductor device 100 as shown in Figure 8 is same as the semiconductor device 100 shown in Fig. 5, therefore it is also applicable to the application of the high voltage devices such as lateral diffusion metal-oxide-semiconductor (LDMOS) device, and has and be same as the minimizing of the semiconductor device 100 shown in Fig. 5 or not there is less desirable current-crowding effect and breakdown voltage reduces the technology effects such as situation.
The enforcement situation of the semiconductor device of the present invention is not limited with the enforcement situation of the semiconductor device 100 shown in Fig. 5 with Fig. 8, also can include the semiconductor device as shown in Fig. 9-15.Here, the semiconductor device shown in Fig. 9-15 is by amendment obtained by Fig. 5, the semiconductor device 100 shown in 8, and identical label is to represent similar elements in Fig. 9-15 etc. is graphic.Based on the purpose simplified, only explain orally at the difference between Fig. 5, semiconductor device 100 shown in 8 in Fig. 9-15.
Refer to Fig. 9, it is shown that according to a generalized section of a kind of semiconductor device 200 of another embodiment of the present invention.At this, it is different from Fig. 5, the enforcement situation of the semiconductor device 100 shown in 8, in semiconductor device 200 shown in Fig. 9, the bottom surface of the part of the grid structure G being arranged in semiconductor layer 104, less than the bottom surface of isolation element 110 and 112, then has the depth difference D3 less than 0.1 micron between bottom surface and isolation element 110 and the bottom surface of 112 of the part of grid structure G.In an embodiment, this depth difference D3 is the most preferably less than 0.05 micron.So, semiconductor device 200 just can provide and has minimizing or do not have the electrical performance situations such as aforementioned less desirable current-crowding effect and breakdown voltage reduction.
Refer to Figure 10, it is shown that according to a generalized section of a kind of semiconductor device 300 of further embodiment of this invention.At this, it is different from Fig. 5, the enforcement situation of the semiconductor device 100 shown in 8, in semiconductor device 300 shown in Figure 10, the bottom surface of the part of the grid structure G being arranged in semiconductor layer 104 is higher than the bottom surface of isolation element 110 and 112, and has the depth difference D4 less than 0.1 micron between the bottom surface of the part of grid structure G and isolation element 110 and the bottom surface of 112.In an embodiment, this depth difference D4 is the most preferably less than 0.05 micron.So, semiconductor device 300 just can provide and has minimizing or do not have the electrical performance situations such as aforementioned less desirable current-crowding effect and breakdown voltage reduction.
Refer to Figure 11, it is shown that according to a generalized section of a kind of semiconductor device 400 of another embodiment of the present invention.At this, it is different from Fig. 5, the enforcement situation of the semiconductor device 100 shown in 8, in semiconductor device 400 shown in Figure 11, in grid structure G is only arranged at the semiconductor layer 104 of trap 106 and cover the portion top surface of its neighbouring isolation element 100, in a part for the semiconductor layer 104 that doped region 122 is then positioned adjacent to the trap 108 of trap 106.
Refer to Figure 12, it is shown that according to a generalized section of a kind of semiconductor device 500 of further embodiment of this invention.At this, it is different from Fig. 5, the enforcement situation of the semiconductor device 100 shown in 8, in semiconductor device 500 shown in Figure 12, isolation element 110 is along stretching and being arranged in the part of trap 108, and in the semiconductor layer 104 that grid structure G is only arranged in trap 108 and cover the portion top surface of its neighbouring isolation element 110.
Refer to Figure 13, it is shown that according to a generalized section of a kind of semiconductor device 600 of another embodiment of the present invention.At this, it is different from Fig. 5, the enforcement situation of the semiconductor device 100 shown in 8, in semiconductor device 600 shown in Figure 13, isolation element 110 along stretching and being positioned adjacent in the part for trap 106 of trap 108, and in the semiconductor layer 104 that grid structure G is only arranged in trap 108 and neighbouring isolation element 110 but cover the end face of isolation element 110.
Refer to Figure 14, it is shown that according to a generalized section of a kind of semiconductor device 700 of further embodiment of this invention.At this, it is different from Fig. 5, the enforcement situation of the semiconductor device 100 shown in 8, in semiconductor device 700 shown in Figure 14, the semiconductor layer 104 that grid structure G is only arranged in trap 106 is interior and covers its neighbouring portion top surface isolating element 110, in of the trap 108 that doped region 122 is then positioned adjacent to trap 106.Here, grid structure G has a section profile of class zigzag (zig-zag-likeshape), rather than as Fig. 5, in 8 shown in the section profile of class U-shaped (U-likeshape).
Refer to Figure 15, it is shown that according to a generalized section of a kind of semiconductor device 800 of another embodiment of the present invention.At this, it is different from Fig. 5, the enforcement situation of the semiconductor device 100 shown in 8, in semiconductor device 800 shown in Figure 15, grid structure G has the section profile of class zigzag (zig-zag-likeshape), and the end face of the semiconductor layer 104 being only covered in trap 106 but do not cover the end face of its neighbouring isolation element 110, in of the trap 108 that doped region 122 is then positioned adjacent to trap 106.
Semiconductor device as shown in Fig. 9-15 also can be formed by the manufacture method as shown in Fig. 2-5,6-8 etc., it only needs to adjust arranging position and completing for forming the pattern of the patterned mask layer of associated components of associated components in the manufacture method as shown in Fig. 2-5,6-8 etc., therefore is not described in detail in this its relative production.It addition, the bottom surface of the grid structure G in the semiconductor device 400,500,600,700,800 shown in Figure 11-15 is schematically shown as general horizontal in the enforcement situation of the bottom surface of isolation element 110,112.But, in other embodiments, the bottom surface of the grid structure G in the semiconductor device 400,500,600,700,800 shown in Fig. 9-15 also can be as shown in figs. 9-10 as situation, can higher or lower than isolation element 110,112 bottom surface, and and isolation element 110,112 bottom surface between there is the depth difference less than 0.1 micron.In an embodiment, this depth difference is the most preferably less than 0.05 micron.So, the semiconductor device 400,500,600,700,800 as shown in Fig. 9-15 just can provide and has minimizing or do not have the electrical performance situations such as aforementioned less desirable current-crowding effect and breakdown voltage reduction.
Similar in appearance to Fig. 5, the semiconductor device 100 shown in 8, semiconductor device 400,500,600,700,800 shown in Fig. 9-15 is also applicable to the application of the high voltage devices such as lateral diffusion metal-oxide-semiconductor (LDMOS) device, and has and be same as Fig. 5, the minimizing of the semiconductor device 100 shown in 8 or do not have less desirable current-crowding effect and breakdown voltage reduces the technology effects such as situation.
Although the present invention is disclosed above with preferred embodiment; so it is not limited to the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when changing and retouching, therefore protection scope of the present invention is when being as the criterion depending on the defined person of right.
Claims (24)
1. a semiconductor device, it is characterised in that including:
Semiconductor substrate；
Semi-conductor layer, is arranged on described semiconductor substrate；
One first trap, is arranged in described semiconductor layer and described semiconductor substrate；
One second trap, in being arranged at described semiconductor layer and adjacent to described first trap；
One first isolation element, is arranged in described first trap；
One second isolation element, is arranged in described second trap；
One grid structure, is arranged in the described semiconductor layer between described first isolation element and described second isolation element；
One first doped region, is arranged in described first trap；And
One second doped region, it is arranged in described second trap, wherein said semiconductor substrate, described semiconductor layer, described second trap have one first conduction type, and described first trap, described first doped region and described second doped region have one second conduction type in contrast to described first conduction type, and a bottom surface of described grid structure is higher than, less than or level in the described first bottom surface isolating element.
2. semiconductor device as claimed in claim 1, it is characterised in that described first conduction type is p-type, and described second conduction type is N-type.
3. semiconductor device as claimed in claim 1, it is characterised in that described first conduction type is N-type, and described second conduction type is p-type.
4. semiconductor device as claimed in claim 1, it is characterised in that the described bottom surface of described grid structure is higher or lower than the described bottom surface of described first isolation element, and has the depth difference less than 0.1 micron.
5. semiconductor device as claimed in claim 1, it is characterized in that, the described bottom surface level of described grid structure is in the described first bottom surface isolating element, and does not has depth difference between the described bottom surface of the described bottom surface of described grid structure and described first isolation element.
6. semiconductor device as claimed in claim 1, it is characterised in that described first isolation element is separator with shallow grooves with described second isolation element.
7. semiconductor device as claimed in claim 1, it is characterised in that described grid structure is arranged in the described semiconductor layer of described first trap between described first isolation element and described second isolation element and described second trap, and has a shape of class U-shaped.
8. semiconductor device as claimed in claim 1, it is characterised in that described grid structure is arranged in the described semiconductor layer of described first trap between described first isolation element and described second isolation element, and has an analog-U shaped shape.
9. semiconductor device as claimed in claim 1, it is characterised in that described grid structure is arranged in the described semiconductor layer of described second trap between described first isolation element and described second isolation element, and has a shape of class U-shaped.
10. semiconductor device as claimed in claim 1, it is characterized in that, described first isolation element is more arranged in the second trap, and described grid structure is arranged in the described semiconductor layer of described second trap between described first isolation element and described second isolation element, and there is a shape of class U-shaped.
11. semiconductor devices as claimed in claim 1, it is characterized in that, described grid structure is arranged in the described semiconductor layer of described first trap between described first isolation element and described second isolation element and described second trap, and has a shape of class zigzag.
The manufacture method of 12. 1 kinds of semiconductor devices, it is characterised in that including:
Semiconductor substrate is provided；
Form semi-conductor layer on described semiconductor substrate；
Form one first trap in described semiconductor layer with described semiconductor substrate；
Form one second trap in described semiconductor layer and adjacent to described first trap；
In described first trap and one second isolation element is in described second trap to form one first isolation element；
Form a grid structure to isolate in the described semiconductor layer between element and described second isolation element in described first；And
In described first trap and one second doped region is in described second trap to form one first doped region, wherein said semiconductor substrate, described semiconductor layer, described second trap have one first conduction type, and described first trap, described first doped region and described second doped region have one second conduction type in contrast to described first conduction type, and a bottom surface of described grid structure is higher than, less than or level in the described first bottom surface isolating element.
The manufacture method of 13. semiconductor devices as claimed in claim 12, it is characterised in that described first conduction type is p-type, and described second conduction type is N-type.
The manufacture method of 14. semiconductor devices as claimed in claim 12, it is characterised in that described first conduction type is N-type, and described second conduction type is p-type.
The manufacture method of 15. semiconductor devices as claimed in claim 12, it is characterised in that the described bottom surface of described grid structure is higher or lower than the described bottom surface of described first isolation element, and has the depth difference less than 0.1 micron.
The manufacture method of 16. semiconductor devices as claimed in claim 12, it is characterized in that, the described bottom surface level of described grid structure is in the described first bottom surface isolating element, and does not has depth difference between the described bottom surface of the described bottom surface of described grid structure and described first isolation element.
The manufacture method of 17. semiconductor devices as claimed in claim 12, it is characterised in that described first isolation element is separator with shallow grooves with described second isolation element.
The manufacture method of 18. semiconductor devices as claimed in claim 12, it is characterized in that, described grid structure is formed in the described semiconductor layer of described first trap between described first isolation element and described second isolation element and described second trap, and has a shape of class U-shaped.
The manufacture method of 19. semiconductor devices as claimed in claim 18, it is characterised in that form described grid structure and isolate in the described semiconductor layer between element and described second isolation element in described first, including:
Being formed in of the recess described semiconductor layer in adjacent described first trap with described second trap, wherein said recess is isolated element adjacent to described first and has a shape of class U-shaped；And
Forming described grid structure isolate on the described semiconductor layer between element and described second isolation element in described first and be positioned on described recess, wherein said grid structure has the shape of class U-shaped.
The manufacture method of 20. semiconductor devices as claimed in claim 18, it is characterized in that, described first isolation element is more formed in one of the second trap, and forms described grid structure and isolate in the described semiconductor layer between element and described second isolation element in described first, including:
Formed in of the recess described semiconductor layer in adjacent described first trap with described second trap, wherein said recess is adjacent to described first isolation element and has a shape of class U-shaped, and eliminates the described first isolation element in this portion being formed at described second trap in time forming described recess and be positioned at of described first isolation element of described first trap；And
Forming described grid structure isolate on the described semiconductor layer between element and described second isolation element in described first and be positioned on described recess, wherein said grid structure has the shape of class U-shaped.
The manufacture method of 21. semiconductor devices as claimed in claim 12, it is characterised in that described grid structure is formed in the described semiconductor layer of described first trap between described first isolation element and described second isolation element, and has an analog-U shaped shape.
The manufacture method of 22. semiconductor devices as claimed in claim 12, it is characterised in that described grid structure is formed in the described semiconductor layer of described second trap between described first isolation element and described second isolation element, and has a shape of class U-shaped.
The manufacture method of 23. semiconductor devices as claimed in claim 12, it is characterized in that, described first isolation element is more formed in the second trap, and described grid structure is arranged in the described semiconductor layer of described second trap between described first isolation element and described second isolation element, and there is a shape of class U-shaped.
The manufacture method of 24. semiconductor devices as claimed in claim 12, it is characterized in that, described grid structure is formed in the described semiconductor layer of described first trap between described first isolation element and described second isolation element and described second trap, and has a shape of class zigzag.
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| CN101211980A (en) * | 2006-12-29 | 2008-07-02 | 东部高科股份有限公司 | High voltage semiconductor device and its fabrication method |
| KR20110079021A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Semiconductor device method for manufacturing the same |
| KR20130073776A (en) * | 2011-12-23 | 2013-07-03 | 주식회사 동부하이텍 | Ldmos transistor device and preparing method of the same |
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| US20050001265A1 (en) * | 2003-06-13 | 2005-01-06 | Satoshi Shiraki | Semiconductor device and method for manufacturing the same |
| CN101211980A (en) * | 2006-12-29 | 2008-07-02 | 东部高科股份有限公司 | High voltage semiconductor device and its fabrication method |
| KR20110079021A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Semiconductor device method for manufacturing the same |
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