CN105826344A - Image sensor and preparation method of pixel units of image sensor - Google Patents
Image sensor and preparation method of pixel units of image sensor Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductors, and discloses an image sensor and a preparation method of pixel units of the image sensor. The image sensor includes a plurality of pixel units that form an array, each pixel unit includes a photodiode, a field effect transistor and a bipolar transistor, wherein the photodiode is connected with a source region of the field effect transistor, and a drain region of the field effect transistor is connected with a base region of the bipolar transistor; a grid region of the field effect transistor is led out as a control end of the pixel unit, and an emitter region of the bipolar transistor is led out as an output end of the pixel unit; and the photodiode collects rays of light to generate electrical signals, and the electrical signals are output after further amplification through the combination of the field effect transistor and the bipolar transistor. Compared with the prior art, the image sensor is beneficial to providing better imaging quality.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of imageing sensor and the preparation method of pixel cell thereof.
Background technology
Imageing sensor is a kind of device converting optical signals into the signal of telecommunication.Imageing sensor is widely used in the technical field of such as digital camera, camcorders, smart mobile phone, game machine, security monitoring video camera, medical miniature photographing unit, telescope etc..Along with the development of science and technology, the demand of high-performance image sensors is quickly increased.
Wherein, CMOS complementary metal-oxide-semiconductor (CMOS) imageing sensor is one of imageing sensor of current main flow.One pixel of cmos image sensor comprises: a photodiode, and in order to produce the electric charge proportional to incident illumination, it also contains some other electronic component simultaneously, to provide caching conversion and reset function.The electric charge accumulated when the electric capacity in each pixel reaches some and is transmitted to signal amplifier again by after digital-to-analogue conversion, and the primary signal of captured image is really formed.Cmos image sensor has the advantages such as low cost, power consumption be little, but in terms of image quality, still suffers from certain improvement space.
Summary of the invention
It is an object of the invention to provide the preparation method of a kind of imageing sensor and pixel cell thereof, to provide more preferably image quality.
For solving above-mentioned technical problem, embodiments of the present invention provide a kind of imageing sensor, comprise: a plurality of pixel cells of composition array, each pixel cell comprises: a photodiode, a field-effect transistor and a bipolar transistor；Wherein, described photodiode is connected with the source region of described field-effect transistor, and the drain region of described field-effect transistor is connected with the base of described bipolar transistor；The control end as described pixel cell is drawn in the grid region of described field-effect transistor, and the outfan as described pixel cell is drawn in the launch site of described bipolar transistor；Wherein, described photodiode collection light produces the signal of telecommunication, and the described signal of telecommunication is amplified further by the combination of described field-effect transistor and described bipolar transistor and exports afterwards.
Embodiments of the present invention additionally provide the preparation method of a kind of image sensor pixel cells, comprise the steps of
One highly doped substrate is provided；
Lightly doped epitaxial layer is grown, as the collecting zone of bipolar transistor in substrate；
On described epitaxial layer, form gate oxide, and on described gate oxide, form the grid region of field-effect transistor；
On epitaxial layer, carry out photoetching for the first time, output window, carry out ion implanting for the first time, form the source region of field-effect transistor；Wherein, the photoresist being lithographically derived for the first time at least covers the reserved region making bipolar transistor；
On epitaxial layer, carry out second time photoetching, output window, carry out second time ion implanting, form the drain region of field-effect transistor；Wherein, the photoresist that second time is lithographically derived at least covers the reserved region making bipolar transistor；
On epitaxial layer, carry out third time photoetching, output window, carry out third time ion implanting, form the base of bipolar transistor；Wherein, the photoresist that third time is lithographically derived at least covers the region at field-effect transistor place；
Carry out the 4th secondary ion to inject, form the launch site of bipolar transistor；
Transmission region is formed in the position corresponding to described source region；
Described grid region and described launch site are drawn, obtains control end and the outfan of pixel cell.
nullEmbodiment of the present invention is in terms of existing technologies，Each pixel cell of composition imaging array comprises a photodiode、One field-effect transistor and a bipolar transistor，And photodiode is connected with the source region of field-effect transistor，The drain region of field-effect transistor is connected with the base of bipolar transistor，And the control end as pixel cell is drawn in the grid region of field-effect transistor，The outfan as pixel cell is drawn in the launch site of bipolar transistor，Thus，The light of collection is converted into the signal of telecommunication by photodiode，Owing to photodiode is connected with the source region of field-effect transistor，So this signal of telecommunication can cause the drain charge of field-effect transistor to change under the effect controlling end，And this change in electrical charge is exported by emitter bipolar transistor (i.e. outfan) after bipolar transistor amplifies，Therefore，Changed by the voltage (or electric current) of the outfan of the bipolar transistor in monitoring certain time，The intensity of light can be detected.The imageing sensor of present embodiment is in each pixel cell, the corresponding component process to imageing sensor is exported again after all directly the signal of telecommunication produced by light being amplified, therefore, the imageing sensor of present embodiment is able to detect that fainter optical signal, thus there is more preferably sensitivity, improve image quality.
Preferably, described pixel cell comprises substrate, it is formed at the epitaxial layer collecting zone as described bipolar transistor of described substrate, the base of the source region of field-effect transistor, drain region and the bipolar transistor that are formed in described epitaxial layer and launch site, it is formed at the gate oxide between the source region of field-effect transistor, drain region on described epitaxial layer, is formed at the grid region of field-effect transistor on described gate oxide；Wherein, the grid region of described field effect field-effect transistor, and the launch site extraction of described bipolar transistor, as control end and the outfan of described pixel cell；The source region region of described pixel cell scene effect field-effect transistor is transmission region, and the source region of described field effect field-effect transistor is used for collecting light by described transmission region as described photodiode.
Preferably, the drain region of described field-effect transistor and the base of described bipolar transistor are adjacent.
Preferably, there is isolation area, described drain region and described base by being formed at the layer metal interconnection on described epitaxial layer between drain region and the base of described bipolar transistor of described field-effect transistor.
Accompanying drawing explanation
Fig. 1 a is structure and the circuit theory schematic diagram of the pixel cell drawn from front according to first embodiment of the invention colelctor electrode；
Fig. 1 b is structure and the circuit theory schematic diagram of the pixel cell drawn from the back side according to first embodiment of the invention colelctor electrode；
Fig. 1 c is the electromotive force schematic diagram according to first embodiment of the invention illumination charging preceding pixel unit；
Fig. 1 d is according to the electromotive force schematic diagram of pixel cell after first embodiment of the invention illumination charging；
Fig. 1 e is according to the electromotive force schematic diagram of pixel cell in first embodiment of the invention electronic transfer process；
Fig. 1 f is according to the electromotive force schematic diagram of pixel cell after first embodiment of the invention electron transfer；
Fig. 2 a is the emitter current Ie according to first embodiment of the invention pixel cell and emitter voltage Ve relation curve schematic diagram under simulated conditions；
Fig. 2 b is that the drain current Id and drain voltage Vd of field-effect transistor are at the relation curve schematic diagram having under identical simulated conditions with Fig. 2 a；
Fig. 3 a is the transfer characteristic emulation schematic diagram according to first embodiment of the invention pixel cell；
Fig. 3 b is the pixel cell Current amplifier characteristic Simulation schematic diagram according to first embodiment of the invention；
Fig. 4 a is the output characteristics of the collector current Ic relative transmission pole tension Ve according to first embodiment of the invention pixel cell；
Fig. 4 b is the output characteristics of the source current Is relative transmission pole tension Ve according to first embodiment of the invention pixel cell；
Fig. 5 is according to first embodiment of the invention pixel cell and the 1/f noise characteristic of single FET；
Fig. 6 a is according to the current direction distribution schematic diagram of first embodiment of the invention pixel cell；
Fig. 6 b is according to the Current amplifier curve synoptic diagram of first embodiment of the invention pixel cell；
Fig. 7 a is the structural representation of the imageing sensor including passive pixel cell according to first embodiment of the invention；
Fig. 7 b is the structural representation of the imageing sensor including active pixel cell according to first embodiment of the invention；
Fig. 8 is the flow chart of the preparation method according to second embodiment of the invention pixel cell；
Fig. 9 is the structural representation of pixel cell that the step 802 of the preparation method according to second embodiment of the invention pixel cell prepares；
Figure 10 be the preparation method according to second embodiment of the invention pixel cell step 803 prepare structural representation；
Figure 11 be the preparation method according to second embodiment of the invention pixel cell step 804 prepare structural representation；
Figure 12 is the structural representation of the pixel cell prepared according to step 805 when drawing colelctor electrode in the preparation method of second embodiment of the invention from front；
Figure 13 is the structural representation of the pixel cell prepared according to step 806 when drawing colelctor electrode in the preparation method of second embodiment of the invention from front；
Figure 14 is the structural representation of the pixel cell prepared according to step 807 when drawing colelctor electrode in the preparation method of second embodiment of the invention from front；
Figure 15 is the structural representation of the pixel cell prepared according to step 809 when drawing colelctor electrode in the preparation method of second embodiment of the invention from front；
Figure 16 is the structural representation according to the pixel cell prepared when drawing colelctor electrode in the preparation method of third embodiment of the invention from the back side.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, it will be understood by those skilled in the art that in each embodiment of the present invention, in order to make reader be more fully understood that, the application proposes many ins and outs.But, even if there is no these ins and outs and many variations based on following embodiment and amendment, it is also possible to realize the application each claim technical scheme required for protection.
First embodiment of the present invention relates to a kind of imageing sensor, for the image sensor cell of the imaging device as digital camera, smart mobile phone, game machine etc., its core is that each pixel cell of imageing sensor is made up of the mixed structure of photodiode, field-effect transistor (Ion-SensitiveField-EffectTransistor:FET) and bipolar transistor (BipolarJunctionTransistor:BJT).
In present embodiment, imageing sensor comprises: a plurality of pixel cells of composition array.Wherein, each pixel cell comprises: a photodiode, a field-effect transistor and a bipolar transistor.Wherein, photodiode is connected with the source region of field-effect transistor, and the drain region of field-effect transistor is connected with the base of bipolar transistor.The control end as pixel cell is drawn in the grid region of field-effect transistor, and the outfan as pixel cell is drawn in the launch site of bipolar transistor.Photodiode collection light produces the signal of telecommunication, and the signal of telecommunication is amplified further by the combination of field-effect transistor and bipolar transistor and exports afterwards.
Shown in Fig. 1 a, the basic structure of each pixel cell is described in detail.Each pixel cell comprises: substrate 1, is formed at the epitaxial layer 2 collecting zone as bipolar transistor of substrate.Unrestricted as an example, the substrate in present embodiment can select silicon substrate, silicon carbide substrates or cadmium (Ge) substrate.Pixel cell also comprises base 5 and the launch site 6 forming the source region 3 of field-effect transistor, drain region 4 and bipolar transistor in the epitaxial layer, it is formed at the gate oxide between the source region 3 of field-effect transistor on epitaxial layer 2, drain region 4, is formed at the grid region 7 of field-effect transistor on gate oxide.The drain region 4 of field-effect transistor and the base 5 of bipolar transistor are adjacent.The collecting zone 9 of pixel cell is drawn the colelctor electrode 90 obtaining pixel cell by present embodiment by its front, specifically, forms the heavily doped region connecting substrate, drawn by heavily doped region, obtain the colelctor electrode 90 of pixel cell in epitaxial layer 2.So that form good insulation between each terminal drawn, pixel cell also comprises formation on substrate 1 for the oxidation insulating layer 8 of electric isolation.The collecting zone 9 of pixel cell, grid region 7 and launch site 6 are formed with contact hole and through hole, and pixel cell also comprises the dielectric layer and metal interconnecting wires being formed between each contact hole and through hole.The collecting zone (i.e. connecting epitaxial layer and the heavily doped region of substrate) of bipolar transistor is drawn by metal interconnecting wires, as the colelctor electrode 9 of pixel cell.The grid region 7 of field-effect transistor, and the launch site 6 of bipolar transistor drawn by metal interconnecting wires, respectively as control end 70 and the outfan 60 of pixel cell.
In present embodiment, pixel cell also comprises the first isolation area 10 being formed in epitaxial layer 2 and outside heavily doped region and launch site and the second isolation area 11 being formed between the drain region 4 of field-effect transistor and the base 5 of bipolar transistor, pixel cell also comprises the metal level 12 being formed on epitaxial layer 2, and the drain region 4 of field-effect transistor and the base 5 of bipolar transistor are interconnected by this metal level 12.Generally, the first isolation area 10 or the second isolation area 11 can use shallow trench isolation technology (ShadowTrenchIsolation is called for short STI) or localized oxidation of silicon technology to be formed.By increasing by the first isolation area advantageously in the large-scale integrated of imageing sensor.
It should be noted that the colelctor electrode controlling end, outfan and field-effect transistor of pixel cell is drawn by the front of pixel cell in present embodiment.In other embodiments, the colelctor electrode of the field-effect transistor of pixel cell can also be drawn from the back side (i.e. substrate) of pixel cell, as shown in Figure 1 b.Additionally, the base of the drain region of pixel cell field-effect transistor and bipolar transistor can be with direct neighbor, so that the structure of pixel cell more simplifies.
In present embodiment, the control end 70 as pixel cell is drawn in the grid region 7 of field-effect transistor, the outfan 60 as pixel cell is drawn in the launch site 6 of bipolar transistor.Compared with existing field-effect transistor, the pixel cell of present embodiment is non-geometrically symmetric, and this makes the pixel cell of present embodiment can compatible different geometry designs and dopant dose (doping).In addition, drain region and the dipolar effect of substrate due to field-effect transistor, when the drain region of field-effect transistor presents negative pressure, field-effect transistor can produce bigger negative current, and in present embodiment, owing to the transmitting terminal of pixel cell has a PNP bipolar, therefore, pixel cell will not produce the biggest negative current.
In present embodiment, silicon substrate or silicon carbide substrates carrying out epitaxial growth, form the collecting zone of vertical PNP pipe, N-district (i.e. N-type is lightly doped district) is connected as the base of PNP pipe, the drain electrode with the field-effect transistor FET of N-channel.Therefore, the operation principle of single pixel cell is as follows:
Grid 70 at metal-oxide-semiconductor applies high voltage so that the electromotive force in source region 3, grid region 7 and drain region 4 reaches steady statue, as illustrated in figure 1 c.After light (photon) arrives in the silicon body (the namely source region of metal-oxide-semiconductor) of photodiode, on part lattice, the covalent bond of silicon atom is interrupted, thus form electron hole pair, the number of its electronics being released is proportional to the intensity of incident illumination, as shown in Figure 1 d, electric charge is put aside in source region 3.Remove the high voltage of grid 7, put aside the electric charge in source region 3 and shift to drain region 4, as shown in fig. le.After certain time, electric charge transfer reaches steady statue, as shown in Figure 1 f.The change in electrical charge in drain region 4 is amplified by BJT pipe, and the change in electrical charge reading this amplification in the launch site of BJT i.e. can obtain being incident on the intensity of the light of source region.What deserves to be explained is, the extraction electrode of launch site connects different testing circuits change in electrical charge can be converted into the change-detection of electric current or voltage.
Present embodiment is verified for the characteristic of pixel cell by using semiconductor technology and device simulation software SilvacoTCAD (TechnologyComputerAidedDesign).And by emulation data, working condition, the characteristic of present embodiment pixel cell are further described as follows:
Fig. 2 a shows emitter stage (i.e. the outfan of pixel cell) electric current Ie and the emitter voltage Ve relation curve schematic diagram under simulated conditions of pixel cell.Fig. 2 b shows that the drain current Id and drain voltage Vd of the internal FET of pixel cell are at the relation curve schematic diagram having under identical simulated conditions with Fig. 2 a.Wherein, grid (i.e. the control end of pixel cell) voltage Vg=1V, collector voltage Vc=0V, substrate (Sub) voltage VSub=0V, source voltage Vsource=0V.Drain voltage Vd and emitter voltage Ve voltage increase to 3V from 0V respectively.As Vg=1V, in saturation region, the emitter current Ie of pixel cell is equivalent to 100 times of the drain current of independent FET under the same terms.From Fig. 2 a, 2b, as drain voltage Vd > 0, field-effect transistor can produce electric current, and the drain current Id of field-effect transistor reaches saturated along with the increase of drain voltage Vd.And for the pixel cell of present embodiment, starting to produce electric current as emitter voltage Ve > 0.7V, this is owing to the threshold voltage of PN junction self determines.The electric current of pixel cell saturation region has reached 10E-4 order of magnitude level, is 100 times of independent FET current gain.Understand through analyzing, pixel cell reach saturation need two pre-conditioned: in first pixel cell, the grid voltage Vg of FET should be more than the threshold voltage of FET, and it two is that the emitter voltage Ve on BJT should be more than the threshold voltage of PN junction.
As Fig. 3 a shows the transfer characteristic of present embodiment pixel cell, i.e. pixel cell source current Is and grid voltage Vg relation curve.In Fig. 3 a, Is represents the source current of the internal FET of pixel cell, and Ic represents the collector current of pixel cell, and gms, gmc represent corresponding mutual conductance.VT represents that threshold voltage, Vg=1, gm reach peak value, as shown in the vertical line in Fig. 3 a.Fig. 3 b shows the current gain ratio of source current (collector current with) curve.From Fig. 3 b, the current gain within the pixel cell current gain more than independent FET, this current gain is the ratio of collector current Ic and source current Is, owing to collector current Ic is similar to emitter current Ie, so the unified ratio (i.e. Ie/Is) for emitter current Ie and source current Is of the current gain in present embodiment.The ratio of emitter voltage Ve=1V, the biggest and stable Direct Current gain drain current Id and source current Is all reaches 80 times at linear zone (linear zone condition: emitter stage and source voltage difference Ves<grid voltage Vg-threshold V T) and saturation region (saturation conditions: emitter stage and source voltage difference Ves>grid voltage Vg-threshold V T).As grid voltage Vg, < during threshold V T, the collector current Ic current gain relative to source current Is can reach 180 times.
< during 0.7V the least, because the threshold voltage of the PN junction in BJT (i.e. bipolar transistor) is less than emitter voltage Ve, only 0.7V at Ve from Fig. 4 a, 4b, collector current Ic and source current Is.Because the FET within pixel cell has threshold V T, two curves when grid voltage takes 0.8V, 0.4V respectively each fall within subthreshold region.When grid voltage takes 1.2V and 1.5V respectively, two curves reach saturation current, and in Fig. 4 a, collector current is 10-2A, Fig. 4 b source current Is is 10-4A, this result shows that pixel cell achieves amplification.
Pixel cell is bound to be affected because of the interference of low frequency signal.From mobility theory of fluctuation (mobilityfluctuationtheory), power spectral density (powerspectrumdensity) S of noiseIIt is that the emitter current Ie in pixel cell and frequency noise f together decides on.And SI FETTogether decided on by source current Is and noise frequency.Such as SI/ I2=αH/fNtotal, αHIt is person of outstanding talent's lattice (Hooge) constant, typically takes 2x10-3.4, SVThen can be affected by grid voltage, SV/SI=gm2.2, Vg take 1.5V, and Ve, Vd take the FET of 1V, pixel cell and Qi Nei respectively and be all operated in linear zone, SVF and SV FETSimulation result as shown in Figure 5 noise apply in be verified.The characteristic of the FET of pixel cell and Qi Nei all presents negative correlation along with frequency.And the 1/f noise of pixel cell is compared with the FET that it is interior, reducing 5.7 times, this shows that pixel cell has more preferably low frequency noise capacity of resisting disturbance than single FET.
Owing to the current path of FET is identical with NMOS, its electric current flows to source electrode from drain electrode, overcomes the grid voltage Vg more than threshold voltage.And pixel cell electric current is entirely different with FET in present embodiment.As shown in Figure 6 a, the electric current of pixel cell comprises two paths, the vertical current in first BJT, and it two is the horizontal current in FET.Wherein, the electric current that drives of pixel cell is mainly the vertical direction electric current that BJT produces.As shown in Figure 6 b, horizontal direction electric current is only the 1% of vertical direction electric current.It is true that FET also has the least vertical direction electric current, it is produced by hot carrier.The vertical current of FET is all harmful for the stability of FET threshold voltage and gate oxide integrity and reliability.Vertical current in pixel cell is about 100 times of horizontal current, and this makes pixel cell have stable amplification electric current.
For large scale integrated circuit manufactures, the big process window (bigprocesswindow) of the bipolar transistor of pixel cell is to ensure that the key of device performance consistent (such as amplification β (emitter current and the ratio of source current)), especially when to use 110 nanometer technology on 8 inch silicon wafer, between device, between chip, the uniformity requirement between silicon chip is the strictest.As it is shown in figure 1, w1 represents the horizontal width of BJT base, w2 represents BJT base vertical width.W1 takes reference value 0.35 micron (micrometer is called for short um), w2 reference value 0.3 micron, increases both reference values respectively or reduces 0.1 micron, and carrying out 8 groups of experiments, and table 1 is shown in which a kind of reference conditions.In base horizontal direction, keeping amplification β is a constant, obtains different w1 values by amendment and is respectively 0.25,0.35,0.45 micron.It may be seen that when the tolerance of horizontal direction base width is 30%, prepared device still has good concordance.Also illustrate that primarily longitudinal bipolar transistor is playing amplification, changing horizontal base width does not affect amplification.And in base vertical direction, amplification β and doping depth are inversely proportional to, wherein w2 respectively take 0.2,0.3., 0.4 micron.The value of amplification β is constant with the product of the longitudinally wide w2 in base, and this shows that different operating currents can obtain by adjusting the longitudinally wide w2 in base with amplification β, such that it is able to optimize the signal amplification characteristic of pixel cell.
Table 1
In sum, the pixel cell of present embodiment has preferably Direct Current amplifying power and the capacity of resisting disturbance of low-frequency noise.Disclosure satisfy that the coherence request of 110 nanometer processing procedures.And amplification β can be adjusted according to the base of BJT is longitudinally wide.These characteristics make the pixel cell of present embodiment require, at gene order detection and cmos imaging etc., the great competitiveness in field that large-scale integrated, high density are integrated.
In conjunction with above-mentioned pixel cell, may be constructed passive pixel sensor and CMOS active pixel sensor, illustrate individually below:
It is the imageing sensor schematic diagram including passive pixel cell array as shown in Figure 7a.Wherein, pixel image sensor comprises: array 1, row select line 20, column selection line 30 and sense amplifier 3.The control end 100 of the pixel cell 10 being positioned at same a line in array 1 is connected to same row select line 20.The outfan 101 of the pixel cell 10 being positioned at same string in array 1 is connected to same column selection line 30.Column selection line 30 connects sense amplifier 3.
Being active pixel cell structural representation as shown in Figure 7b, imageing sensor can also comprise: position output lead and the sense amplifier being connected with position output lead.Imageing sensor is also correspondingly arranged on a reset transistor T1 at each pixel cell 10, a transistor T2 and row gating transistor T3 is followed in a source.The grid that the outfan 101 of pixel cell 10 follows transistor T2 with the source electrode of reset transistor T1 and source is connected.The source electrode of source electrode and row gating transistor T3 that transistor T2 is followed in source is connected.The drain electrode of reset transistor T1 and source are followed the drain electrode of transistor T2 and are connected power supply.The grid of the grid of reset transistor T1 and row gating transistor T3 connects reset signal and row gating signal respectively.The drain electrode of row gating transistor connects position output lead.It is by light sensitive diode, reset transistor T1, source follower T2 and row gating switch pipe T3 composition.Light sensitive diode and electric capacity are resetted by reset transistor T1, and the effect of source follower T2 is to realize amplifying and buffering signal, improves the noise problem of APS.Source follower may also speed up the discharge and recharge of bus capacitance, and hence allowing to bus length increases and pixel scale increase.The work process of this kind of imageing sensor is: initially entering " reset state ", T1 opens, and resets light sensitive diode, but enter " sample states ", T1 closes, and light is irradiated on photodiode produce photo-generated carrier, and amplifies output by source follower T2.Finally entering " reading state ", at this moment row gate tube T3 opens, and signal is exported by column bus.
By Fig. 7 a and 7b, the imageing sensor of present embodiment both can realize passive design, it would however also be possible to employ active design, designs the most flexible.
Additionally, what deserves to be explained is, present embodiment is with P type substrate; it is illustrated as a example by the metal-oxide-semiconductor of N-type source and drain and the BJT pipe of positive-negative-positive; but the present invention should not be as restriction, also should be within protection scope of the present invention with N-type substrate, the metal-oxide-semiconductor of p-type source and drain and the BJT pipe of NPN type.
Second embodiment of the present invention relates to the preparation method of a kind of imageing sensor, and its flow process as shown in Figure 8, comprises the steps of
Step 801: a highly doped substrate is provided.Unrestricted as an example, the substrate of present embodiment is highly dope p-type substrate.
Step 802: grow lightly doped epitaxial layer in substrate, as the collecting zone of bipolar transistor.Corresponding to the highly dope p-type substrate in step 801, the epitaxial layer in present embodiment is doped with P type epitaxial layer.In this step, it is also possible to forming isolation area at epitaxial layer, isolation area comprises the first isolation area 10 and the second isolation area 11, wherein, second isolation area is used for the drain region of isolation camp effect transistor and the base of bipolar transistor, and the first isolation area is positioned at the two ends of epitaxial layer, as shown in Figure 9.
Step 803: form gate oxide on epitaxial layer, and form the grid region of field-effect transistor on gate oxide.Specifically, can use following sub-step make grid region:
Thermal oxidation process grows gate oxide 7 on epitaxial layer, and depositing polysilicon also adulterates, and etches polysilicon gate figure, lightly doped drain (lightlydopeddrain, LDD) N-type impurity ion implanting, forms LDD shallow junction, forms side wall in gate oxide both sides.Cause short-channel effect for preventing the source region drain region injection of heavy dose from getting too close to raceway groove, to form side wall after the ldd implantation in the both sides of polysilicon gate.Depositing silicon dioxide at silicon chip surface, dry etching is until exposing polysilicon surface.Due to anisotropic etching, polysilicon gate both sides retain silicon dioxide side wall, as shown in Figure 10.
Step 804: carry out photoetching for the first time on epitaxial layer, output window, carries out ion implanting for the first time, forms the source region of field-effect transistor.Wherein, the photoresist being lithographically derived for the first time at least covers the reserved region making bipolar transistor.The photoresist being lithographically derived for the first time at least covers the reserved region making bipolar transistor.In this step, photoresist also covers the reserved region for making bipolar transistor collecting zone, and this collecting zone reserved area is adjacent with isolation area 10.Field-effect transistor source region 3 is formed after annealing.In present embodiment, being formed in step 802 in the step of isolation area 10, be preset with the collecting zone 9 of bipolar transistor inside isolation area 10, the structure that therefore step 804 is formed is as shown in figure 11.
Step 805: carry out second time photoetching on epitaxial layer, output window, carries out second time ion implanting, forms the drain region of field-effect transistor.Wherein, the photoresist that second time is lithographically derived at least covers the reserved region making bipolar transistor, as shown in figure 12.
Step 806: carry out third time photoetching on epitaxial layer, output window, carries out third time ion implanting, forms the base of bipolar transistor.Wherein, the photoresist that third time is lithographically derived at least covers the region at field-effect transistor place.I.e. region in addition to the base except reserved bipolar transistor arranges photoresist, outputs the window that base is corresponding, and N-type low dosage foreign ion injects, thus forms the base 5 of bipolar transistor, as shown in figure 13.
Step 807: carry out the 4th secondary ion and inject, form the launch site of bipolar transistor.In present embodiment, the region in addition to the launch site except reserved bipolar transistor arranges photoresist, the window that Kai Qu launch site is corresponding, and p-type heavy doping foreign ion injects, thus forms the launch site 6 of bipolar transistor, as shown in figure 14.Specifically, on epitaxial layer, carry out third time photoetching, output window, carry out the 4th secondary ion and inject, form the launch site of bipolar transistor.Wherein, the photoresist that third time is lithographically derived covers the region at field-effect transistor place and the subregion of base.In other embodiments, it is not necessary to again make photoresist layer, it is also possible to by regulation ion implanting direction so that p-type heavy doping foreign ion tilts to inject reserved launch site, thus forms the launch site of bipolar transistor.Specifically, carry out ion implanting, in the step of the launch site forming bipolar transistor, using the previous photoresist being lithographically derived, it is only necessary to adjusting ion implanting direction, form the launch site of bipolar transistor.It is thus possible to save the making step of photoresist layer, the most cost-effective.It should be noted that in this step, it is also possible to formed and connect drain region and the metal level of base.
Step 808: form transmission region in the position corresponding to source region.
Step 809: grid region and launch site are drawn, obtains control end and the outfan of pixel cell.This step specifically comprises contact hole and is formed and insulating barrier formation.Utilize physical vapour deposition (PVD) (PVD) to deposit layer of metal, annealing at silicon chip surface, form metal silicide (i.e. insulating medium layer 8).Multilayer interconnection technique realizes the electric function of device.Multilayer interconnection metal wire top layer can be the grid of the field-effect transistor drawn, and passivated, encapsulation forms pixel device, as shown in figure 15.
It should be noted that present embodiment step 802 is well known to the skilled person to the shape photoetching related in each step of step 807 and ion injection method, the most no longer describe in detail.Should be appreciated that and the present invention is formed the concrete steps of the base of the source region of pixel, drain region, grid region and bipolar transistor, collecting zone and launch site and sequentially should not be limited with present embodiment.
Present embodiment is in terms of existing technologies, on substrate, field-effect transistor and bipolar transistor mixed structure is formed by series of steps, make it compared with CCD of the prior art or cmos imaging unit, not only there is Direct Current amplifying power, preferably noise inhibiting ability, and the imager chip of simple in construction can be manufactured, be conducive to improving image quality, reducing manufacturing cost.
The step of the most various methods divides, and is intended merely to describe clear, it is achieved time can merge into a step or some step is split, be decomposed into multiple step, as long as comprising identical logical relation, all in the protection domain of this patent；To adding inessential amendment in algorithm or in flow process or introducing inessential design, but do not change the core design of its algorithm and flow process all in the protection domain of this patent.
It is seen that, present embodiment is the embodiment of the method corresponding with the first embodiment, and present embodiment can be worked in coordination enforcement with the first embodiment.The relevant technical details mentioned in first embodiment is the most effective, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment is also applicable in the first embodiment.
Third embodiment of the present invention relates to the preparation method of the pixel cell of a kind of imageing sensor.3rd embodiment and the second embodiment are roughly the same, are in place of the main distinction: in this second embodiment, and the colelctor electrode of pixel cell is drawn from front.And in third embodiment of the invention, the colelctor electrode of semiconductor biosensor is drawn from the back side.
Specifically, carrying out ion implanting for the first time, in the step of the source region forming field-effect transistor, the source region of field-effect transistor and isolation area direct neighbor, without the reserved heavily doped region as bipolar transistor collecting zone, the colelctor electrode of bipolar transistor directly can be drawn from substrate.In addition, direct neighbor between drain region and the base of bipolar transistor of the field-effect transistor prepared in present embodiment, i.e. without separately setting isolation area between this drain region and base, remaining step is identical with the preparation method of the second embodiment, and the structure of the pixel cell prepared is as shown in figure 16.
It will be understood by those skilled in the art that the respective embodiments described above are to realize the specific embodiment of the present invention, and in actual applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (10)
1. an imageing sensor, it is characterised in that described imageing sensor comprises a plurality of pixel cells of composition array, and each pixel cell comprises a photodiode, a field-effect transistor and a bipolar transistor；
Wherein, described photodiode is connected with the source region of described field-effect transistor, and the drain region of described field-effect transistor is connected with the base of described bipolar transistor；
The control end as described pixel cell is drawn in the grid region of described field-effect transistor, and the outfan as described pixel cell is drawn in the launch site of described bipolar transistor；
Wherein, described photodiode collection light produces the signal of telecommunication, and the described signal of telecommunication is amplified further by the combination of described field-effect transistor and described bipolar transistor and exports afterwards.
Imageing sensor the most according to claim 1, it is characterized in that, described pixel cell comprises substrate, it is formed at the epitaxial layer collecting zone as described bipolar transistor of described substrate, the base of the source region of field-effect transistor, drain region and the bipolar transistor that are formed in described epitaxial layer and launch site, it is formed at the gate oxide between the source region of field-effect transistor, drain region on described epitaxial layer, is formed at the grid region of field-effect transistor on described gate oxide；
Wherein, the grid region of described field effect field-effect transistor, and the launch site extraction of described bipolar transistor, as control end and the outfan of described pixel cell；
The source region region of described pixel cell scene effect field-effect transistor is transmission region, and the source region of described field effect field-effect transistor is used for collecting light by described transmission region as described photodiode.
Imageing sensor the most according to claim 2, it is characterised in that the drain region of described field-effect transistor and the base of described bipolar transistor are adjacent.
Imageing sensor the most according to claim 2, it is characterised in that there is isolation area, described drain region and described base by being formed at the layer metal interconnection on described epitaxial layer between drain region and the base of described bipolar transistor of described field-effect transistor.
Imageing sensor the most according to claim 1, it is characterised in that described imageing sensor also comprises row select line, column selection line and sense amplifier；
The control end of the pixel cell being positioned at same a line in array is connected to same row select line；
The outfan of the pixel cell being positioned at same string in array is connected to same column selection line；
Described column selection line connects described sense amplifier.
Imageing sensor the most according to claim 1, it is characterised in that described imageing sensor also comprises an output lead and the sense amplifier being connected with institute rheme output lead；
Described imageing sensor is also correspondingly arranged on a reset transistor at each pixel cell, transistor and a row gating transistor are followed in a source；
The grid that the outfan of described pixel cell follows transistor with the source electrode of described reset transistor and described source is connected；
The source electrode of source electrode and described row gating transistor that transistor is followed in described source is connected；
The drain electrode of described reset transistor and described source are followed the drain electrode of transistor and are connected power supply；
The grid of the grid of described reset transistor and described row gating transistor connects reset signal and row gating signal respectively；
The drain electrode of described row gating transistor connects position output lead.
7. the preparation method of an image sensor pixel cells, it is characterised in that comprise the steps of
One highly doped substrate is provided；
Lightly doped epitaxial layer is grown, as the collecting zone of bipolar transistor in substrate；
On described epitaxial layer, form gate oxide, and on described gate oxide, form the grid region of field-effect transistor；
On epitaxial layer, carry out photoetching for the first time, output window, carry out ion implanting for the first time, form the source region of field-effect transistor；Wherein, the photoresist being lithographically derived for the first time at least covers the reserved region making bipolar transistor；
On epitaxial layer, carry out second time photoetching, output window, carry out second time ion implanting, form the drain region of field-effect transistor；Wherein, the photoresist that second time is lithographically derived at least covers the reserved region making bipolar transistor；
On epitaxial layer, carry out third time photoetching, output window, carry out third time ion implanting, form the base of bipolar transistor；Wherein, the photoresist that third time is lithographically derived at least covers the region at field-effect transistor place；
Carry out the 4th secondary ion to inject, form the launch site of bipolar transistor；
Transmission region is formed in the position corresponding to described source region；
Described grid region and described launch site are drawn, obtains control end and the outfan of pixel cell.
The preparation method of image sensor pixel cells the most according to claim 7, it is characterized in that, inject at described the 4th secondary ion that carries out, in the step of the launch site forming bipolar transistor, use the photoresist that third time is lithographically derived, adjust ion implanting direction, form the launch site of described bipolar transistor.
The preparation method of image sensor pixel cells the most according to claim 7, it is characterized in that, inject at described the 4th secondary ion that carries out, in the step of the launch site forming bipolar transistor, four mask is carried out on epitaxial layer, output window, carry out the 4th secondary ion and inject, form the launch site of bipolar transistor；Wherein, the photoresist that four mask obtains covers the region at field-effect transistor place and the subregion of base.
The preparation method of image sensor pixel cells the most according to claim 7, it is characterised in that after the step of substrate growth lightly doped epitaxial layer, also comprise the steps of
Forming isolation area at described epitaxial layer, one of them isolation area is for isolating the drain region of described field-effect transistor and the base of described bipolar transistor；
After forming the step of launch site of bipolar transistor, on described epitaxial layer, corresponding to being used for the position in the drain region isolating described field-effect transistor and the isolation area of the base of described bipolar transistor, formed and connect described drain region and the metal level of described base.
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