CN105826177A - Formation method of semiconductor device - Google Patents
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- CN105826177A CN105826177A CN201510006064.7A CN201510006064A CN105826177A CN 105826177 A CN105826177 A CN 105826177A CN 201510006064 A CN201510006064 A CN 201510006064A CN 105826177 A CN105826177 A CN 105826177A
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Abstract
The invention relates to a formation method of a semiconductor device. The formation method comprises the steps of providing a substrate which comprises a first region, a second region and a third region, wherein the substrate in the first region is provided with a first pseudo gate, the substrate in the second region is provided with a second metal gate, and the surface of the substrate in the first region and the second region is provided with an interlayer dielectric layer, converting partial thickness of the second metal gate into a nitrided metal protection layer, forming an initial gallium nitride layer on the substrate in the third region, the surface of the first pseudo gate, the surface of the nitrided metal protection layer and the surface of the interlayer dielectric layer, etching the initial gallium nitride layer by adopting a dry etching process so as to form a gallium nitride layer located at the substrate in the third region, etching the first pseudo gate by taking the gallium nitride layer as a mask so as to form a first opening in the interlayer dielectric layer in the first region, and forming a first metal gate which fully fills the first opening. During the process of forming the semiconductor device, the second metal gate always protected by the nitrided metal protection layer, so that the formed semiconductor device is good in electrical performance.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, particularly to the forming method of a kind of semiconductor device.
Background technology
At present, in the manufacturing process of semiconductor device, P-type mos (PMOS, PtypeMetalOxideSemiconductor) pipe, N-type metal-oxide semiconductor (MOS) (NMOS, NtypeMetalOxideSemiconductor) pipe or CMOS complementary metal-oxide-semiconductor (CMOS, the ComplementaryMetalOxideSemiconductor) pipe that collectively formed by PMOS and NMOS tube are the main devices constituting chip.
Along with the development of production of integrated circuits technology, semiconductor device art node constantly reduces, and the physical dimension of device is followed Moore's Law and constantly reduced.When device size is reduced to a certain degree, various because the second-order effect that the physics limit of device is brought occurs in succession, the characteristic size of device is scaled becomes more and more difficult.Wherein, in field of semiconductor fabrication, the most challenging is how to solve the problem that device creepage is big.The leakage current of device is big, is mainly constantly reduced caused by tradition gate dielectric layer thickness.The current solution that proposes is, uses high-k gate dielectric material to replace traditional silicon dioxide gate dielectric material, and use metal as gate electrode, to avoid high-g value and conventional gate electrodes material generation fermi level pinning effect and boron osmotic effect.The introducing of high-k/metal gate, reduces the leakage current of device.
But, although the high-k/metal gate technique introduced, the electric property of the semiconductor device that prior art is formed still has much room for improvement.
Summary of the invention
When the problem that the present invention solves is to form the first metal gates after prior art is previously formed the second metal gates, the second metal gate being initially formed easily is corroded or by etching injury, the overall performance causing semiconductor device is low.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor device, including: provide and include first area, second area and the substrate in the 3rd region, the first pseudo-grid it are formed with on the part of substrate of described first area, it is formed with the second metal gates on described second area part of substrate, described first area and second area substrate surface are formed with interlayer dielectric layer, and described interlayer dielectric layer is also covered in the first pseudo-grid sidewall surfaces and the second metal gates sidewall surfaces；Described second metal gates surface is carried out nitrogen treatment, the second metal gates of segment thickness is converted into nitridation coat of metal；On described 3rd substrate areas, the first pseudo-grid surface, nitridation coat of metal surface and interlayer dielectric layer surface form initial gallium nitride layer；Use dry etch process to etch described initial gallium nitride layer, expose the first pseudo-grid surface and nitridation coat of metal surface, formed and be positioned at the gallium nitride layer on the 3rd substrate areas；With described gallium nitride layer as mask, etching removes the described first pseudo-grid, forms the first opening in the interlayer dielectric layer of described first area；Form the first metal gates filling full described first opening.
Optionally, the etching gas of described dry etch process includes Cl2；Described dry etch process is more than or equal to 10 to the etching selection ratio of initial gallium nitride layer with nitridation coat of metal.
Optionally, described dry etch process is inductively coupled plasma etching.
Optionally, the technological parameter of described inductively coupled plasma etching technique is: providing source power is 100 watts to 1100 watts, and direct current biasing power is 10V to 50V, and etching cavity pressure is 1 millitorr to 20 millitorrs, Cl2Flow is 10sccm to 30sccm, and being also passed through Ar, Ar flow in etching cavity is 0sccm to 15sccm.
Optionally, described etching technics more than or equal to 10 and is less than or equal to 40 to the etching selection ratio of initial gallium nitride layer with nitridation coat of metal.
Optionally, chemical gaseous phase deposition, physical vapour deposition (PVD) or atom layer deposition process is used to form described initial gallium nitride layer.
Optionally, the technological parameter using chemical vapor deposition method to form described initial gallium nitride layer is: providing gallium source and nitrogen source, wherein, gallium source is (C2H5)3Ga、(CH3)3Ga or (C4H9)3Ga, nitrogen source is NH3, reaction chamber temperature is 600 degrees Celsius to 1000 degrees Celsius.
Optionally, the thickness of described initial gallium nitride layer is 50 angstroms to 500 angstroms.
Optionally, N is used2O and NH3Carry out described nitrogen treatment；The treatment temperature of described nitrogen treatment is 300 degrees Celsius to 1000 degrees Celsius.
Optionally, the thickness of described nitridation coat of metal is 10 angstroms to 100 angstroms.
Optionally, described second metal gates includes: the second work-function layer and be positioned at the second metallic object layer on the second work-function layer surface, and described second metallic object layer flushes with second area interlayer dielectric layer top.
Optionally, the method that the second metal gates of described segment thickness is converted into nitridation coat of metal is: the second metallic object layer of segment thickness is converted into nitridation coat of metal.
Optionally, the material of described second metallic object layer includes copper, aluminum or tungsten.
Optionally, when the material of described second metallic object layer is aluminum, the material of described nitridation coat of metal is aluminium nitride.
Optionally, before being formed after described first opening, forming described first metal gates, further comprise the steps of: employing CF4Gas performs etching post processing to the first opening.
Optionally, the technological parameter of described etching post processing is: reaction chamber pressure is that 0.2 torr is to 1 torr, it is provided that RF source power is 50 watts to 200 watts, is also passed through Ar, wherein, Ar and CF in reaction chamber4Gas flow ratio be 0 to 0.3, during technique a length of 10 seconds to 600 seconds.
Optionally, described first metal gates includes: be positioned at the first work-function layer of the first open bottom and sidewall surfaces；It is positioned at the first work-function layer surface and fills the first metallic object layer of full described first opening, and described first metallic object layer top flushes with interlayer dielectric layer top, first area.
Optionally, it is formed with first grid dielectric layer between described first metal gates and substrate；It is formed with second gate dielectric layer between described second metal gates and substrate.
Optionally, described first area is NMOS area or PMOS area；Described second area is NMOS area or PMOS area, and described first area is different from the area type of second area.
Compared with prior art, technical scheme has the advantage that
In the technical scheme of the method for forming semiconductor devices that the present invention provides, first area part of substrate is formed the first pseudo-grid, second area part of substrate is formed the second metal gates；Then the second metal gates surface is carried out nitrogen treatment; second metal gates of segment thickness is converted into nitridation coat of metal; the nitridation coat of metal formed can play the effect of protection the second metal gates, prevents the second metal gates to be corroded or sustain damage；Then, initial gallium nitride layer is formed on the first pseudo-grid surface, nitridation coat of metal surface, interlayer dielectric layer surface；nullThen，Dry etching is used to etch initial gallium nitride layer，Expose the first pseudo-grid surface and nitridation coat of metal surface，Formed and be positioned at the gallium nitride layer on the 3rd substrate areas，For identical compared to the thickness nitrogenizing coat of metal after traditional titanium nitride layer and nitrogen treatment，In the present invention, dry etch process is big to the etching selection ratio between initial gallium nitride layer and nitridation coat of metal，And dry etch process is little to the etching selection ratio between titanium nitride layer and nitridation coat of metal，Therefore in the present invention during etching initial gallium nitride layer formation gallium nitride layer，The amount of the nitrided metal layer consumed is less，Make in the present embodiment being formed after gallium nitride layer，Still there is the nitridation metal nitride layer of adequate thickness on second metal gates surface，The second metal gates is prevented to be exposed in described dry etch process，The second metal gates is avoided to be corroded.
Simultaneously; compared with being mask with traditional titanium nitride layer; time in the present invention with gallium nitride layer for mask etching removal the first pseudo-grid; the thickness of the nitridation coat of metal being positioned at the second metal gates surface is thicker; it is removed it can be avoided that nitrogenize coat of metal during etching forms the first pseudo-grid, it is to avoid the second metal gates is exposed to etch in the etching environment of the second pseudo-grid.Therefore, the present invention can improve the performance of the second metal gates, thus improves the electric property of the semiconductor device of formation.
Further, in the present invention, dry etch process is more than or equal to 10 to the etching selection ratio of initial gallium nitride layer with nitridation coat of metal so that during etching forms gallium nitride layer, and nitridation coat of metal is etched hardly.
Further; the present invention use inductively coupled plasma etching technique initial gallium nitride layer is performed etching; and the technological parameter of three-dimensional etching technics is waited by changing inductive so that dry etch process has higher etching selection ratio between initial gallium nitride layer and nitridation coat of metal.Concrete, the technological parameter of inductively coupled plasma etching technique is: providing source power is 100 watts to 1100 watts, and direct current biasing power is 10V to 50V, and etching cavity pressure is 1 millitorr to 20 millitorrs, Cl2Flow is 10sccm to 30sccm, and being also passed through Ar, Ar flow in etching cavity is 0sccm to 15sccm.
Further, after etching forms the first opening, use CF4Gas performs etching post processing to the first opening, and etching removes the etch by-products being positioned at the first opening.Simultaneously; the present invention it also avoid etching post processing nitridation coat of metal is caused too much etching; make to etch post processing the least to the etch rate of nitridation coat of metal; thus avoid the second metal gates to be exposed; make the second metal gates obtain preferably protection, improve the electric property of semiconductor device further.Concrete, the technological parameter etching post processing in the present invention is: reaction chamber pressure is that 0.2 torr is to 1 torr, it is provided that RF source power is 50 watts to 200 watts, is also passed through Ar, wherein, Ar and CF in reaction chamber4Gas flow ratio be 0 to 0.3, during technique a length of 10 seconds to 600 seconds.
Accompanying drawing explanation
The cross-sectional view of the semiconductor device forming process that Fig. 1 to Fig. 4 provides for an embodiment；
The cross-sectional view of the semiconductor device forming process that Fig. 5 to Figure 12 provides for another embodiment of the present invention.
Detailed description of the invention
From background technology, the electric property of the semiconductor device that prior art is formed has much room for improvement.
It has been investigated that, in order to meet NMOS tube and the requirement of PMOS improvement threshold voltage (ThresholdVoltage) simultaneously, generally use different metal materials as work function (WF in the metal gates of NMOS tube and PMOS, WorkFunction) layer material, therefore the metal gates of NMOS tube and PMOS is successively to be formed, rather than concurrently forms NMOS tube and PMOS metal gates.
In one embodiment, with reference to Fig. 1, it is provided that substrate 100, described substrate 100 includes PMOS area, NMOS area and other device areas；The first pseudo-grid 111 it are formed with in described NMOS area substrate 100, the second pseudo-grid 121 it are formed with in described PMOS area substrate 100, it is formed with interlayer dielectric layer 101 in described PMOS area, NMOS area and other device area substrates 100, and described interlayer dielectric layer 101 is covered in the first pseudo-grid 111 sidewall and the second pseudo-grid 121 sidewall.
With reference to Fig. 2, etching removes the described first pseudo-grid 111, forms the first opening in NMOS area interlayer dielectric layer 101；Form the first metal gates 112 filling full described first opening, and described first metal gate material has the first work function.
With reference to Fig. 3, form the initial hard mask layer 102 being covered in pseudo-grid 121 surface of interlayer dielectric layer 101 surface, the first metal gates 112 surface and second；
With reference to Fig. 4, etching described initial hard mask layer 102 (with reference to Fig. 3) and form the hard mask layer 103 being covered in other device area interlayer dielectric layer 101 surfaces, described hard mask layer 103 exposes the first pseudo-grid 121 of metal gates 112, second and interlayer dielectric layer 101 surface of NMOS area and PMOS area.
Then, with described hard mask layer 103 as mask, etching removes the second pseudo-grid 121, formation the second opening described PMOS area interlayer dielectric layer 101 in；Form the second metal gates filling full described second opening, and described second metal gate material has the second work function.
Use said method, it is possible to make PMOS different with the work function of the metal gates of NMOS tube, meet the requirement to metal gates work function of PMOS and NMOS tube respectively.But, use in the semiconductor device that said method is formed, the degraded performance of NMOS tube thus cause the electric property of semiconductor device overall low.
The material of the first metal gates 112 includes copper, aluminum or tungsten.Such as, the material of the first metal gates 112 can include that the material on the first metal gates 112 surface that aluminum, corresponding hard mask layer 103 exposes is aluminum.Along with semiconductor structure size constantly reduces, the problem that figure that is that occur caves in order to the thickness preventing initial hard mask layer 102 is blocked up, use metal material as initial hard mask layer 102 material, conventional initial hard mask layer 102 material is TiN；And the etching gas etching initial hard mask layer 102 includes Cl2, during etching initial hard mask layer 102, the first metal gates 112 surface can be exposed, therefore Cl2Enter in the first metal gates 112.Due to Cl2With aluminum, electrochemical reaction can occur, and then cause the first metal gates 112 to corrode, the electric property causing NMOS tube is low.
In order to avoid the problems referred to above; before forming initial hard mask layer 102; first metal gates 112 is carried out nitrogen treatment; first metal gates 112 of segment thickness is converted into nitridation coat of metal; such as; when first metal gates 112 surfacing is aluminum, the material of described nitridation coat of metal is aluminium nitride.Described nitridation coat of metal can stop Cl2Enter in the first metal gates 112, thus prevent the first metal gates 112 to be corroded.
But; further study show that; etch initial hard mask layer 102 when forming hard mask layer 103; described etching technics is low to the etching selection ratio between initial hard mask layer 102 and nitridation coat of metal; therefore during etching forms hard mask layer 103; substantial amounts of nitridation coat of metal is etched removal, the first metal gates 112 even can be caused to be exposed to etch in the environment of initial hard mask layer 102 so that the first metal gates 112 is corroded.
Even if after forming hard mask layer 103, the first metal gates 112 surface is still covered by nitridation coat of metal, but compared with before formation hard mask layer 103, the thickness of nitridation coat of metal seriously reduces.When etching removes the second pseudo-grid 121; nitridation coat of metal is exposed to etch in environment; and owing to the thickness of nitridation coat of metal is the thinnest; make to nitrogenize coat of metal to be easily etched; the first metal gates 112 is caused to be exposed to etch in the etching environment of the second pseudo-grid 121; cause the first metal gates 112 by etching injury, affect the electric property of NMOS tube.
As the above analysis, if etching technics can improve to the etching selection ratio between initial hard mask layer and nitridation coat of metal, then can reduce the thickness of the nitridation coat of metal of loss, prevent the first metal gates to be exposed to etch in environment.
For this, the embodiment of the present invention also provides for the forming method of a kind of semiconductor device, there is provided and include first area, second area and the substrate in the 3rd region, the first pseudo-grid it are formed with on the part of substrate of described first area, it is formed with the second metal gates on described second area part of substrate, described first area and second area substrate surface are formed with interlayer dielectric layer, and described interlayer dielectric layer is also covered in the first pseudo-grid sidewall surfaces and the second metal gates sidewall surfaces；Described second metal gates surface is carried out nitrogen treatment, the second metal gates of segment thickness is converted into nitridation coat of metal；On described 3rd substrate areas, the first pseudo-grid surface, nitridation coat of metal surface and interlayer dielectric layer surface form initial gallium nitride layer；Dry etch process is used to etch described initial gallium nitride layer; formed and be positioned at the gallium nitride layer on the 3rd substrate areas; described gallium nitride layer exposes the first pseudo-grid surface, nitridation coat of metal surface and first area and second area interlayer dielectric layer surface, and described etching technics is more than or equal to 10 to the etching selection ratio of initial gallium nitride layer with nitridation coat of metal；With described gallium nitride layer as mask, etching removes the described first pseudo-grid, forms the first opening in the interlayer dielectric layer of described first area；Form the first metal gates filling full described first opening.The present invention is compared with before formation gallium nitride layer; the thickness of the nitridation coat of metal after forming gallium nitride layer is kept approximately constant; hence in so that nitridation coat of metal can play the effect of enough protection the second metal gates; prevent the second metal gates from sustaining damage, and then improve electric property and the reliability of semiconductor device.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
The cross-sectional view of the semiconductor device forming process that Fig. 5 to Figure 12 provides for another embodiment of the present invention.
With reference to Fig. 5, substrate 200 is provided, described substrate 200 includes first area I, second area II and the 3rd region III, the first pseudo-grid 212 it are formed with on described first area I part of substrate 200, the second pseudo-grid 222 it are formed with on described second area II part of substrate 100, described first area I and second area II substrate 200 surface are formed with interlayer dielectric layer 201, and described interlayer dielectric layer 201 is also covered in the first pseudo-grid 212 sidewall surfaces and the sidewall surfaces of the second pseudo-grid 222.
The material of described substrate 200 is silicon, germanium, SiGe, GaAs, carborundum or gallium indium；Described substrate 200 can also be the silicon substrate on insulator or the germanium substrate on insulator.In the present embodiment, the material of described substrate 200 is silicon.
Described first area I is NMOS area or PMOS area, and described second area II is NMOS area or PMOS area；Described first area I and second area I can be adjacent or interval.Described first area I is different with the area type of second area II, and when described first area I is NMOS area, described second area II is PMOS area, and when described first area I is PMOS area, described second area II is NMOS area.In an embodiment of the present invention, with described first area I as NMOS area, second area II is that PMOS area is done exemplary illustrated, follow-up in NMOS area formation NMOS tube, forms PMOS in PMOS area.
Described 3rd region III is to be formed with the region of other devices or for the region of other devices to be formed, other devices described refer to NMOS tube or the PMOS that non-the present embodiment is formed.The present embodiment is covered as example using the 3rd III substrate 200 surface, region by interlayer dielectric layer 201.
Can also be formed with fleet plough groove isolation structure in described substrate 200, the packing material of described fleet plough groove isolation structure is silicon oxide, silicon nitride or silicon oxynitride.
The material of the described first pseudo-grid 212 is polysilicon, silicon nitride or amorphous carbon；The material of the described second pseudo-grid 222 is polysilicon, silicon nitride or amorphous carbon.In the present embodiment, the material of the described first pseudo-grid 212 is polysilicon, and the material of the second pseudo-grid 222 is polysilicon.
In the present embodiment, it is also formed with first grid dielectric layer 211 between first pseudo-grid 212 and substrate 200, it is also formed with second gate dielectric layer 221 between second pseudo-grid 222 and substrate 200, wherein, the material of first grid dielectric layer 211 and second gate dielectric layer 221 is high-k gate dielectric material, and high-k gate dielectric material refers to the relative dielectric constant gate dielectric material more than silicon oxide relative dielectric constant, such as, high-k gate dielectric material can be HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
In order to prevent the technique of the pseudo-grid 212 of subsequent etching first from first grid dielectric layer 211 is caused damage, etching barrier layer can also be formed between first grid dielectric layer 211 and the first pseudo-grid 212, same forms etching stop layer between second gate dielectric layer 221 and the second pseudo-grid 222, and the material of described etching stop layer can be TiN or TaN.
In other embodiments, described first grid dielectric layer and second gate dielectric layer can also be pseudo-gate dielectric layer, and follow-up etching while etching removes the first pseudo-grid removes first grid dielectric layer, etches and remove second gate dielectric layer while etching removes the second pseudo-grid；Then, before forming the first metal gates, re-form the first high-k gate dielectric layer, before forming the second metal gates, re-form the second high-k gate dielectric layer.
In the present embodiment, the material of described interlayer dielectric layer 201 is silicon oxide, and the material of interlayer dielectric layer 201 can also be silicon nitride or silicon oxynitride.The described pseudo-grid 212 of interlayer dielectric layer 201, first flush with the second pseudo-grid 222 top surface.
In a specific embodiment, the processing step forming the pseudo-grid 212 of first grid dielectric layer 211, first, the pseudo-grid 222 of second gate dielectric layer 221, second and interlayer dielectric layer 201 includes: forms gate dielectric film on described substrate 200 surface and is positioned at the pseudo-grid film on gate dielectric film surface；Graphical dummy gate film, form the first grid dielectric layer 211 being positioned at I part of substrate 200 surface, first area and the first pseudo-grid 212 being positioned at first grid dielectric layer 211 surface, form the second gate dielectric layer 221 being positioned at second area II part of substrate 200 surface and the second pseudo-grid 222 being positioned at second gate dielectric layer 221 surface；Then, forming interlayer dielectric layer 201 at first area I, second area II and the 3rd III substrate 200 surface, region, described interlayer dielectric layer 201 is covered in the first pseudo-grid 212 sidewall surfaces and the second pseudo-grid 222 sidewall surfaces；Planarize described interlayer dielectric layer 201, until interlayer dielectric layer 201 top flushes with the first pseudo-pseudo-grid 222 top of grid 212, second.
With reference to Fig. 6, etching removes the described second pseudo-grid 222 (with reference to Fig. 5), forms the second opening in second area II interlayer dielectric layer 201；Form the second metal gates filling full described second opening.
Using dry etch process etching to remove the described second pseudo-grid 222, the etching gas of dry etch process includes CF4、HBr、Cl2、HCl、O2、CHF3、NF3Or SF6In one or more.
In the present embodiment, etching is removed the technological parameter of the second pseudo-grid 222 and is: etching gas is HBr, O2And Cl2, in etching cavity, also it being passed through He, etching cavity pressure is 2 millitorrs to 50 millitorrs, and the source power of etching is 200 watts to 2000 watts, and etching biasing power is 10 watts to 100 watts, and HBr flow is 50sccm to 500sccm, O2Flow is 2sccm to 20sccm, Cl2Flow is 10sccm to 300sccm, and He flow is 50sccm to 500sccm.
In order to improve the work function driveability with raising PMOS of the second metal gates, described second metal gates includes: is positioned at the second open bottom and the second work-function layer 223 of sidewall surfaces, is positioned at the second work-function layer 223 surface and fills the second metallic object layer 224 of full second opening.Described second metallic object layer 224 top flushes with second area II interlayer dielectric layer 201 surface.
Wherein, the material work functions scope of the second work-function layer 223 is 5.1ev to 5.5ev, such as, 5.2ev, 5.3ev or 5.4ev.The material of the second work-function layer 223 is one or more in TiN, TaN, TaSiN, TiSiN, TaAlN or TiAlN；The material of described second metallic object layer 224 is Al, Cu, Ag, Au, Pt, Ni, Ti or W.
In the present embodiment, the material of the second work-function layer 223 is TiN, and the material of the second metallic object layer 224 is Al.Second gate dielectric layer 221 it is also formed with between second metal gates and substrate 200.
With reference to Fig. 7, described second metal gates surface is carried out nitrogen treatment, the second metal gates of segment thickness is converted into nitridation coat of metal 225.
In the present embodiment, the second metallic object layer 224 of segment thickness in the second metal gates is converted into nitridation coat of metal 225.
Rear extended meeting forms the initial gallium nitride layer being covered in the second metallic object layer 224 surface, then dry etch process etching is used to remove the initial gallium nitride layer being positioned at the second metallic object layer 224 surface, forming the gallium nitride layer being positioned at the 3rd region III, the etching gas of described dry etching includes Cl2；After etching initial gallium nitride layer, the second metallic object layer 224 surface will be exposed to etch in environment so that Cl2Enter in the second metallic object layer 224, cause in the second metallic object layer 224 and generation electrochemical reaction is corroded.
To this end, the present embodiment forms nitridation coat of metal 225 on the second metallic object layer 224 surface, described nitridation coat of metal 225 can stop Cl2Enter in the second metallic object layer 224, thus prevent the second metallic object layer 224 to be corroded.
When the material of the second metallic object layer 224 is copper, the material of the nitridation coat of metal 225 of formation is copper nitride.In the present embodiment, the material of the second metallic object layer 224 is aluminum, and the material of the nitridation coat of metal 225 of formation is aluminium nitride.
Use N2O and NH3Carry out described nitrogen treatment.In the present embodiment, the treatment temperature of described nitrogen treatment is 300 degrees Celsius to 1000 degrees Celsius, for example, 500 degrees Celsius, 600 degrees Celsius or 800 degrees Celsius.
If the thickness of the nitridation coat of metal 225 formed is the thinnest, then in follow-up etching process, nitrogenizes coat of metal 225 be easily etched removals, do not have the effect protecting the second metallic object layer 224；If the thickness of the nitridation coat of metal 225 formed is blocked up, then the thickness remaining the second metallic object layer 224 is the thinnest, causes the degradation of the second metal gates.
To this end, the thickness of the nitridation coat of metal 225 formed in the present embodiment is 10 angstroms to 100 angstroms.
With reference to Fig. 8, in described 3rd region III substrate 200, the first pseudo-grid 212 surface, nitridation coat of metal 225 surface and interlayer dielectric layer 201 surface form initial gallium nitride layer 202.
In the present embodiment, the 3rd region III substrate 200 is covered by interlayer dielectric layer 201, and therefore the initial gallium nitride layer 202 of the 3rd region III is positioned at interlayer dielectric layer 201 surface of the 3rd region III.
Follow-up employing dry etch process; etching removes the initial gallium nitride layer 202 being positioned at first area I and second area II; expose the first pseudo-grid 212 and the second metal gates surface; formed and be positioned at the gallium nitride layer in the 3rd region III substrate 200; the gallium nitride layer formed is used as subsequent etching and removes the mask of the first pseudo-grid 212, and plays the effect of protection the 3rd region III.
Owing to the etching selection between initial gallium nitride layer 202 with nitridation coat of metal 225 is compared high by dry etch process, while etching removal is positioned at the initial gallium nitride layer 202 on nitridation coat of metal 225 surface, it can be avoided that nitridation coat of metal 225 is caused etching by described dry etch process, make follow-up during etching initial gallium nitride layer 202, the thickness of nitridation coat of metal 225 keeps constant, thus prevent nitrogenizing coat of metal 225 and be etched, the second metallic object layer 224 is avoided to be exposed in etching environment, the second metallic object layer 224 is avoided to be corroded.
Prior art generally uses titanium nitride layer to remove the material of the first pseudo-grid as etching.First; formed and be covered in nitridation coat of metal and the initial titanium nitride layer on interlayer dielectric layer surface; then use dry etch process etching to remove and be positioned at nitridation coat of metal surface and the initial titanium nitride layer on the first pseudo-grid surface, form the titanium nitride layer being positioned at the 3rd region.But; owing to dry etch process is relatively low to the etching selection ratio between titanium nitride layer and nitridation coat of metal; therefore during etching forms titanium nitride layer; described dry etch process etches removal nitridation coat of metal the most completely; make the second metallic object layer be exposed to etch in environment, cause the second metallic object layer to corrode；Or; the nitridation metal coating layer thickness that described dry etch process etching is removed is blocked up; therefore during the pseudo-grid of subsequent etching first; remaining nitridation coat of metal is the most easily etched removal; cause the second metallic object layer to be exposed to etch in the etching environment of the first pseudo-grid, and then also the second metallic object layer can be caused damage.
Chemical gaseous phase deposition, physical vapour deposition (PVD) or atom layer deposition process is used to form described initial gallium nitride layer.In the present embodiment, the technological parameter using chemical vapor deposition method to form described initial gallium nitride layer is: providing gallium source and nitrogen source, wherein, gallium source is (C2H5)3Ga、(CH3)3Ga or (C4H9)3Ga, nitrogen source is NH3, reaction chamber temperature is 600 degrees Celsius to 1000 degrees Celsius.
If the thickness of initial gallium nitride layer 202 is the thinnest, follow-up during the pseudo-grid 212 of etching removal first, the first pseudo-grid 212 have not been disappeared by gallium nitride layer during all etching removals；If the thickness of initial gallium nitride layer 202 is blocked up, then the overlong time needed for the initial gallium nitride layer of subsequent etching 202.
To this end, the thickness of initial gallium nitride layer 202 is 50 angstroms to 500 angstroms described in the present embodiment.
With reference to Fig. 9; use the described initial gallium nitride layer 202 (with reference to Fig. 8) of dry etch process etching; being formed and be positioned at the gallium nitride layer 203 in the 3rd region III substrate 200, described gallium nitride layer 203 exposes the first pseudo-grid 212 surface, nitridation coat of metal 225 surface and first area I and second area II interlayer dielectric layer 201 surface.
The present embodiment is formed with interlayer dielectric layer 201 due to the 3rd III substrate 200 surface, region, then the gallium nitride layer 203 formed after etching is positioned at the 3rd III interlayer dielectric layer 201 surface, region.
Concrete, form patterned photoresist layer 204 on initial gallium nitride layer 202 surface；With described patterned photoresist layer 204 as mask; etching is removed and is positioned at the first pseudo-grid 212 surface, nitridation coat of metal 225 surface and first area I and the initial gallium nitride layer 202 on second area II interlayer dielectric layer 201 surface, forms the gallium nitride layer 203 being positioned at the 3rd III interlayer dielectric layer 201 surface, region.
The etching gas of described dry etch process includes Cl2.And; dry etch process described in the present embodiment is more than or equal to 10 to the etching selection ratio between initial gallium nitride layer 202 and nitridation coat of metal 225; therefore after described nitridation coat of metal 225 surface is exposed; described dry etch process is even negligible the etch rate nitrogenizing coat of metal 225 is the least; make compared with before dry etching; the thickness of the nitrided metal layer 225 after dry etching is kept approximately constant, thus avoids the second metallic object layer 224 surface to be exposed in dry etching environment.
Simultaneously; due to after forming gallium nitride layer 203; second metallic object layer 224 surface still has the nitridation coat of metal 225 of adequate thickness; thus avoid nitrogenizing coat of metal 225 during the pseudo-grid 212 of subsequent etching first and be etched removals, it is to avoid the second metallic object layer 224 is exposed to etch in the first puppet grid 212 environment.
In the present embodiment, described etching technics more than or equal to 10 and is less than or equal to 40 to the etching selection ratio of initial gallium nitride layer 202 with nitridation coat of metal 225；Described dry etch process is that (ICP, (InductiveCouplingPlasma) etches inductively coupled plasma.
In inductive sensing etching process, except providing Cl2Outward, DC offset voltage, the source power forming inductively coupled plasma and etching cavity pressure are also provided for.
It has been investigated that, if Cl2Flow is excessive, then dry etch process will be bigger to the etch rate of nitridation coat of metal 225.To this end, Cl in the present embodiment2Flow is 10sccm to 30sccm, for example, 15sccm, 20sccm or 25sccm.
The density of Cl plasma increases along with the increase of source power; thus enhance ion physical sputtering and the reaction rate of etching surface; so that the etch rate of initial gallium nitride layer 202 and nitridation coat of metal 225 is accelerated by etching technics; and the degree of the initially etch rate quickening of gallium nitride layer 202 is more greatly, improve etching technics to initial gallium nitride layer 202 and the etching selection ratio nitrogenizing coat of metal 202；When source power becomes excessive, the degree that the etch rate of nitridation coat of metal 225 is accelerated also can become the biggest, and therefore the etching selection ratio of initial gallium nitride layer 202 with nitridation coat of metal 225 is reduced by etching technics.To this end, in the present embodiment, source power is 100 watts to 1100 watts, for example, 300 watts, 500 watts, 800 watts or 1000 watts.
When DC offset voltage is less than or equal to 20V; owing to the increase of bias voltage creates the Cl plasma that more orientation is accelerated; so that the etch rate of initial gallium nitride layer 202 is increased by etching technics, improve the etching technics etching selection ratio to initial gallium nitride layer 202 with nitridation coat of metal 225；And after DC offset voltage is more than 20V; owing to the energy of Cl plasma is excessive; initial gallium nitride layer 202 not being performed etching by Cl plasma the most adsorbed, therefore the etching selection ratio of initial gallium nitride layer 202 with nitridation coat of metal 225 is reduced by etching technics.To this end, in the present embodiment, DC offset voltage is 10V to 50V, for example, 15V, 20V, 30V or 40V.
In a specific embodiment, the technological parameter of described inductively coupled plasma etching technique is: providing source power is 100 watts to 1100 watts, and direct current biasing power is 10V to 50V, and etching cavity pressure is 1 millitorr to 20 millitorrs, Cl2Flow is 10sccm to 30sccm, it is also possible to being passed through Ar, Ar flow in etching cavity is 0sccm to 15sccm.
After forming described gallium nitride layer 203, remove patterned photoresist layer 204.
With reference to Figure 10, with described gallium nitride layer 203 as mask, etching removes the described first pseudo-grid 212 (with reference to Fig. 9), formation the first opening 205 described first area I interlayer dielectric layer 201 in.
Etching is removed the technique of the described first pseudo-grid 212 and is referred to the aforementioned technique etching and removing the second pseudo-grid 222, does not repeats them here.
Due to aforementioned after forming gallium nitride layer 203; second metallic object layer 224 surface still has thicker nitridation coat of metal 225; therefore during the pseudo-grid 212 of etching described first; nitridation coat of metal 225 can play the effect of protection the second metallic object layer 224; the second metallic object layer 224 is prevented to be exposed to etch in the etching environment of the first pseudo-grid 212; thus avoid described second metallic object layer 224 by etching injury so that the second metallic object layer 224 keeps higher performance.
With reference to Figure 11, use CF4Gas performs etching post processing (PET, PostEtchTreatment) to described first opening 205.
Aforementioned etching formed the first opening 205 process can form etch by-products, partial etching by-product can leave etching cavity, and also partial etching by-product can be attached to bottom the first opening 205 and sidewall surfaces under gravity.If directly form the first metal gates in the first opening 205 follow-up, then the first metal gates performance can be had undesirable effect by the etch by-products adhered to.
To this end, the present embodiment is before forming the first metal gates, the first opening 205 performing etching post processing, etching removes the etch by-products in the first opening 205.
In the etching last handling process of the present embodiment; require that post-etch treatment process is less to the etch rate of nitridation coat of metal 225; after making to process after etching; the nitridation coat of metal 225 still having thicker degree is covered in the second metallic object layer 224 surface, it is to avoid the second metallic object layer 224 is exposed in external environment.
After etching in processing procedure, in reaction chamber, provide CF4, also providing for Ar, reaction chamber has certain pressure, in addition it is also necessary to provide RF source power.
If reaction chamber pressure is too low, then etching post processing to nitridation coat of metal 225 etch rate excessive, for reaction chamber pressure in this present embodiment be 0.2 torr to 1 torr, for example, 0.4 torr, 0.6 torr are to 0.8 torr.
If the RF source power provided is too small, then to remove the ability of etch by-products in the first opening low in etching post processing；If the RF source power provided is excessive, then etching post processing becomes big the most relatively to the etch rate of nitridation coat of metal 225.To this end, providing RF source power in the present embodiment is 50 watts to 200 watts, for example, 100 watts or 150 watts.
In a specific embodiment, the technological parameter of etching post processing is: reaction chamber pressure is that 0.2 torr is to 1 torr, it is provided that RF source power is 50 watts to 200 watts, is also passed through Ar, wherein, Ar and CF in reaction chamber4Gas flow ratio be 0 to 0.3, during technique a length of 10 seconds to 600 seconds.
With reference to Figure 12, form the first metal gates filling full described first opening 205 (with reference to Figure 11).
In the present embodiment, first area I is NMOS area, and in order to improve the work function of the first metal gates of NMOS tube, described first metal gates includes: be positioned at bottom the first opening 205 and the first work-function layer 213 of sidewall surfaces；It is positioned at the first work-function layer 213 surface and fills the first metallic object layer 214 of full described first opening 205, and described first metallic object layer 214 top flushes with I interlayer dielectric layer 201 top, first area.
The material work functions scope of described first work-function layer 213 is 3.9ev to 4.5ev, for example, 4ev, 4.1ev or 4.3ev.The material of described first work-function layer 213 is TiN, Mo, MoN or AlN；The material of described first metallic object layer 214 is Al, Cu, Ag, Au, Pt, Ni or Ti.
In the present embodiment, the material of described first work-function layer 213 is MoN, and the material of the first metallic object layer 214 is Al, is formed with first grid dielectric layer 211 between the first metallic object layer 214 and substrate 200.
In a specific embodiment; the processing step forming described first metal gates includes: form the first work-function layer 213 bottom described first opening 205 with sidewall surfaces, and described first work-function layer 213 is also covered in interlayer dielectric layer 201 surface and nitridation coat of metal 225 surface；Form the first metallic object layer 214 on described first work-function layer 213 surface, described first metallic object layer 214 fills full first opening 205；Use chemical mechanical milling tech, grind and remove the first metallic object layer 214 and the first work-function layer 213 higher than I interlayer dielectric layer 201 surface, first area.
In process of lapping; owing to the second metallic object layer 224 surface is formed with nitridation coat of metal 225; described nitridation coat of metal 225 is prevented from grinding technics and the second metallic object layer 224 is caused damage, so that the second metallic object layer 224 keeps good performance.
Owing in the present embodiment, the second metallic object layer 224 is covered by nitridation coat of metal 225 all the time; the second metallic object layer 224 is avoided to be corroded or sustain damage; electric property for the PMOS of this second area II is good, so that the semiconductor device formed has good electric property.
In other embodiments, it is also possible to first etching is removed the first pseudo-grid, formed the first metal gates, then the first metal gates of segment thickness is converted into nitridation coat of metal；Then the processing step perform etching and remove the second pseudo-grid, forming the second metal gates.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (19)
1. the forming method of a semiconductor device, it is characterised in that including:
There is provided and include first area, second area and the substrate in the 3rd region, the first pseudo-grid it are formed with on the part of substrate of described first area, it is formed with the second metal gates on described second area part of substrate, described first area and second area substrate surface are formed with interlayer dielectric layer, and described interlayer dielectric layer is also covered in the first pseudo-grid sidewall surfaces and the second metal gates sidewall surfaces；
Described second metal gates surface is carried out nitrogen treatment, the second metal gates of segment thickness is converted into nitridation coat of metal；
On described 3rd substrate areas, the first pseudo-grid surface, nitridation coat of metal surface and interlayer dielectric layer surface form initial gallium nitride layer；
Use dry etch process to etch described initial gallium nitride layer, expose the first pseudo-grid surface and nitridation coat of metal surface, formed and be positioned at the gallium nitride layer on the 3rd substrate areas；
With described gallium nitride layer as mask, etching removes the described first pseudo-grid, forms the first opening in the interlayer dielectric layer of described first area；
Form the first metal gates filling full described first opening.
The forming method of semiconductor device the most according to claim 1, it is characterised in that the etching gas of described dry etch process includes Cl2；Described dry etch process is more than or equal to 10 to the etching selection ratio of initial gallium nitride layer with nitridation coat of metal.
The forming method of semiconductor device the most according to claim 2, it is characterised in that described dry etch process is inductively coupled plasma etching.
The forming method of semiconductor device the most according to claim 3, it is characterized in that, the technological parameter of described inductively coupled plasma etching technique is: providing source power is 100 watts to 1100 watts, and direct current biasing power is 10V to 50V, etching cavity pressure is 1 millitorr to 20 millitorrs, Cl2Flow is 10sccm to 30sccm, and being also passed through Ar, Ar flow in etching cavity is 0sccm to 15sccm.
The forming method of semiconductor device the most according to claim 3, it is characterised in that described etching technics more than or equal to 10 and is less than or equal to 40 to the etching selection ratio of initial gallium nitride layer with nitridation coat of metal.
The forming method of semiconductor device the most according to claim 1, it is characterised in that use chemical gaseous phase deposition, physical vapour deposition (PVD) or atom layer deposition process to form described initial gallium nitride layer.
The forming method of semiconductor device the most according to claim 6, it is characterised in that the technological parameter using chemical vapor deposition method to form described initial gallium nitride layer is: providing gallium source and nitrogen source, wherein, gallium source is (C2H5)3Ga、(CH3)3Ga or (C4H9)3Ga, nitrogen source is NH3, reaction chamber temperature is 600 degrees Celsius to 1000 degrees Celsius.
The forming method of semiconductor device the most according to claim 1, it is characterised in that the thickness of described initial gallium nitride layer is 50 angstroms to 500 angstroms.
The forming method of semiconductor device the most according to claim 1, it is characterised in that use N2O and NH3Carry out described nitrogen treatment；The treatment temperature of described nitrogen treatment is 300 degrees Celsius to 1000 degrees Celsius.
The forming method of semiconductor device the most according to claim 1, it is characterised in that the thickness of described nitridation coat of metal is 10 angstroms to 100 angstroms.
The forming method of 11. semiconductor device according to claim 1, it is characterized in that, described second metal gates includes: the second work-function layer and be positioned at the second metallic object layer on the second work-function layer surface, and described second metallic object layer flushes with second area interlayer dielectric layer top.
The forming method of 12. semiconductor device according to claim 11, it is characterised in that the method that the second metal gates of described segment thickness is converted into nitridation coat of metal is: the second metallic object layer of segment thickness is converted into nitridation coat of metal.
The forming method of 13. semiconductor device according to claim 11, it is characterised in that the material of described second metallic object layer includes copper, aluminum or tungsten.
The forming method of 14. semiconductor device according to claim 11, it is characterised in that when the material of described second metallic object layer is aluminum, the material of described nitridation coat of metal is aluminium nitride.
The forming method of 15. semiconductor device according to claim 1, it is characterised in that before being formed after described first opening, forming described first metal gates, further comprises the steps of: employing CF4Gas performs etching post processing to the first opening.
The forming method of 16. semiconductor device according to claim 15, it is characterised in that the technological parameter of described etching post processing is: reaction chamber pressure is that 0.2 torr is to 1 torr, thering is provided RF source power is 50 watts to 200 watts, in reaction chamber, also it is passed through Ar, wherein, Ar and CF4Gas flow ratio be 0 to 0.3, during technique a length of 10 seconds to 600 seconds.
The forming method of 17. semiconductor device according to claim 1, it is characterised in that described first metal gates includes: be positioned at the first work-function layer of the first open bottom and sidewall surfaces；It is positioned at the first work-function layer surface and fills the first metallic object layer of full described first opening, and described first metallic object layer top flushes with interlayer dielectric layer top, first area.
The forming method of 18. semiconductor device according to claim 1, it is characterised in that be formed with first grid dielectric layer between described first metal gates and substrate；It is formed with second gate dielectric layer between described second metal gates and substrate.
The forming method of 19. semiconductor device according to claim 1, it is characterised in that described first area is NMOS area or PMOS area；Described second area is NMOS area or PMOS area, and described first area is different from the area type of second area.
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