CN105825894B - Memory reading method and digital memory device - Google Patents
Memory reading method and digital memory device Download PDFInfo
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Abstract
The present invention provides a kind of memory reading method and digital memory device, using have be divided into the data buffer of Data buffer and cache buffer, the internal error more code related with cache buffer that user can set and Rapid Damage block management.When data read operation, error correcting code state can be as shown by error correcting code state bit.The output data that state (1:1) can represent entire multi-page includes more than the continuous read mode of 4 bit mistakes per-page, however, someone will wonder the error correcting code state of each page or each page subregion, for the former, at the end of exporting the page, judges the error correcting code state of full page and be stored in state buffer；For the latter the error correcting code state of each page subregion is judged and exported before exporting corresponding paging partition.The present invention can integrate error correcting code processing, without waiting for the time.
Description
Technical field
The present invention integrates at error correcting code about digital memory device and its operating method particularly with regard to having
The NAND gate flash memory and its operating method of reason.
Background technique
NAND gate flash memory quite receives an acclaim in data storage, because using single-layer type (single
Level cell, SLC) NAND gate flash memory memory cell dimensions it is substantially smaller so that the list of 512Mb or more
Laminar NAND gate flash memory cost in density quite have advantage.
NAND gate flash memory also becomes quite welcome in the various applications other than data storage, including code
It maps (code shadowing).Although usually used single-layer type NAND gate flash memory has framework, efficiency, data
Integrality and failure area limitation, make it be difficult to support to be suitble to the high speed code mapping of serial nor gate flash memory
Using various technologies, which are developed, enables NAND gate flash memory to be suitble to these applications.
Error correcting code (Error Correction Code, EEC) algorithm has been developed to management data integrity
The problem of.In a method, what internal error correcting code calculating was executed when page write-in, the error correction of generation
Code information is stored in 64 additional regions character group (byte) of referred to as spare area of each page.Work as reading data
When operation, error correcting code engine verify data according to previously stored error correcting code information, and in limited range
Inside carry out specified correction.Verifying and more positive status are wrong more by the first error correcting code state bit ECC-0 and second
Code state bit ECC-1, according to mode below.Second error correcting code state bit ECC-1, the first mistake are more
When the state of code state bit ECC-0 is (0:0), representing entire data output is success without any error correcting code
To correct.Second error correcting code state bit ECC-1, the first error correcting code state bit ECC-0 state be (0:1)
When, the output of entire data, which is represented, successfully, to need 1~4 bit/page error correcting code corrects single page or multiple
The page.Second error correcting code state bit ECC-1, the first error correcting code state bit ECC-0 state be (1:0) when,
Entire data output is represented only in single page including mistakes more than 4 bits, and can not be by error correcting code reparation, the number
According to unsuitable use.In continuous read mode, an additional instruction can be used to read the page of the page including the mistake
Address (Page Address, PA).Second error correcting code state bit ECC-1, the first error correcting code state bit ECC-0
State when being (1:1), represent the mistake that each page of the entire data output in multiple pages includes 4 bits or more.?
In continuous read mode, additional instruction provides the page address for having last vicious page, and other tools are vicious
The page address of the page can't be mentioned report.
Summary of the invention
The present invention provides a kind of memory reading method and digital memory device, solves the prior art and is difficult to support
The problem of being suitble to the high speed code mapping of serial nor gate flash memory to apply.
One embodiment of the invention is a kind of memory reading method, suitable for continuously reading from a digital memory device
Data, wherein above-mentioned digital memory device includes that the NAND gate flash memory array being mutually coupled and a page are slow
Device is rushed, above-mentioned page buffer is at least divided into a first part and a second part, and memory reading method includes: certainly
One first data of above-mentioned one first page of NAND gate flash memory array access；From above-mentioned first data in the above-mentioned page
One first error correcting code processing data are established in the above-mentioned first part of buffer；Judge above-mentioned first error correcting code processing
One first error correcting code state of data；Above-mentioned first error correction is exported from the above-mentioned first part of above-mentioned page buffer
Code processing data；In the equitant time of the step of with above-mentioned output above-mentioned first error correcting code processing data, from above-mentioned the
One data establish one second error correcting code processing data in the above-mentioned second part of above-mentioned page buffer；From above-mentioned first
Error correcting code handles the above-mentioned first error correcting code state of data and establishes above-mentioned second error correcting code processing in above-mentioned
In the time of the step of data, one second error correcting code state of one second data of a second page is determined, above-mentioned second
Data include above-mentioned first error correcting code processing data and above-mentioned second error correcting code processing data；It is wrong by above-mentioned second
Accidentally more code state is stored in a state buffer；The step of the first error correcting code processing data above-mentioned with above-mentioned output, is mutually be overlapped
In the folded time, from the data of above-mentioned one first continuous page of NAND gate flash memory array access；It is slow from the above-mentioned page
The above-mentioned second part for rushing device exports above-mentioned second error correcting code processing data；With above-mentioned second error correcting code of above-mentioned output
In the step of handling data equitant time, from the data of above-mentioned first continuous page in above-mentioned the of above-mentioned page buffer
A part establishes third error correcting code processing data；Judge a third mistake of above-mentioned third error correcting code processing data
More code state；Above-mentioned third error correcting code, which is exported, from the above-mentioned first part of above-mentioned page buffer handles data；With it is upper
In the step of the stating output above-mentioned third error correcting code processing data equitant time, above-mentioned the of above-mentioned page buffer
In two parts, one the 4th error correcting code processing data are established from the data of above-mentioned first continuous page；From above-mentioned third mistake
More code handles the above-mentioned third error correcting code state of data and establishes above-mentioned 4th error correcting code processing data in above-mentioned
Step when, judge one the 4th error correcting code state of a third data of a third page, above-mentioned third data include upper
State third error correcting code processing data and above-mentioned 4th error correcting code processing data；Store above-mentioned 4th error correcting code
State is in above-mentioned state buffer；And the step of with above-mentioned output above-mentioned third error correcting code processing data it is equitant when
Between in, from the data of above-mentioned one second continuous page of NAND gate flash memory array access.
Another embodiment of the present invention is a kind of digital memory device, comprising: a NAND gate flash memory array；
One row decoder is coupled to above-mentioned NAND gate flash memory array；One Data buffer is coupled to above-mentioned NAND gate quick flashing
Formula memory array, and including at least one first data portion and one second data portion；One cache buffer, is coupled to
Data buffer is stated, and including at least one first cache part and one second cache part, above-mentioned first data portion is corresponding
To above-mentioned first cache part, above-mentioned second data portion is corresponding to above-mentioned second cache part；One error correcting code circuit, coupling
It is connected to above-mentioned cache buffer；One column decoder is coupled to above-mentioned cache buffer；And a control circuit, it is coupled to above-mentioned
Row decoder, above-mentioned column decoder, above-mentioned Data buffer, above-mentioned cache buffer and above-mentioned error correcting code circuit.On
Stating control circuit includes multiple logic elements and multiple buffer elements, to execute function below: from above-mentioned NAND gate
Flash memory array is loaded into one first data of a first page to above-mentioned Data buffer；From above-mentioned cache buffer
One first data segments of one first data of above-mentioned first page are copied to above-mentioned cache and kept in by above-mentioned first cache part
The above-mentioned first cache part of device；By above-mentioned first data segments of above-mentioned first data in above-mentioned the of above-mentioned cache buffer
One first error correcting code processing data are established in one cache part；Judge the one the of above-mentioned first error correcting code processing data
One error correcting code state；Above-mentioned first error correcting code processing is exported from the above-mentioned first cache part of above-mentioned cache buffer
Data；From above-mentioned second data portion of above-mentioned Data buffer, by the one second of above-mentioned first data of above-mentioned first page
Data segments are copied to the above-mentioned second cache part of above-mentioned cache buffer；At above-mentioned first error correcting code of above-mentioned output
In the function equitant time for managing data, in the above-mentioned second cache part of Yu Shangshu cache buffer, from above-mentioned first page
Above-mentioned second data segments of above-mentioned first data in face establish one second error correcting code processing data；From above-mentioned first mistake
More code handles the above-mentioned first error correcting code state of data and establishes above-mentioned second error correcting code processing when part is above-mentioned
When the function of data, one second error correcting code state of one second data of a second page, above-mentioned second data are determined
Data are handled including above-mentioned first error correcting code and above-mentioned second error correcting code handles data；More by above-mentioned second mistake
Code state is stored in a state buffer；It is equitant with the function of the above-mentioned first error correcting code processing data of above-mentioned output
In time, the data of one first continuous page are loaded into above-mentioned Data buffer from above-mentioned NAND gate flash memory array；
Above-mentioned second error correcting code, which is exported, from the above-mentioned second cache part of above-mentioned cache buffer handles data；Above-mentioned first is connected
One first continuous page section of the data of the continuous page is copied to above-mentioned from above-mentioned first data portion of above-mentioned Data buffer
The above-mentioned first cache part of cache buffer；It overlaps with the function of the above-mentioned second error correcting code processing data of above-mentioned output
Time in, established at a third error correcting code from the above-mentioned first continuous page section of the data of above-mentioned first continuous page
Data are managed in the above-mentioned first cache part of above-mentioned cache buffer；Judge the one the of above-mentioned third error correcting code processing data
Three error correcting code states；Above-mentioned third error correcting code processing is exported from the above-mentioned first cache part of above-mentioned cache buffer
Data；From above-mentioned second data portion of above-mentioned Data buffer by one second continuous page of the data of above-mentioned first continuous page
Face section is copied to the above-mentioned second cache part of above-mentioned cache buffer；It is handled with the above-mentioned third error correcting code of above-mentioned output
It is continuous from above-mentioned first in the above-mentioned second cache part of above-mentioned cache buffer in the function of the data equitant time
The above-mentioned second continuous page section of the data of the page establishes one the 4th error correcting code processing data；More from above-mentioned third mistake
The above-mentioned third error correcting code state of code processing data and above-mentioned 4th error correcting code processing number is established in part is above-mentioned
According to function when, judge one the 4th error correcting code state of a third data of a third page, above-mentioned third data packet
Include above-mentioned third error correcting code processing data and above-mentioned 4th error correcting code processing data；Store above-mentioned 4th mistake more
Code state is in above-mentioned state buffer；And it overlaps with the function of the above-mentioned third error correcting code processing data of above-mentioned output
Time in, the data of one second continuous page are loaded into above-mentioned data from above-mentioned NAND gate flash memory array and are kept in
Device.
Another embodiment of the present invention is a kind of memory reading method, suitable for continuously reading from a digital memory device
Access evidence, wherein above-mentioned digital memory device includes the NAND gate flash memory array and a page being mutually coupled
Buffer, above-mentioned page buffer are at least divided into a first part and a second part, the memory reading method
It include: one first data from above-mentioned one first page of NAND gate flash memory array access；From above-mentioned first data in
One first error correcting code processing data are established in the above-mentioned first part of above-mentioned page buffer；Judge above-mentioned first mistake more
One first error correcting code state of code processing data；Above-mentioned first is exported from the above-mentioned first part of above-mentioned page buffer
Error correcting code handles data；In the step of the first error correcting code processing data above-mentioned with above-mentioned output equitant time,
One second error correcting code processing data are established in the above-mentioned second part of above-mentioned page buffer from above-mentioned first data；From
Above-mentioned first error correcting code handles the above-mentioned first error correcting code state of data and establishes above-mentioned second mistake more in above-mentioned
Code was handled in the time of the step of data, determined one second error correcting code state of one second data of a second page,
Above-mentioned second data include above-mentioned first error correcting code processing data and above-mentioned second error correcting code processing data；Storage
Above-mentioned second error correcting code state；The step of the first error correcting code processing data above-mentioned with above-mentioned output equitant time
In, from the data of above-mentioned one first continuous page of NAND gate flash memory array access；From the upper of above-mentioned page buffer
It states second part and exports above-mentioned second error correcting code processing data, and from the above-mentioned second error correcting code state of above-mentioned storage
The step of export above-mentioned second error correcting code state；The step of handling data with above-mentioned second error correcting code of above-mentioned output phase
In the time of overlapping, a third is established in the above-mentioned first part of above-mentioned page buffer from the data of above-mentioned first continuous page
Error correcting code handles data；Judge a third error correcting code state of above-mentioned third error correcting code processing data；From upper
The above-mentioned first part for stating page buffer exports above-mentioned third error correcting code processing data；It is wrong with the above-mentioned third of above-mentioned output
Accidentally in the step of more code processing data equitant time, from the data of above-mentioned first continuous page in above-mentioned page buffer
Above-mentioned second part in establish one the 4th error correcting code processing data；From the upper of above-mentioned third error correcting code processing data
It states third error correcting code state and when the above-mentioned step for establishing above-mentioned 4th error correcting code processing data, judges a third
One the 4th error correcting code state of one third data of the page, above-mentioned third data include above-mentioned third error correcting code processing
Data and above-mentioned 4th error correcting code handle data；Store above-mentioned 4th error correcting code state；It is above-mentioned with above-mentioned output
Third error correcting code was handled in the step of data equitant time, from above-mentioned NAND gate flash memory array access one
The data of second continuous page；And it is exported at above-mentioned 4th error correcting code from the above-mentioned second part of above-mentioned page buffer
Data are managed, and the step of the 4th error correcting code state above-mentioned from above-mentioned storage exports above-mentioned 4th error correcting code state.
Another embodiment of the present invention is a kind of memory reading method, suitable for continuously reading from a digital memory device
Access evidence, wherein above-mentioned digital memory device includes the NAND gate flash memory array and a page being mutually coupled
Buffer, above-mentioned page buffer are at least divided into a first part and a second part, the memory reading method
It include: one first data from above-mentioned one first page of NAND gate flash memory array access；From above-mentioned first data in
One first error correcting code processing data are established in the above-mentioned first part of above-mentioned page buffer；Judge above-mentioned first mistake more
One first error correcting code state of code processing data；Export above-mentioned first error correcting code processing data；In above-mentioned output
After the step of above-mentioned first error correcting code processing data, above-mentioned first part output from above-mentioned page buffer above-mentioned the
One error correcting code handles data；The step of the first error correcting code processing data above-mentioned with above-mentioned output equitant time
In, from above-mentioned one first continuous page data of NAND gate flash memory array access；With above-mentioned first mistake of above-mentioned output
More code was handled in the step of data equitant time, from above-mentioned first data in above-mentioned second of above-mentioned page buffer
One second error correcting code processing data are established in point；Determine one second error correction of one second error correcting code processing data
Code state；Export above-mentioned second error correcting code state；After the step of above-mentioned output above-mentioned second error correcting code state, from
The above-mentioned second part of above-mentioned page buffer exports above-mentioned second error correcting code and handles data；With above-mentioned output above-mentioned second
Error correcting code was handled in equitant time the step of data, from the data of above-mentioned first continuous page in above-mentioned page buffer
The above-mentioned first part of device establishes third error correcting code processing data；Judge above-mentioned third error correcting code processing data
One third error correcting code state；Export above-mentioned third error correcting code processing data；The above-mentioned third mistake of above-mentioned output more
After code handles the step of data, exported at above-mentioned third error correcting code from the above-mentioned first part of above-mentioned page buffer
Manage data；In the step of third error correcting code processing data above-mentioned with above-mentioned output equitant time, from above-mentioned NAND gate
The data of one second continuous page of flash memory array access；And it is handled with the above-mentioned third error correcting code of above-mentioned output
In the step of data equitant time, from the data of above-mentioned first continuous page in above-mentioned second of above-mentioned page buffer
Divide and establishes one the 4th error correcting code processing data.
The present invention provides a kind of memory reading method and digital memory device, seals with less pin number purpose
Fill type；Error correcting code processing can be integrated, the time is withouted waiting for；Guarantee data output speed and it is successional before
It puts and will not influence damage block management.
Detailed description of the invention
Fig. 1 shows that NAND gate flash memory described in an embodiment according to the present invention operates in one and continuously reads
Flow chart；
Fig. 2 shows that the page with Data buffer and cache buffer described in an embodiment according to the present invention is slow
Rush functional schematic of the device in the continuous reading process of a part of Fig. 1；
Fig. 3 shows the continuous of the another part for having the page buffer of Data buffer and cache buffer in Fig. 1
Functional schematic in reading process；
Fig. 4 shows the continuous of the another part for having the page buffer of Data buffer and cache buffer in Fig. 1
Functional schematic in reading process；
Fig. 5 shows the functional block diagram of the pipeline circuit for error correcting code state pipeline operation；
Fig. 6 display participates in the page buffer with Data buffer as Figure 1-Figure 4 and cache buffer
The signal timing diagram of various signals；
Fig. 7 shows that NAND gate flash memory operates in the flow chart continuously read；
Fig. 8 display participates in the various of the page buffer with Data buffer as shown in Figure 7 and cache buffer
The signal timing diagram of signal；
Fig. 9 shows that NAND gate flash memory operates in the flow chart continuously read；
Figure 10 display participates in the various of the page buffer with Data buffer as shown in Figure 9 and cache buffer
The signal timing diagram of signal；Figure 11 display participates in the signal timing diagram of the various signals of the page buffer of the deformation of Fig. 9；And
Figure 12 shows the functional block diagram of serial NAND gate flash memory.
Symbol description:
210 data busbar connectors；220 error correcting code circuits；
230 cache buffers；240 Data buffers；
250 NAND gate flash memory arrays；
252 first pages；254 second pages；
260 first time axis；270 second time shafts；
280 third time shafts；300 error correcting code blocks；
302 next page error correcting code state bits；
304 current page faults more code mode bit member；
310 page datas read instruction；330,360 waiting time；
340,370 data command is read；
320,350,380 reading state buffers instruct；
390 FFh instruction；
600 serial NAND gate flash memories；
622 i/o controllers；623 state buffers；
624 continuous pages read address register；
625 order buffers；626 address registers；
627 LUT buffers；628 counterlogics；
629 address counters；630 control logics；
631 continuous pages read failure area logic；
632 continuous page failure area buffers；
633 high voltage generators；634 row decoders；
635 power-on detectors；636 column decoders；
638 page buffers；
640 NAND gate flash memory arrays；
The 642 addressable regions of NAND gate flash memory array user；
644 redundancy block regions；646 LUT information blocks；
647 buffer mode flags；648 ECC-E flags；
650, the first error correcting code of ECC-0 state bit；
651, the second error correcting code of ECC-1 state bit；
652, the busy bit of BUSY；
The first data portion of DR-0；The second data portion of DR-1；
The first cache of CR-0 part；The second cache of CR-1 part；
A first period；The B second phase；
During C1+C2 third；Between the D fourth phase；
The E period 5；During F1+F2+F3 the 6th；
During G the 7th；During H the 8th；
During I the 9th；During J1+J2 the tenth；
BS confirms busy bit；CLK clock signal；
The chip select signal of/CS reverse phase；
DI input serial data signal；DO serial data output signal；
ES error correcting code state bit；I/O input/output；
LUT look-up table；SP spare area；
The write protect signal of/WP reverse phase；
The maintenance signal of/HOLD reverse phase；ECC_EN enable signal；
ECC_UPDATE more new signal；VCC power supply line supplies voltage；
GND ground terminal；
100~160,400~442,500~542 process steps.
Specific embodiment
NAND memory device can be made with the compatible characteristic of the numerous characteristics of AND OR NOT gate memory device, including (1)
Multi input/output (I/O) Serial Peripheral Interface (SPI) (SPI)/fast channel interconnection (QPI) interface；(2) less pin number purpose envelope
Type (density is 256Mb or higher 8*6mm) is filled, for example, SOIC and 24 ball of the WSON of 8 contact points, 16 foot positions
BGA type package, have using big encapsulation (as is common for general parallel or general serial NAND Flash formula memory
VBGA-63 elasticity)；(3) high clock frequency operation (such as 104MHz) is to high transfer rate (such as 50MHz/ seconds)；(4) it is used for
The leap page boundary of fast coding mapping application continuously reads and has error correcting code processing, without the waiting time；(5)
Via being sent to external system and not having dysgenic damage block management (bad in the speed and continuity of output
Block management), the memory continuously indicated to logicality；And (6) are set by user or manufacturer
The value of setting, to determine that output initial address is any for the address that user can specify in logical zero or memory array
Person.Continuous read mode is particularly suitable for executing (execute-in- in coding mapping to random access memory (RAM), chip
Place, XIP) and big message, image, text and the data segments of quick-searching.
Many skills can reach rapidly and effectively continuous read operation, such as with the Data buffer and subregion of subregion
The Data buffer of cache buffer, the configurable internal error correcting code related with cache buffer of user and quick
Damage block management.To overcome framework, efficiency, unreliability and the skill of damage block limitation, make it difficult to support height
Fast coding mapping and entitled " Method and Apparatus for Reading NAND Flash Memory ", invention
Artificial Gupta et al., bulletin are in the US patent number 8,667,368 on March 4th, 2014；Entitled " On-Chip Bad
Block Management for NAND Flash Memory ", it inventor Michael et al., is disclosed in 2013 12
The U.S. Patent Publication No. 2013/0346671 on the moon 26；And entitled " NAND Flash Memory ", inventor
Jigour et al., the patent application number 13/799,215 for applying on March 13rd, 2013；And it is relative with
The application executed in the chip of NOT gate flash memory, it is all these to be all incorporated herein it herein all as reference.
A device of continuous read operation is provided as positioned at the winbond electronics company (Winbond of San Jose,California,USA
Electronics Corporation) W25N01GV produced, it is described as winbond electronics company W25N01GV in 2013
It is fast with two/tetra- Serial Peripheral Interface (SPI)s and the 3V Serial Peripheral Interface (SPI) continuously read in the preliminary version B that November 26 proposed
Entire contents are incorporated in this herein by the flash serial single-layer type NAND gate flash memory of 1G bit.W25N01GV device
It is incorporated to a traditional large-scale NAND gate non-volatility memorizer space, is especially arranged to 2048 of 65536 programmable pages
1G bit memory array in tuple.The device is also incorporated into Serial Peripheral Interface (SPI) (Serial Peripheral
Interface, SPI), Serial Peripheral Interface (SPI) includes serial (bit-serial) Serial Peripheral Interface (SPI) of single bit and dibit
First serial (dual serial), nibble serial (quad serial) and four input/output Serial Peripheral Interface (SPI)s.Serial peripheral
Interface clock frequency can support up to 104MHz, when using dual input/output/tetra- input/output instruction is quickly read, allow
Equivalent clocking rate 208MHz (104MHz*2) is to dual input/output, and allows equivalent clocking rate 416MHz (104MHz*
4) to four input/output.W25N01GV is installed on the buffering read mode (BUF=1) to the data of access page buffer
And the continuous read mode (BUF=0) efficiently to access the whole memory array with one reading command it
Between switch.
W25N01GV device has effective error correcting code ability to manage the integrality of data.In data read operation
When, error correcting code engine verify data in a limited degree, and correct.Verifying and more positive status can be by the second mistakes
Represented by more code mode bit member ECC-1 and the first error correcting code state bit ECC-0.For example, when the second error correction
State when being (1:1) of code state bit ECC-1, the first error correcting code state bit ECC-0, are only applicable to continuously read
Mode, representing entire data output includes the mistake that each page is more than 4 bits in multi-page.In continuous read mode,
The page address (Page Address, PA) of the additional vicious last page of instruction offer tool, and other wrong pages
Address can't be mentioned report.The shape of second error correcting code state bit ECC-1, the first error correcting code state bit ECC-0
State be (1:1) usually enough because it is very rare that the bit mistake in the page per-page accessed, which is more than 4 bits,.
However, in some embodiments, some may wish to the error correcting code state for knowing each page.
Fig. 1 is to show the continuous page read step 100 for executing and having one page then error correcting code state of one page
Operational flowchart, Fig. 2-Fig. 4 is shown in the particular electrical circuit of NAND gate flash memory device and executes many operations, Fig. 6
Display participates in the various signals of these operations.One page then one page error correcting code state model can by it is any it is desired in a manner of cause
Can and disability, an exemplary skill be (set) set by the bit that is set as a user and reset (reset).
No matter automatically powering on (such as NAND gate flash memory array page zero) or responding page data when resetting
It reads instruction (page data referring to Fig. 6 reads instruction 310) or in such a way that any other is needed, is loaded into a page to the page
Buffer (step 110).As shown in Fig. 2, two single page buffer cooperations and page buffer is provided, especially data are temporary
Storage 240 is divided into the first data portion DR-0 and the second data portion DR-1, cache buffer 230 are divided into the first cache
Part CR-0 and the second cache part CR-1 is corresponding to the first data portion DR-0 of Data buffer 240 and the second data
Part DR-1.In first period A, first page 252 is loaded into Data buffer 240, and first page 252 is then in the second phase
Between B be copied to cache buffer 230 (first page 252 can be replicated all as shown in the figure, or only the first of Data buffer 240
Reproducible the first cache part CR-0 to cache buffer 230 of data portion DR-0), and during third in C1+C2 in fast
Execution error correction coded program on the first cache part CR-0 of buffer 230 is taken, wherein C1 is represented by the first cache part CR-
0 transfer data to the first error correcting code state bit ECC-0 of error correcting code circuit 220 needed for the time, C2 same generation
Time needed for table transfers data to the first cache part CR-0 as the first error correcting code state bit ECC-0.If necessary,
Error correction coded program can also be implemented in the second cache part of cache buffer 230 between the fourth phase in (not display in figure)
CR-1, these operations are all continuous, therefore these times are accumulation, as shown in first time axis 260.
With further reference to Fig. 1, confirming that the state (step 120) of busy bit (BS) is available has busy bit BUSY's
Reading state buffer (0Fh/05h) instruction of the address of state buffer (is instructed referring to the reading state buffer of Fig. 6
320).State buffer bit is then moved to D0 foot position in the falling edge of clock signal CLK.Error correcting code state bit
(ES) it can also access by this method, although may be ignored at this moment.The instruction of reading state buffer can be used for any time,
Therefore allow to confirm busy bit BUSY and determine when that circulation terminates and whether device is subjected to another instruction, state is temporary
Device can continuously be read, which can be completed by chip select signal/CS of driving reverse phase to high logic level.
After taking buffer to instruct the time of 320 (Fig. 6) in read states, busy bit BUSY is removed (step 120 confirmation
Be no) and receive read data command 340 (Fig. 6) (step 122 is confirmed as) when, can by execute error correction coded program
A continuous page reading is carried out, and can be from the first cache part CR-0 and the second cache part CR-1 of cache buffer 230
Alternately output data, further cooperation are from Data buffer 240 to the duplication of the data of cache buffer 230 and the subsequent page
Loading, such as be loaded into from the continuous second page 254 of NAND gate flash memory array 250 to Data buffer 240.Such as step
Shown in rapid 130, step 132 and step 134, read data command 340 (Fig. 6) with betide substantially be overlapped same time
Three different operations carry out simultaneously, that is, output data to data from the first cache part CR-0 of cache buffer 230
Busbar connector 210 executes error correcting code in the second cache part CR-1 of cache buffer 230 and deposits NAND gate flash type
The continuous second page 254 of memory array 250 is loaded into Data buffer 240.As shown in figure 3, the data of output betide the
Four period D, error correction coded program betide the 6th period F1+F2+F3 and page loading betides the 7th period G, wherein
D, the 6th period F1+F2+F3 and the 7th period G are substantially overlapped just as shown in the second time shaft 270 between the fourth phase.
Between the short fifth phase E to replicate data buffer 240 the second data portion DR-1 to cache buffer 230 the second cache
Part CR-1, after E followed by the 6th period F1+F2+F3 and the 7th period G between the fifth phase, can between the fourth phase D phase it is be overlapped
It is folded.
Error correcting code journey is carried out to the first cache part CR-0 and the second cache part CR-1 of cache buffer 230
The page data of sequence read after instruction first read data command for, can omit replicate data period 5 E and
6th period F1+F2+F3 of error correction coded program.
The error correcting code state bit of the page and next page can utilize pipeline at present, have ensured that error correction
Code state bit and the data of output are synchronised.When the error correction coded program of the page register of second part is completed, mesh
The error correcting code state bit of the preceding page can be finally confirmed (step 132), then be latched in the 6th period F3 (Fig. 3)
To state buffer, so that can be in the case where not adjusting the error correcting code state bit in state buffer too early, certainly
Determine the error correcting code state bit of next page.Fig. 5 shows the demonstrative circuit for being suitable for realizing pipeline operation.When the letter that is enabled
After number ECC_EN enable, error correcting code block 300 executes error correction coded program.Next page error correcting code state bit
302 can update the next page error correcting code state from error correcting code block 300 according to clock signal CLK.Work as completion
Next page error correcting code state bit 302 and when essentially becoming current page fault more code mode bit member, can be more
Under the control of new signal ECC_UPDATE and clock signal CLK, it is latching to current page fault and updates code mode bit
Member 304.If necessary, page fault more code mode bit member 304 can be stored in state buffer at present.In state buffer
At present page fault more code mode bit member thus page synchronization with output, can be too early in adjustment state buffer
In the case where error correcting code state bit, the new next page error correcting code state bit 302 of next page is determined.
Then, as shown in step 140 and step 142, two different operations were betided in the substantially equitant time,
Data busbar connector 210 namely is output data to from the second cache part CR-1 of cache buffer 230, and temporary in cache
When first cache part CR-0 of device 230 executes error correcting code, start to determine error correcting code state.As shown in figure 4, output
Data betide the 8th period H and the tenth period J1+J2 being substantially overlapped shown in third time shaft 280.It betides
The error correction coded program of tenth period J1+J2 starts to determine next page error correcting code state bit, but adequate measures,
Such as pipeline operation, it can be used to ensure that current page fault more code mode bit member holds effectively the page dimensions of output.Short the 9th
Period I to replicate data buffer 240 the first data portion DR-0 to cache buffer 230 the first cache part CR-
0, after the 9th period I then the tenth period J1+J2, then overlap with the 8th period H.
Then, continuous page reading can suspend in page boundary (step 150), to read the corresponding page just exported
Error correcting code state bit.The technology read suitable for pause continuous page is, will after reading last page bit group
Chip select signal/CS of reverse phase is pulled to high logic level.When enable one page then one page error correction pattern, reverse phase
When chip select signal/CS is changed into high logic level, suspend internal operation so that controller is using a reading state
Buffer instruction (step 160) (the reading state buffer referring to Fig. 6 instructs 350) reads the error correction of the page just exported
Code state.When busy bit removed (not showing) and after appropriate latent period (referring to the waiting time 360 of Fig. 6),
It issues again and reads data command (referring to the reading data command 370 of Fig. 6) to restore continuous page read operation.
In error correcting code state bit (the reading shape of reference Fig. 6 for the last page for reading continuous page read operation
After the instruction 380) of state buffer, can by it is any it is desired in a manner of terminate the continuous page with one page then one page error correcting code
The progress of reading is such as instructed by issuing FFh afterwards in page boundary (the FFh instruction 390 of Fig. 6) in pause, or in page data
Chip select signal/CS of reverse phase is pulled to high logic level when output.
Fig. 7 is shown to execute with the various of one page then continuous read step 400 of one page error correcting code state
The flow chart of operation, wherein continuous page reads the effective continuous page for exporting not only data of instruction, more exports each continuous
The error correcting code state bit of the page.For example, usually as shown in figs 2-4 and its mode of corresponding description, in conjunction with one
The page register of page subregion and the cache buffer of one page subregion provide page buffer.Fig. 8 display participates in these behaviour
The various signals made.One page then one page error correcting code state model can by it is any it is desired in a manner of enable and disability, one
Exemplary skill is (set) set by the bit that is set as a user and resets (reset).
Referring to Fig. 7, automatic (such as page 0 of NAND gate flash memory array) or the response page when being powered
Data read command or in such a way that any other is desired, is loaded into page buffer (step 410) for a page.The page
Face is then copied to cache buffer, and (page can be all replicated, or the first part of only Data buffer can be answered
Make to the first part of cache buffer), error correction coded program can be implemented in the first part of cache buffer.
Referring again to Fig. 7, using the reading state buffer (0Fh/ of the address of the state buffer with busy bit
It 05h) instructs, to confirm the state of busy bit (BS).State buffer bit is then in the negative edge of clock signal CLK, quilt
Move to serial data output signal DO.(step 420 is no) and reception reading data command (step when busy bit is removed
422 be yes) when, continuous page reading is carried out using the error correction coded program for executing data, and can be from cache buffer
First cache part CR-0 and the second cache part CR-1 replace output data, and further cooperation is from Data buffer to fast
The data of buffer are taken to replicate and be loaded into Data buffer from the subsequent page of NAND gate flash memory array.Such as
Shown in step 430, step 432 and step 434, data and three differences betiding substantially be overlapped same time are read
It operates while carrying out, that is, output data to data busbar connector, in cache from the first cache part CR-0 of cache buffer
Second cache part CR-1 of buffer executes error correcting code and by the continuous page of NAND gate flash memory array
It is loaded into Data buffer.The error correcting code state bit of the page and next page at present, can as shown in Figure 3-Figure 5 and its
The mode of narration and pipeline operation, to ensure that the page of error correcting code state bit and output is synchronised.Then, such as step
440 and step 442 shown in, two different operations betided in the time of the same nature, that is, temporary from cache
Second cache part CR-1 of device is output data to after data busbar connector, output error more code mode bit member, and in cache
First cache part CR-0 of buffer executes error correcting code.
It is read in the last page of continuous page read operation and the error correcting code state bit of the last page
Afterwards, the continuous page with one page then one page error correcting code read can by it is any it is desired in a manner of terminate, as shown in Fig. 8
Output page data when, chip select signal/CS of reverse phase is pulled to high logic level.
Fig. 9 display execute have a subregion then a subregion error correcting code state continuous page read 500 it is various
The flow chart of operation, wherein continuous page reading instruction is not only effective to the data of output continuous page, also to each continuous page
The error correcting code state bit of each subregion in face is effective.Furthermore error correcting code state can provide before the page of output.
By this method, user can learn whether the data can be used before reading data, also can accurately grasp very much wrong bit
Position at which.For example, usually as shown in Fig. 2-Fig. 4 figure and its narration mode, in conjunction with one page subregion the page keep in
The cache buffer of device and one page subregion provides page buffer.Figure 10 display participates in the various signals of these operations.One
Subregion then a subregion error correcting code state model can by it is any it is desired in a manner of enable and disability, an exemplary skill
For (set) set by the bit that is set as a user and reset (reset).
With reference to Fig. 9, refer to no matter automatically powering on (such as NAND gate flash memory) or responding page data reading
It enables or in such a way that any other is needed, is loaded into a page to page buffer (step 510).The page is then copied to
Cache buffer (the cache that the page can be integrally replicated or only the Data buffer of first part is copied to first part
Buffer), and error correction coded program is implemented in the cache buffer of first part.
Referring again to Fig. 9, pass through the reading state buffer (0Fh/ of the address of the state buffer with busy bit
It 05h) instructs, to confirm the state (step 520) of busy bit (BS).State buffer bit is then clock signal CLK's
When negative edge, it is moved to serial data output signal DO.It is removed (step 520 is no) when busy bit and receives reading data and referred to
When enabling (step 522 is yes), continuous page reading is carried out using the error correction coded program for executing data, and can be temporary from cache
The the first cache part CR-0 and the second cache part CR-1 of storage replace output data, and further cooperation is temporary from data
Device to cache buffer data duplication and from the subsequent page of NAND gate flash memory array to be loaded into data temporary
Storage.As shown in step 530, step 532 and step 534, read data with betide substantially be overlapped same time
Three different operations carry out simultaneously, that is, output data to data busbar connector from the first cache part CR-0 of cache buffer
(step 530) executes error correcting code in the second cache part CR-1 of cache buffer and result is latching to error correction
Code state bit (step 532) and by the continuous page of NAND gate flash memory array be loaded into Data buffer (step
It is rapid 534).The error correcting code state bit of the page and next page at present, can mode as shown in Figure 3-Figure 5 and its narration
And pipeline operation, to ensure that the page of error correcting code state bit and output is synchronised, and error correcting code state can be in
It is reseted after latching every time.Then, as shown in step 540 and step 542, two different operations betide substantially identical
Time in, that is, from the second cache part CR-1 of cache buffer export the first error correcting code state bit to data
Busbar connector (step 540), and error correcting code is executed in the first cache part CR-0 of cache buffer, and result is latching to
Error correcting code state bit (step 542).
It is read in the last page of continuous page read operation and the error correcting code state bit of the last page
Afterwards, with a subregion then a subregion error correcting code continuous page read can by it is any it is desired in a manner of terminate, such as in page
It (is not shown) when face data exports, chip select signal/CS of reverse phase is pulled to high logic level.
In some embodiments, user may want to the data of the spare area of access each page.The method of Fig. 9 can
It is slightly adjusted to, the partial data in output is ready for use using first part's data with cache buffer region, and with
The second part data of cache buffer and the partial data in output is ready for use region, and reach this purpose.Corresponding signal is as schemed
Shown in 11, wherein SP represents spare area (spare area), and EC represents error correcting code state bit.In addition, entire spare
Region can be used as the first part's data or second part data of the cache buffer of part.
Serial NAND gate flash memory framework
Figure 12 shows the functional block diagram of serial NAND gate flash memory 600, serial NAND gate flash memory
600 are capable of providing the continuous reading across page boundary, and from continuous storage address in logic read and without waiting for when
Between, serial NAND gate flash memory 640 is also capable of providing the error correcting code status information of one page then one page.Serially with
NOT gate flash memory 600 includes NAND gate flash memory array 640 and related page buffer 638.With it is non-
Door flash memory array 640 includes wordline (row) and bit line (column), and is placed in NAND gate flash memory array
The addressable region 642 of user, redundancy block region (redundant block area) 644 and look-up table (LUT) letter
Cease block 646.Any desired flash memory monotechnics can be used for the quick flashing of NAND gate flash memory array 640
Formula memory cell.Serial NAND gate flash memory 600 may include various other circuits to support memory write-in, wipe
It removes and reads, such as row decoder 634, column decoder 636, i/o controller 622, state buffer 623, continuous page
Read address register 624, order buffer 625, address register 626, look-up table (LUT) buffer 627, control logic in face
630, continuous page reads bad block logic 631, continuous page bad block buffer 632 and high voltage generator 633.
Row decoder 634 user control and in some embodiments under internal control, NAND gate flash type is deposited
Memory array select the addressable region 642 of user column, and under internal control select redundancy block region 644 and
The column of look-up table (LUT) information block 646.Voltage VCC and ground terminal GND is supplied using power supply line, provides power supply to serial
All circuits (not shown in figure) of NAND gate flash memory 600.When serial NAND gate flash memory 600 can be with
Any desired mode encapsulates and the interface with any pattern, including general NAND gate flash memory interface, Figure 12's
Control logic 630 exemplarily realizes Serial Peripheral Interface (SPI) (SPI)/fast channel interconnection (QPI) agreement, including multiple input is defeated
Serial Peripheral Interface (SPI) out.Other Serial Peripheral Interface (SPI)s (SPI)/fast channel interconnection (QPI) interface details and memory
A variety of different circuits, can be in the mark of the Jigour et al. US patent number 7,558,900 proposed on July 7th, 2009
What entitled " Serial Flash Semiconductor Memory " and aforementioned winbond electronics were proposed on November 26th, 2013
In preliminary version B, with two/tetra- Serial Peripheral Interface (SPI)s and the serial single-layer type NAND gate quick flashing of 3V 1G bit continuously read
Entire contents are incorporated in this herein by the W25N01GV of formula memory.
If pattern switching is as expection, it is possible to provide buffer mode flag (BUF) 647.If necessary, it is possible to provide buffer mode
A bit of the flag (BUF) 647 as state buffer 623.Power-on detector 635 is provided in control logic 630, to start spy
The setting of mould-fixed and the default page of loading when one is powered.
Busy bit 652 is the only read bit member of state buffer, when device is powered or executes many instructions, busy bit
652 can be set as the state of logic 1, including page data reads instruction and continuous read instructs.
Page buffer 638 includes single page Data buffer (not showing in figure), single page cache buffer
(not shown in figure) and single page gate (not shown in figure), the data of Data buffer are copied to cache
Buffer.Any suitable latch or memory technology can be used for Data buffer and cache buffer, any suitable lock
Road technology can be used for the data of Data buffer being copied to cache buffer.Data buffer and cache buffer can appoint
The block of what be intended to number arranges, such as transmission gate (transmission gate) is line and the biography for being used to control data
It is defeated.For example, Data buffer and cache buffer are respectively divided into two different parts, and use is by unit control
Individual groups of the transmission gate of line traffic control and alternately operate.The Data buffer and cache buffer of page buffer 638 can
When being operated in a conventional manner by applying identical control signal to individual transport lock control line, or can apply suitable
Between control signal to transmission gate control line blocked operation.For example, in two-part embodiment, the page is 2K character
The half page (1K) of group, transmission gate can be controlled by a control line, the other half page (1K) of transmission gate can be by another control
Line is controlled, therefore arrangement data buffer and cache buffer are in the part of two and half pages (1K).Because of two parts
Blocked operation can be considered " table tennis (ping pong) " buffer with the page buffer 638 that two parts are realized.Error correcting code
Circuit (not showing in figure) can be used to according to ECC-E flag (ECC-E) 648, and execution executes mistake to the content of cache buffer
Accidentally more code calculates.First error correcting code state bit (ECC-0) 650 and the second error correcting code state bit (ECC-
1) 651 error condition to represent the data in related pages can be true after completion read operation and verify data are completed
Recognize the error condition of the data in the page.If necessary, the 648, first error correcting code of ECC-E flag (ECC-E) state bit
(ECC-0) 650 and second error correcting code state bit (ECC-1) 651 can be used as the part of state buffer 623.
If necessary, can be used different size of page buffer and/or page buffer be divided into greater than two parts or
Unequal part can also.Two groups of control signals may be needed to two parts of page buffer, unlike only needing one group of control letter
Number give undivided page buffer.Furthermore the difference of logicality and physical NAND gate flash memory array, no
It will affect teaching in this.For example, there are two physical NAND gate flash memory array can have in a wordline
The page (the even number 2KB page and the odd number 2KB page) a, so that wordline can be the NAND gate flash memory bit of 4KB
Unit.For clear expression, description in this and attached drawing are all according to logicality NAND gate flash memory array.Mistake is more
Code circuit 220 can be considered as in logic with a part to provide the content error correcting code of the first cache part CR-0
Part the first error correcting code state bit ECC-0 and to provide the content error correcting code of the second cache part CR-1
Part the second error correcting code state bit ECC-1.Various error correcting code algorithms are all suitble to use, including such as
Hamming error correcting code algorithm, BCH error correcting code algorithm, Reed-Solomon error correcting code algorithm and its
He etc..When to simplify the explanation and by the first error correcting code state bit ECC-0 and the second error correcting code mode bit
First ECC-1 is docked with the first cache part CR-0 and the second cache part CR-1 respectively, two physical error correcting codes
Block or a single one physical error correcting code block can be used to and the first cache part CR-0 and the second cache part CR-
1 interface connects.It, can be in aforementioned topic about other related contents of page buffer 638, error correcting code circuit and its operation
For the US patent number 8,667,368 of " Method and Apparatus for Reading NAND Flash Memory "
Entire contents are only incorporated in this herein by middle acquirement.Continuous page described herein is read in aforesaid patent specifications, is claimed
For " adjustment continuous page is read ".Data buffer and cache buffer enter the portion schedules of the page and the portion to the page
Divide the mode for executing error correcting code to be only to illustrate to be used, other technologies can also be used if necessary.
When serial NAND gate flash memory 600 is to execute various read operations, including continuous page read operation
And error correcting code on chip is executed in single plane NAND gate flash memory framework, these frameworks be it is exemplary and
Its deformation is understood that.It is understood that the page-size of 2KB and the example of particular block size are only to illustrate and are used, if having
Needing can also be different.Furthermore because actual pages size can be different according to design factor, specific size is with reference to simultaneously non-slice
Face is by literal upper explanation, such as the term may include that the main region of 2048 character groups adds the spare area of additional 64 character group
Domain, wherein spare area is to store error correcting code and other information, such as background data (meta data).The term of 1KB
It can be the main region of 1024 character groups and the spare area of 32 character groups.For convenience of description, when description in this according to
When single plane framework, teaching in this is also equally applicable to more Flat Architectures.When using multiple physical planes, it can be total to
Multi input/the output that with one or more wordline storage system can be serviced while requiring.Each plane provides one page of data
Face, and the cache buffer of the Data buffer including a corresponding page-size and a corresponding page-size.It is described herein
Skill can be applied individually to any each plane, so that each Data buffer and cache buffer are arranged in different parts, or
Can be applied to more planes makes each Data buffer and cache buffer be the multi-page Data buffer and fast of itself
Take a part of buffer.
Figure 12 also shows chip select signal/CS of the reverse phase for Serial Peripheral Interface (SPI), clock signal CLK, serial number
According to maintenance signal/HOLD of input signal DI, serial data output signal DO, write protect signal/WP of reverse phase and reverse phase.
The Serial Peripheral Interface (SPI) flash type interface of standard with write protect signal/WP of reverse phase and maintenance signal/HOLD of reverse phase,
Chip select signal/CS, clock signal CLK, input serial data signal DI and the serial data output signal of reverse phase are provided
DO.When (data are inputted via input serial data signal the bit serial data busbar connector in standard Serial Peripheral interface
DI, and data output provides simple interface and with starting in single Serial Peripheral Interface (SPI) via serial data output signal DO)
When the compatibility of many controllers of mode, which limit reach higher handling capacity (thru-put).Multidigit member
The interface of Serial Peripheral Interface (SPI) is thus added, and extraly supports that (nibble connects for binary channels (two bit interfaces) and/or four-way
Mouthful) to increase the handling capacity read.Figure 12 also shows binary channels Serial Peripheral Interface (SPI) and the operation of four-way Serial Peripheral Interface (SPI)
Additional data bus signals, that is, by selectively redefining I/O (0), I/O (1), I/O (2) and I/O
(3) function of this four foot positions.In the four-way Serial Peripheral Interface (SPI) read operation (in other embodiments of the embodiment of an explanation
Also it is contemplated that), provide readings appropriate via I/O (0) using a bit standard Serial Peripheral interface and instruct, but address with
And the interface of output data can be four-way (namely nibble data busbar connector).It is grasped with being read in standard Serial Peripheral interface
The data that a bit is exported in work are compared, and four-way Serial Peripheral Interface (SPI) read operation can export nibble in a clock cycle
Data, thus four-way Serial Peripheral Interface (SPI) read operation can provide four times of high read throughputs.Four-way string in this
Row Peripheral Interface read operation, which is merely to illustrate, to be used, and teaching in this can also be applied to other operation modes in the same manner, including
But it is not limited to single serial peripheral busbar connector, binary channels serial peripheral busbar connector, four Peripheral Interfaces (Quad Peripheral
Interface, QPI) and the read modes such as double transmission rate (Double Transfer Rate, DTR).It is connect in four peripheral hardwares
In mouth agreement, complete interface (operation code, address and data output) is based on nibble.It reaches an agreement in double transmission rate
In, output data is provided in the positive triggering edge and negative triggering edge of clock signal CLK, rather than such as single transmission rate (Single
Transfer Rate, STR) in read mode, output data only is provided in the negative triggering edge of clock signal CLK.
The application and advantage that narration of the invention, which includes it, to be mentioned at this are only purposes of discussion, not to limit this hair
The bright range in claim.The deformation and modification of embodiment described herein are all possible, and art technology
Personnel, which also both know about, actually substitutes and is equal to various elements of the invention, can obtain via research patent specification.It lifts
For example, although many embodiments described herein are used for serial NAND gate flash memory, particular mechanics described herein
Such as power-up sequence, model selection and leap page boundary do not have to the waiting time with from logicality connected storage address
Continuous data output etc., can be used for parallel NAND gate flash memory.Furthermore given special value is to illustrate it herein
With can voluntarily modify if necessary.Vocabulary such as " first " and " second " for difference vocabulary rather than are construed to an implicit sequence
An or whole specific part.The deformation and adjustment of these or other embodiment described herein, including reality described herein
The substitution and equivalent of example are applied, can be obtained under without departing substantially from the scope of the present invention and spirit, it is special including application of the invention
Sharp range.
Claims (7)
1. a kind of memory reading method, which is characterized in that suitable for continuously reading data from a digital memory device, wherein
The digital memory device includes the NAND gate flash memory array and page buffer being mutually coupled, described
Page buffer is at least divided into a first part and a second part, and the memory reading method includes:
From one first data of one first page of NAND gate flash memory array access；
One first error correcting code processing number is established in the first part of the page buffer from first data
According to；
Judge one first error correcting code state of the first error correcting code processing data；
First error correcting code, which is exported, from the first part of the page buffer handles data；
In the equitant time of the step of with the output first error correcting code processing data, from first data in
One second error correcting code processing data are established in the second part of the page buffer；
The first error correcting code state of data is handled from first error correcting code and establishes described second in described
Error correcting code was handled in the time of the step of data, determined one second error correcting code of one second data of a second page
State, second data include the first error correcting code processing data and second error correcting code processing number
According to；
The second error correcting code state is stored in a state buffer；
In the step of the first error correcting code processing data described with the output equitant time, from the NAND gate quick flashing
Formula memory array accesses the data of one first continuous page；
Second error correcting code, which is exported, from the second part of the page buffer handles data；
In the step of the second error correcting code processing data described with the output equitant time, from first continuous page
The data in face establish third error correcting code processing data in the first part of the page buffer；
Judge a third error correcting code state of the third error correcting code processing data；
The third error correcting code, which is exported, from the first part of the page buffer handles data；
In the step of third error correcting code processing data described with the output equitant time, in the page buffer
The second part in, from the data of first continuous page establish one the 4th error correcting code processing data；
The third error correcting code state of data is handled from the third error correcting code and establishes the described 4th in described
When error correcting code handles the step of data, one the 4th error correcting code state of a third data of a third page is judged,
The third data include the third error correcting code processing data and the 4th error correcting code processing data；
The 4th error correcting code state is stored in the state buffer；And
In the step of third error correcting code processing data described with the output equitant time, from the NAND gate quick flashing
Formula memory array accesses the data of one second continuous page.
2. memory reading method as described in claim 1, which is characterized in that
The page buffer includes a cache buffer and a Data buffer, and the cache buffer is at least divided into one
First cache part and one second cache part, the Data buffer are at least divided into one first data portion and one
Two data portions, first data portion is corresponding to first cache part, and second data portion is corresponding to described
Second cache part；
Described the step of establishing the second error correcting code processing data, be included in the cache buffer described second are fast
It takes in part and executes error correction coded program and establish the second error correcting code processing number in second cache part
According to；
The step of access first continuous page, including first continuous page is loaded into the Data buffer；
The step of output second error correcting code processing data, including fast from described the second of the cache buffer
Part is taken, second error correcting code is exported and handles data；
Described the step of establishing the third error correcting code processing data, be included in the cache buffer described first are fast
Part is taken to execute error correction coded program, the third error correcting code processing data are established in the first cache of Yu Suoshu part；
The step of output third error correcting code processing data, including fast from described the first of the cache buffer
Part is taken to export the third error correcting code processing data；And
The step of access second continuous page, including second continuous page is loaded into the Data buffer.
3. memory reading method as described in claim 1, which is characterized in that the digital memory device further includes receiving
One input terminal of one chip select signal, the memory reading method further include:
The step of completing the storage the second error correcting code state, output second error correcting code handle number
According to the step of and described the step of establishing third error correcting code processing data after, postpone the output described the
Three error correcting codes handle the step of data, to respond the transition of the chip select signal；
Receive reading state buffer instruction；
The state buffer is exported, the step of to respond the reception reading state buffer；
After the step of completing the output state buffer, a buffer readout order is received；And
The reception buffering reading is responded together with the step of third error correcting code processing data described with the output to refer to
The step of enabling.
4. a kind of digital memory device, which is characterized in that the digital memory device includes:
One NAND gate flash memory array；
One row decoder is coupled to the NAND gate flash memory array；
One Data buffer, is coupled to the NAND gate flash memory array, and including at least one first data portion with
And one second data portion；
One cache buffer is coupled to the Data buffer, and including at least one first cache part and one second cache
Part, first data portion is corresponding to first cache part, and second data portion is corresponded to described second fastly
Take part；
One error correcting code circuit is coupled to the cache buffer；
One column decoder is coupled to the cache buffer；And
One control circuit is coupled to the row decoder, the column decoder, the Data buffer, the cache buffer
And the error correcting code circuit is used wherein the control circuit includes multiple logic elements and multiple buffer elements
To execute function below:
From one first data of the NAND gate flash memory array one first page of loading to the Data buffer；
From first data portion of the Data buffer, by one first number of first data of the first page
First cache part of the cache buffer is copied to according to section；
First data segments of first data are established in first cache part of the cache buffer
One first error correcting code handles data；
Judge one first error correcting code state of the first error correcting code processing data；
First error correcting code, which is exported, from first cache part of the cache buffer handles data；
From second data portion of the Data buffer, by one second number of first data of the first page
Second cache part of the cache buffer is copied to according to section；
In the function equitant time of the output the first error correcting code processing data, Yu Suoshu cache buffer
Second cache part in, establish one second from second data segments of first data of the first page
Error correcting code handles data；
From the first error correcting code states of first error correcting code processing data and described the is established as described
Two error correcting codes handle a part of the step of data, determine one second error correction of one second data of a second page
Code state, second data include the first error correcting code processing data and second error correcting code processing number
According to；
The second error correcting code state is stored in a state buffer；
In the function equitant time of the output the first error correcting code processing data, from the NAND gate quick flashing
The data of one first continuous page are loaded into the Data buffer by formula memory array；
Second error correcting code, which is exported, from second cache part of the cache buffer handles data；
One first continuous page section of the data of first continuous page is counted from described the first of the Data buffer
According to first cache part for being partially copied to the cache buffer；
In the function equitant time of the output the second error correcting code processing data, from first continuous page
The first continuous page section of the data in face establishes third error correcting code processing data in the cache buffer
First cache part；
Judge a third error correcting code state of the third error correcting code processing data；
The third error correcting code, which is exported, from first cache part of the cache buffer handles data；
From second data portion of the Data buffer by one second continuous page of the data of first continuous page
Face section is copied to second cache part of the cache buffer；
In the function equitant time of the output third error correcting code processing data, in the cache buffer
Second cache part in, establish one the 4th from the second continuous page section of the data of first continuous page
Error correcting code handles data；
From the third error correcting code states of third error correcting code processing data and described the is established as described
Four error correcting codes handle a part of the step of data, judge one the 4th error correction of a third data of a third page
Code state, the third data include the third error correcting code processing data and the 4th error correcting code processing number
According to；
The 4th error correcting code state is stored in the state buffer；And
In the function equitant time of the output third error correcting code processing data, from the NAND gate quick flashing
The data of one second continuous page are loaded into the Data buffer by formula memory array.
5. a kind of memory reading method, suitable for continuously reading data from a digital memory device, which is characterized in that described
Digital memory device includes the NAND gate flash memory array and page buffer being mutually coupled, the page
Buffer is at least divided into a first part and a second part, and the memory reading method includes:
From one first data of one first page of NAND gate flash memory array access；
One first error correcting code processing number is established in the first part of the page buffer from first data
According to；
Judge one first error correcting code state of the first error correcting code processing data；
First error correcting code, which is exported, from the first part of the page buffer handles data；
In the equitant time of the step of with the output first error correcting code processing data, from first data in
One second error correcting code processing data are established in the second part of the page buffer；
The first error correcting code state of data is handled from first error correcting code and establishes described second in described
Error correcting code was handled in the time of the step of data, determined one second error correcting code of one second data of a second page
State, second data include the first error correcting code processing data and second error correcting code processing number
According to；
Store the second error correcting code state；
In the step of the first error correcting code processing data described with the output equitant time, from the NAND gate quick flashing
Formula memory array accesses the data of one first continuous page；
Second error correcting code is exported from the second part of the page buffer and handles data, and is deposited described in
The step of storing up the second error correcting code state exports the second error correcting code state；
In the step of the second error correcting code processing data described with the output equitant time, from first continuous page
The data in face establish third error correcting code processing data in the first part of the page buffer；
Judge a third error correcting code state of the third error correcting code processing data；
The third error correcting code, which is exported, from the first part of the page buffer handles data；
In the step of third error correcting code processing data described with the output equitant time, from first continuous page
The data in face establish one the 4th error correcting code processing data in the second part of the page buffer；
The third error correcting code state of data is handled from the third error correcting code and establishes the described 4th in described
When error correcting code handles the step of data, one the 4th error correcting code state of a third data of a third page is judged,
The third data include the third error correcting code processing data and the 4th error correcting code processing data；
Store the 4th error correcting code state；
In the step of third error correcting code processing data described with the output equitant time, from the NAND gate quick flashing
Formula memory array accesses the data of one second continuous page；And
The 4th error correcting code is exported from the second part of the page buffer and handles data, and from the storage
The step of 4th error correcting code state, exports the 4th error correcting code state.
6. a kind of memory reading method, suitable for continuously reading data from a digital memory device, which is characterized in that described
Digital memory device includes the NAND gate flash memory array and page buffer being mutually coupled, the page
Buffer is at least divided into a first part and a second part, and the memory reading method includes:
From one first data of one first page of NAND gate flash memory array access；
One first error correcting code processing number is established in the first part of the page buffer from first data
According to；
Judge one first error correcting code state of the first error correcting code processing data；
Export the first error correcting code processing data；
After the step of output first error correcting code handles data, from described the first of the page buffer
Part exports the first error correcting code processing data；
In the step of the first error correcting code processing data described with the output equitant time, from the NAND gate quick flashing
Formula memory array accesses one first continuous page data；
In the equitant time of the step of with the output first error correcting code processing data, from first data in
One second error correcting code processing data are established in the second part of the page buffer；
Determine one second error correcting code state of one second error correcting code processing data；
Export the second error correcting code state；
It is defeated from the second part of the page buffer after the step of output the second error correcting code state
Second error correcting code handles data out；
In the step of the second error correcting code processing data described with the output equitant time, from first continuous page
The data in face establish third error correcting code processing data in the first part of the page buffer；
Judge a third error correcting code state of the third error correcting code processing data；
Export the third error correcting code processing data；
After the step of output third error correcting code handles data, from described the first of the page buffer
Part exports the third error correcting code processing data；
In the step of third error correcting code processing data described with the output equitant time, from the NAND gate quick flashing
Formula memory array accesses the data of one second continuous page；And
In the step of third error correcting code processing data described with the output equitant time, from first continuous page
The data in face establish one the 4th error correcting code processing data in the second part of the page buffer.
7. memory reading method as claimed in claim 6, which is characterized in that the memory reading method further include:
It is handled with corresponding first error correcting code simultaneously, is exported the step of the output the first error correcting code state
One first spare area of data；
It is handled with corresponding second error correcting code simultaneously, is exported the step of the output the second error correcting code state
One second spare area of data；And
It is handled with the corresponding third error correcting code simultaneously, is exported the step of the output third error correcting code state
One third spare area of data.
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