CN103295647B - There is data copy method and the device of the memory array of redundant memory - Google Patents
There is data copy method and the device of the memory array of redundant memory Download PDFInfo
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Abstract
The invention discloses a kind of is such as copy the page copy operation writing back programming between the source page between this storage array of different section and an object page of this storage array.This group redundancy behavior such as multiple row group in the row of this this primary array of sector division and redundant array.This copies and writes back programming by the data Replica of data this source page part from this redundant array to this object page part of this primary array, and by the data Replica of data this source page part from this primary array to this object page part of this redundant array.
Description
Technical field
Technology of the present invention is stored in one has data in the memory array in redundant memory region about copying.
Background technology
One is such as copy the memory page replicate run writing back program command, is copy to the object page from the source page of storer, and does not need to shift the memory buffer that this copies data turnover integrated circuit external.But this page copy operation is the page buffer copying to IC interior from the source page of storer, and then from then on page buffer copy to the object page.
In the prior art, to a redundant memory mechanism (as shown in fig. 1), this defect row utilizes a redundant row to repair.It is quite simple that the copying of this prior art storage mechanism writes back programming mechanism, and display in fig. 2.Copy at this and write back in programming flow process, send one in the 1st step and copy and write back reading order.In the 2nd step, the data of source page from then on array are downloaded to internal pages impact damper.In the 3rd step, send one and copy and write back program command, it comprises input object page address.4th step is optionally, if if required, this internal buffer data from external source amendment or can increase.In the 5th step, send one and copy and write back programming initiation command.An in the end step, these internal buffer data can Direct Programming to the object page.
In this prior art, page addressing can be directed to by row redundancy circuit the redundant memory locations distributing to this primary array defect memory location again to the storage operation of defect memory position.Therefore, the storage operation being so addressed to defect memory position can perform on redundant memory locations.
But in a defect row, these defects can in full line or a part for this journey exists.In normal circumstances, most defect only can exist in a part for this journey, and the way of its less expensive is that a redundant row is divided into many reparation sections, and such as, shown in Fig. 3, it shows two redundancy section SEG1 and SEG2.In another example of Fig. 8, these redundancy sections SEG1, SEG2, SEG3 and SEG4 are divided into primary array and redundant array.First redundant row section can be used for reparation first defect row section, namely from block 0 to 255.Second redundant row section can be used for reparation second defect row section (from block 256 to 511), and the rest may be inferred by analogy for it.Technology described at present uses the latter that one redundant row is divided into many reparation sections.
To this multi session redundant system, copying of this prior art cannot be used to write back programming mechanism.One is such as copied the memory page replicate run writing back programming and can skip over row redundancy circuit, therefore, consequently, causes and also skips over the operation that relative defect memory address is directed to redundant memory address again.If a particular row of this memory array is the defective words of tool in source page, then from the data that copy of the defect row of source page be inefficent.Similarly, if a particular row of this storage array is the defective words of tool at the object page, then from the data that copy of the defect row of the object page be inefficent.
Because the locked memory pages replicate run defective addresses do not comprised in primary array is directed to redundancy in redundant array again replace address, create many mistakes from source page to the locked memory pages replicate run of the object page.
In one case, source page has the specific main address of a defect at the primary array of this source page, for example, at a particular row of the primary array of this source page.But the object page does not perhaps have the identical specific main address of a defect at the primary array of this object page, for example, at a particular row of the primary array of this object page.
In another case, the object page has the specific main address of a defect at the primary array of this object page, for example, at a particular row of the primary array of this object page; But source page does not perhaps have the identical specific main address of a defect at the primary array of this source page, for example, at a particular row of the primary array of this source page.
In still another case, source page and the object page have the identical specific main address of a defect at the primary array of this source page and the object page, for example, at the identical particular row of this source page with the primary array of the object page.But, this defect is perhaps repaired by the respective redundant array different piece at different redundant address, for example, in one first particular row reparation of the defect source page redundant array portion thus of the primary array part of this source page, and one second particular row reparation of defect object page redundant array portion thus in the primary array part of this object page.
To the another kind of prior art of this multi session redundant system, need page buffer just can become and do not have defective storer.In this storer, external data can pass in and out at the page buffer of this primary array.In this fetch program, page buffer data move to defect row when the fetch program closes to an end from redundant row.In this program, page buffer data move to redundant row when program starts from defect row.This mechanism is very simple.But some non-defective page buffer needs to pay a price.For example, a larger page buffer area can be used to this Critical Design criterion of releiving.
In order to solve the many problems in prior art, to this multi session redundant system, a kind of copying and write back programming mechanism newly can be provided in the following description.
Summary of the invention
An object of the present invention is to provide a kind of memory storage technology with storage array and control circuit.
This storage array is arranged to a primary array and is divided into multiple section, and a redundant array is divided into multiple section corresponding with this primary array.
One group of defective locations in one particular section of wherein this primary array is replaced by the redundant memory in a particular section of this redundant array of correspondence.
For example, storage array is arranged to rows and columns.This redundant array comprises one group of redundant row.The multiple row group of this group redundancy behavior in the row of this this primary array of sector division and redundant array.Redundant memory in this particular column group thus in redundant row of one group of defective locations in one particular column group of primary array replaces.In one embodiment, because redundant row is divided into multiple section, this redundant row can distribute to repair the defect in this primary array different rows, as long as these defects appear among different sections.
This control circuit is supported in the page copy operation in the plurality of section between the source page between this storage array of different section and an object page of this storage array, and this page copy operation can be to copy and writes back programming.In one embodiment, this copy writing back programming the data Replica of data this source page from this storage array is not needed to copy data in the impact damper outside this memory storage to this object page of this storage array.In another embodiment, this copies and writing back programming data this source page from this storage array is copied this object page in data to storage array, and perform following one of at least: Data Migration is gone out this memory storage or by Data Migration to this memory storage page.
This page copy operation by the Data Migration of this source page part in this redundant array in this object page part of this primary array, and/or by the Data Migration of this source page part in this primary array in this object page part of this redundant array.From this redundant array, the Data Migration of this source page part considers the defective source page Redundant binary number of tool in redundant memory source page to this object page part of this primary array, and in this primary array, the Data Migration of this source page part considers tool defective object page Redundant binary number in the redundant memory object page to this object page part of this redundant array.
Different embodiments also comprises page buffer, and this page buffer comprises a main page impact damper, and primary array is corresponding and a redundancy page buffer is corresponding with this redundant array therewith.For example, a locked memory pages has a specific size among this primary array and redundant array, and can be stored by the page buffer with suitable primary array page buffer and redundant array page buffer size.
In one embodiment, this page copy operation supported by this control circuit, and the data of a copy in this page buffer with this source page are had one or more change.
This page copy operation supported by this control circuit, and the data of a copy in this page buffer with this source page are had one or more change, and this source page Redundant binary number and this object page Redundant binary number are considered in this one or more change.
Different embodiments comprises a source page Redundant binary number and an object page Redundant binary number to repair defect respective in source page and the object page.This source page Redundant binary number is this group defective locations that the particular portion of the redundant memory of respective segments by this source page assigns to replace in the primary array of this source page, this group defective locations of replacing in the primary array of this object page and the particular portion that this object page Redundant binary number is the redundant memory of respective segments by this object page is assigned to.
Different embodiment comprises page buffer described herein and temporary register is corresponding with this redundancy page buffer.This temporary register provide extra memory location its can be assisted when control circuit operates.
Different embodiments has a multiple partial source page, a multiple partial object page, main addressing mechanism and redundant address mechanism.
This source page has and comprises a main source page in this primary array and the part of a redundancy source page in this redundant array.Defect in the main source page of primary array is by the redundancy source page reparation of redundant array.
This object page has and comprises a fundamental purpose page in this primary array and the part of a redundancy purpose page in this redundant array.Defect in the fundamental purpose page of primary array is by the redundancy purpose page reparation of redundant array.
This main addressing mechanism is shared by this main source page, this fundamental purpose page and this main page impact damper, makes the corresponding part in one of this main addressing mechanism main this main source page of address identification, this fundamental purpose page and this main page impact damper.For example, the main source page, this fundamental purpose page and this main page impact damper all have be such as that N is capable, position, byte or N number of address location of other memory cells.Then a main address i can the corresponding part of the main source page of identification primary array, the fundamental purpose page and main page impact damper between 1 to N.When this page copy operation, at the main address i of data Replica to the fundamental purpose page and the main address i of main page impact damper of the main address i of the main source page, it has improvement described herein.
This redundant address mechanism is shared by this redundancy source page, this redundancy purpose page, redundancy page buffer and temporary register, makes the corresponding part in this redundancy source page of a redundant address identification of this redundant address mechanism, this redundancy purpose page and this redundancy page buffer.For example, redundancy source page, this redundancy purpose page and this redundancy page buffer all have be such as that M is capable, position, byte or the M of other memory cells address location.Then a redundant address j between 1 to M can the redundancy source page in the redundant array of identification redundant array, the redundancy purpose page, redundancy page buffer and the temporary register in redundant array corresponding part.When this page copy operation, at the data Replica of the redundant address j of redundancy source page to redundant address j, the redundant address j of redundancy page buffer of the redundancy purpose page and the redundant address j of temporary register, it has improvement described herein.
This source page Redundant binary number uses the specific part of this redundancy source page to replace this group defective locations in this main source page, and it is the one or more main address that one or more redundant address by distributing this redundancy source page replace this group defective locations in this main source page.
This object page Redundant binary number uses the specific part of this redundancy purpose page to replace this group defective locations in this fundamental purpose page, and it is the one or more main address that one or more redundant address by distributing this redundancy purpose page replace this group defective locations in this fundamental purpose page.
In certain embodiments, this main address is identical for the part of this primary array in this storage array one phase colleague, and in the part of this redundant address for this redundant array in this redundant array one phase colleague be identical.
In different embodiments, this control circuit performs many by the many different operatings outside the page copy to page buffer and temporary register of source, such as by main source page copy to main page impact damper, and redundancy source page is copied to redundancy page buffer and temporary register.
In one embodiment, at least one specific main address of this control circuit from least one specific redundancy address transferring data of this temporary register to this main page impact damper, wherein this source page Redundant binary number uses at least one specific redundancy address of this redundancy source page to repair at least one specific main address of this main source page.
In one embodiment, at least one specific redundancy address of this control circuit from least one specific main address transferring data of this main page impact damper to this redundancy page buffer, wherein this object page Redundant binary number uses at least one specific redundancy address of this redundancy purpose page to repair at least one specific main address of this fundamental purpose page.One embodiment is in conjunction with above-mentioned two kinds of data batchmove.Another embodiment then with different order in conjunction with above-mentioned two kinds of data batchmove.
Another embodiment then adjusts data batchmove, if this source page Redundant binary number and this object page Redundant binary number repair main address identical in this source page and the object page.This control circuit, respond this source page Redundant binary number and this object page Redundant binary number and repair an identical address of this main source page and this fundamental purpose page, one second redundant address of data to this redundancy page buffer is transferred from one first redundant address of this temporary register, wherein this source page Redundant binary number uses this first redundant address of this redundancy source page and repairs this main identical address of this main source page, and this object page Redundant binary number uses this second redundant address of this redundancy purpose page and repairs this main identical address of this fundamental purpose page.
If its words occurred in previously described embodiment of transfer of another embodiment then omitted data.This control circuit, data at least one specific redundancy address to this redundancy page buffer is transferred from least one specific main address of this main page impact damper, except at this, at least one specific main address is contained in except the situation of this identical main address, wherein this object page Redundant binary number uses at least one specific redundancy address of this redundancy purpose page to repair at least one specific main address of this fundamental purpose page.
Another object of the present invention is to provide a kind of method of operational store, comprising:
Perform the page copy operation in multiple section between the source page between a storage array of different section and an object page of this storage array, this page copy operation by the Data Migration of this source page part in this section in this object page part of this primary array, and by the Data Migration of this source page part in this primary array in this object page part of this redundant array.
Many different embodiments are also described herein.
Accompanying drawing explanation
Fig. 1 is a redundant row repairing whole defect row.
Fig. 2 copies the process flow diagram writing back programming operation.
Fig. 3 shows the redundant row that is divided into multiple reparation section.
Fig. 4 copies the process flow diagram writing back programming operation, and it has the operation of internal data movement.
The diagram of Fig. 5 ~ Fig. 7 storage array and page buffer, show this and copy the step writing back programming operation, wherein storage array comprises a main storage array and a redundant storage array, and this page buffer comprises a main page impact damper and a redundancy page buffer.
Fig. 8 shows a storage array and is divided into multiple redundancy section, and it detects defect in this primary array of a particular section by the redundant array reparation in same sector.
Fig. 9 is presented at the source page Redundant binary number in a specific redundancy section, and the source page specific part wherein in this redundant array is assigned to one or more defects of repairing source page specific part in primary array.
Figure 10 is presented at the object page Redundant binary number in a specific redundancy section, and the object page specific part wherein in this redundant array is assigned to one or more defects of repairing object page specific part in primary array.
Figure 11 displaying duplication writes back a form of programming operation signal value in different step and in the different phase of different step.
Figure 12 is the calcspar copying page buffer and other circuit when writing back programming operation the 1st step, and data are transferred to temporary register from page buffer in this step, particularly from the page buffer part transfer comprising redundancy page buffer.
Figure 13 is the calcspar copying page buffer and other circuit when writing back programming operation the 2nd step, and data are transferred to page buffer from temporary register in this step, and it considers source page Redundant binary number.
Figure 14 ~ Figure 16 is the calcspar copying page buffer and other circuit when writing back programming operation the 3rd step, data are transferred in page buffer in this step, particularly be transferred to redundancy page buffer from main page impact damper, it considers object page Redundant binary number.
Figure 17 displaying duplication writes back a form of programming operation signal value in different step and in the different phase of different step, and its sequence of steps is different with the form of Figure 11.
Figure 18 is the calcspar copying page buffer and other circuit when writing back programming operation the 2nd step, data are transferred in page buffer in this step, particularly be transferred to redundancy page buffer from main page impact damper, it considers object page Redundant binary number, and the data that display is similar in Figure 13 distribute improvement.
Figure 19 shows the rough schematic view of integrated circuit according to an embodiment of the invention, and it comprises and carries out disclosed herein copying and write back programming operation and page buffer.
[main element symbol description]
750: integrated circuit;
700: array of non-volatile memory cells;
701: word-line decoder;
702: wordline;
703: line decoder and page buffer circuit;
704: bit line;
705: bus;
707: data bus;
706: sensing amplifier/data input structure;
709: programming, erasing and reading adjust bias voltage and copy and write back programming state mechanism;
708: bias voltage adjustment supply voltage;
711: Data In-Line;
715: DOL Data Output Line.
Embodiment
To this multi session redundant system, provide a kind of copying and write back programming mechanism newly in the diagram.Write back in programming mechanism in this new copying, add an extra step between step and final step the 5th.In the step that this is extra, this page buffer changes into from the reparation that source page is base the reparation that the object page is base.
Fig. 4 copies the process flow diagram writing back programming operation.For example, at a Sheffer stroke gate flash memory, this copies and writes back programming operation and directly copy a page and do not need from then on integrated circuit to read out data to another page.
First, reception one copies and writes back reading order.Data in this source page transfer to page buffer from array.In an example, after internal processes completes, data are not had to be read out.In certain embodiments, if there are these data of needs to be read out and to adjust afterwards.This source page is in one first redundancy section.Defect in the Primary memory of a specific redundancy section can by the redundant memory reparation in same redundant section.
Afterwards, send this to copy and write back program command series.Copy at this and write back in program command series, copy writing back order and first send, subsequently and then address input.Afterwards, if if required, data are issued.These data can be that error correction is added to this source page to source page or new data.At this data input phase, this page buffer data structure still can follow this first redundancy section to distribute.Then, this copies and writes back program command and be issued to start this programming operation.
Afterwards, the data in page buffer are adjusted to consider source page Redundant binary number and object page Redundant binary number.Consideration so solves many different problems.For example, in source page, the position of any defect is perhaps identical or different with the position of any defect in the object page.In another example, even the position of any defect is identical with the position of defect in the object page in source page, in redundant memory, the position of repair-deficiency is perhaps identical or different with the position in source page or the object page.
Afterwards, outside memory storage page buffer be copied to the object page.This object page is in one second redundancy section.Because source page and the object page are in different redundancy sections, can be different from redundant array to the distribution of primary array.For example, in the first redundancy section, one particular row of this redundant array repairs one or more defect in primary array, but in the second redundancy section, another particular row of this redundant array repair primary array go together mutually with particular row in one or more defects.In another example, in the second redundancy section, going together mutually with particular row of this redundant array does not distribute for repairing any defect, or primary array go together mutually with particular row in not there is any defect.The previous steps of adjustment page buffer considers situation like this.
Finally, complete this to copy and write back programming operation.
The diagram of Fig. 5 ~ Fig. 7 storage array and page buffer, show this and copy the step writing back programming operation, wherein storage array comprises a main storage array and a redundant storage array, and this page buffer comprises a main page impact damper and a redundancy page buffer.
The source page that Fig. 5 shows redundancy section 1 in storage array is copied to page buffer.Specifically, the data Replica so far main page impact damper in this source page primary array part, and the data Replica so far redundancy page buffer in source page redundant array portion.Afterwards, one in page buffer with source page is copied version.In one embodiment, a memory page is 256 bytes; In other examples, other size can be had.
The mode that version discusses with this place that copies that Fig. 6 is presented at source page in this page buffer adjusts.Afterwards, content in page buffer is considered source page Redundant binary number and object page Redundant binary number and is adjusted.
Fig. 7 show data from then on page buffer be transferred to the object page of redundancy section 3 in storage array.Specifically, in the primary array part of the so far object page of the data Replica in this main page impact damper, and in the redundant array portion of data Replica in this redundancy page buffer so far object page.Afterwards, one that has source page in the object page is copied version.
Fig. 8 shows a storage array and is divided into multiple redundancy section, and it detects defect in this primary array of a particular section by the redundant array reparation in same sector.
In this example arranges, primary array is divided into multiple redundancy section in the following manner.Redundancy section SEG1, SEG2, SEG3, SEG4 split primary array and redundant array two class.There is in other embodiment the redundancy section of different number.The block 0 ~ 255 of primary array is redundancy section 1, and the block 256 ~ 511 of primary array is redundancy section 2, and the block 512 ~ 767 of primary array is redundancy section 3, and the block 768 ~ 1023 of primary array is redundancy section 4.Other embodiment has the section of different number in different blocks.According to arrangement so, the redundant array reparation in the redundancy section that the defect in primary array one particular block can be distributed thus.Multiple redundancy section can raising efficiency, because a discrete cell of redundant array is for this reason such as a redundant row, can repair the defect of primary array in different redundancy section.
Fig. 9 is shown in the source page Redundant binary number in a specific redundancy section, and the source page specific part wherein in this redundant array is assigned to one or more defects of repairing source page specific part in primary array.
This source page is the redundancy section 1 being arranged in this storage array.The primary array part M3 of this source page and M6 has defect.These defects are replaced by redundant array portion R1 and R2 of the source page of source page Redundant binary number.Because of source page Redundant binary number for this reason, be such as read, programming or erasing etc. use the primary array part M3 of source page and the storage operation of M6 address, be in fact to be performed by redundant array portion R1 and R2 of its respective source page.
Figure 10 is shown in the object page Redundant binary number in a specific redundancy section, and the object page specific part wherein in this redundant array is assigned to one or more defects of repairing object page specific part in primary array.
This object page is the redundancy section 3 being arranged in this storage array.The primary array part M1 of this object page, M3 and M7 have defect.These defects are replaced by the redundant array portion R1 ~ R3 of the source page of object page Redundant binary number.Because of page Redundant binary number for this purpose, be such as read, the primary array part M1 of the application target page, the storage operation of M3 and M7 address such as programming or erasing, be in fact performed by the redundant array portion R1 ~ R3 of its respective object page.
Fig. 9 shows and considers that the copying from source page to the object page of source page Redundant binary number writes back an example of programming operation, and Figure 10 shows the example considering object page Redundant binary number.
Figure 11 displaying duplication writes back a form of programming operation signal value in different step and in the different phase of different step.
The meaning of unlike signal in Figure 11 is explained in following list.
YREDx: comprise YRED1 ~ YRED3, chooses R1 ~ R3;
YRED1: choose R1 as input/output data;
YRED2: choose R2 as input/output data;
YRED3: choose R3 as input/output data;
YDISABLE: by normal Y input/output data path anergy (when YREDx ≠ 0);
The Y redundancy cache circuit (comprising SEG1 ~ 4RED) of SEGxRED: section X;
SEG1RED: the cache circuit of section 1;
SEG2RED: the cache circuit of section 2;
SEG3RED: the cache circuit of section 3;
SEG4RED: the cache circuit of section 4;
The decoder circuit YADDR_PB of YPREDECODER:M1 ~ M8 routing;
YMUX: select input/output data path from R1 ~ R3 and M1 ~ M8;
YADDR_PB: the Y address (selecting from redundancy YADD and normal Y address) of page buffer;
YADDR: normal Y address;
Ymn: select M1 ~ M8.
These copy the different step that writes back in programming operation and describe in fig. 11 in different phase.In addition, these copy and write back different step in programming operation and describe at the calcspar of different phase also in Figure 12, Figure 13 and Figure 14 ~ Figure 16, its display page impact damper and copy other circuit write back in programming operation.
Page buffer in Figure 12, Figure 13 and Figure 14 ~ Figure 16 comprises a redundancy page buffer and main page impact damper.Redundancy page buffer comprises R1, R2, R3 part.And main page impact damper comprises M1, M2, M3, M4, M5, M6, M7, M8 part.In other examples, redundancy page buffer and/or main page impact damper can have the part of other numbers.
Temporary register in Figure 12, Figure 13 and Figure 14 ~ Figure 16 or redundancy buffer comprises TR1, TR2, TR3 part.The number of redundancy page buffer mates with the fractional numbers in temporary register.In other examples, the part of other numbers can be had in temporary register.
Describe in fig. 8 about copying the Short Description writing back programming operation, and the calcspar in Figure 12, Figure 13 and Figure 14 ~ Figure 16 describes.
When the 1st step, the live part R1 ~ R3 of redundancy page buffer is copied in temporary register TR1 ~ TR3 part.When the 2nd step, the live part of temporary register TR1 ~ TR3 is copied in the corresponding part of main page impact damper M1 ~ M8.The live part of temporary register TR1 ~ TR3 and the corresponding part of main page impact damper M1 ~ M8 are decided by source page Redundant binary number, and it is utilized by the defective locations of source page M1 ~ M8 the position R1 ~ R3 of the redundant memory of source page to replace.
In another example, the 2nd and the 3rd step is exchanged, such as, shown in following Figure 17.
Copy about this more detailed description writing back programming operation to be described in the calcspar of in the table in fig. 11 following and Figure 12 ~ Figure 16.
When the 1st step, the data of redundancy page buffer are stored in temporary register.The calcspar of page buffer and other circuit when Figure 12 is the 1st step.In fig. 12, circle 1 and circle 2 indicate respective extraction stage Load1 and Load2.
In this example, 2 part R1, R2 in this redundancy page buffer 3 part R1, R2, R3 are effective.So when the 1st step, two are extracted stage Load1 and Load2 and copy 2 live parts R1, R2 in redundancy page buffer to 2 part TR1, TR2 in temporary register 3 part TR1, TR2, TR3.In another example, the comparatively small part in this redundancy page buffer is effective, so need the less extraction stage.In another example, the more parts in this redundancy page buffer are effective, so need more to extract the stage.And in another example, it is effective for having different number part in this redundancy page buffer.
When extracting stage Load1, the R1 in redundancy page buffer is copied to the TR1 in temporary register.Because the R1 in redundancy page buffer is accessed, signal YRED1 is 1 and signal YRED2 and YRED3 is 0.Because at least one is 1 in signal YREDx, so signal YDISABLE is 1.Why do not need pipe YADDR_PB, because live part R1, R2 of picking out in step 1 in redundancy page buffer are enough.Because main page impact damper M1 ~ M8 is not accessed, Ymn is 0.The multiplexer MUX of YREDx chooses redundancy section circuit SEG1, live part R1, R2 in its access identification redundancy page buffer.Because main page impact damper M1 ~ M8 is not accessed, why do not need the multiplexer MUX of pipe YADDR_PB.The multiplexer MUX of YADDR_RED is YADDR, because whether any ongoing redundancy ratio same position comparatively decided in main page impact damper does not represent a defective locations of source page and the object page simultaneously.
When extracting stage Load2, the R2 in redundancy page buffer is copied to the TR2 in temporary register.Because the R2 in redundancy page buffer is accessed, signal YRED2 is 1 and signal YRED1 and YRED3 is 0.
In step 2, the data in temporary register are written in page buffer.Be so determined by source page Redundant binary number, the specific part of one group of defect in the primary array position M1 ~ M8 in source page by the redundant memory R1 ~ R3 of redundancy section SEG1 ~ SEG4 corresponding to source page replaces by it.In some cases, so also can be determined by object page Redundant binary number, the specific part of one group of defect in the primary array position M1 ~ M8 in source page by the redundant memory R1 ~ R3 of redundancy section SEG1 ~ SEG4 corresponding to the object page replaces by it.
In this example, 2 part TR1, TR2 in temporary register 3 part TR1, TR2, TR3 are effective.So in step 2,2 of temporary register part TR1, TR2 are passed among M1 ~ M8 part of the correspondence of main page impact damper by two write phase Write1 and Write2.But, in some cases, perhaps can be redirected to in R1 ~ R3 part of the correspondence of redundancy page buffer among the M1 ~ M8 part being passed to the correspondence of main page impact damper.Corresponding relation between redundancy page buffer R1 ~ R3 and main page impact damper M1 ~ M8 is determined by source page Redundant binary number, and the position of one group of defect in the primary array position M1 ~ M8 in source page by redundant memory R1 ~ R3 corresponding to source page replaces by it.
But source page Redundant binary number is replaced the position of one group of defect in the primary array position M1 ~ M8 in source page by redundant memory R1 ~ R3 corresponding to source page.If the position of any one M1 ~ M8 is present in source page Redundant binary number and object page Redundant binary number simultaneously, then can be redirected to in R1 ~ R3 part of the correspondence of redundancy page buffer among the M1 ~ M8 part being transferred to the correspondence of main page impact damper.R1 ~ R3 part of the correspondence of this redundancy page buffer determined by object page Redundant binary number.
In another example, the comparatively small part encumbrance certificate in temporary register, it needs less write phase.In another example, the more parts in temporary register retain data, and it needs more write phase.In another example, the different piece in temporary register retains data, and it needs different write phases.
The calcspar of page buffer and other circuit when Figure 13 is the 2nd step.In fig. 13, circle 1 and circle 2 indicate respective write phase Write1 and Write2.
When the 1st write phase Write1, the data in temporary register TR1 are written in redundancy page buffer R2.Position M3 in the main source page uses the R1 position of redundancy source page to repair by source page Redundant binary number.This source page Redundant binary number indicates the data of initial temporary register TR1 to be passed to the R3 position of main page impact damper.But the R2 position of the position M3 application target source page in the fundamental purpose page is repaired by object page Redundant binary number.Main address M3 shared with object page Redundant binary number by source page Redundant binary number.So replace the data in temporary register TR1 to be passed in redundancy page buffer R2.
When Figure 11 is shown in write phase Write1, the block schematic diagram of the redundant circuit of multi session.Shown in Figure 10 by the interior details of the redundant circuit of dotted line by the redundant circuit of dotted line in fig. 11.In the different memory page, redundant address and the corresponding relation of main address are stored in redundant circuit in different redundancy section, and this redundant circuit is also referred to as SEGxRED circuit.By providing normal Y address YADDR to multiplexer MUX, the address of this redundant circuit enable redundant memory response one coupling.Compare for Redundancy Match, this redundant circuit provides the Y address of a signal YADDR_RED and main address.In normal running, signal YADDR_RED chooses YADDR path.Under special circumstances, selected the fetching of SEGmREDYADDR is carried out SEGnRED Redundancy Match and is compared.For example, be shown in Figure 11, when the 1st write phase Write1 of the 2nd step, this SEG1RED redundant circuit exports YADDR_RED=main address M3 to SEG3RED redundant circuit and mates as redundant address.Afterwards, as shown in Figure 10, YRED2 be 1 because SEG3RED redundant circuit in main address M3 repaired by redundant address R2.
Because Data Migration is in redundancy page buffer R2, signal YRED2 is 1 and signal YRED1 and YRED3 is 0.Because at least one is 1 in signal YREDx, so signal YDISABLE is 1.YADDR_PB is M3, because for source page, SEG1RED circuit, corresponding main address M3 has redundant address R1/TR1.Because main page impact damper M1 ~ M8 is not accessed, Ymn is 0.The multiplexer MUX of YREDx chooses redundancy section circuit SEG3, and for the object page, corresponding main address M3 has redundant address R2.The multiplexer MUX of YADDR_RED is SEG1, because SEG1RED circuit, corresponding redundancy TR1 has main address M3.The multiplexer MUX of YADDR_RED is M3, because ongoing redundancy ratio comparatively decides the defective locations whether identical main address M3 represents source page and the object page simultaneously.
When the 2nd write phase Write2, the data in temporary register TR2 are passed to main page impact damper and obtain in M6.Position M6 in the main source page uses the R2 position of redundancy source page to repair by source page Redundant binary number.Data in this source page Redundant binary number instruction temporary register TR2 are passed to main page impact damper and obtain in M6.
Because be not accessed in the data in the position R1 ~ R3 of redundancy page buffer, signal YRED1, YRED2 and YRED3 are 0.Because not having the signal of YREDx to be 1, YDISABLE is 0.YADDR_PB is M6, because to SEG1RED circuit, for source page, the redundant address of corresponding main address M6 is R2/TR2.Because main page buffer address M6 is written into, Ymn is M6.The multiplexer MUX of YADDR_PB is SEG3, for the object page, checks whether that have identical address is shared by source page and the object page simultaneously.The multiplexer MUX of YADDR_PB is SEG1, because SEG1RED circuit, the main address of corresponding redundant address TR2 is M6.YADDR_RED is M6, because ongoing redundancy ratio comparatively decides the defective locations whether identical main address M6 represents source page and the object page simultaneously.
When step 3, M1 ~ M8 part of main page impact damper is copied in one of corresponding redundancy buffer R1 ~ R3 part.Corresponding between redundancy register location R1 ~ R3 with main page buffer positions M1 ~ M8 is determined by object page Redundant binary number, and it is replaced by the redundant memory address R1 ~ R3 in the object page one group of defect of object page location M1 ~ M8.But, if when the main page address M1 ~ M8 in both source page Redundant binary number and object page Redundant binary number is repaired, from M1 ~ M8 partial replication of main page impact damper or transfer to corresponding redundancy buffer R1 ~ R3 part and can skip; Because in such case, occur in step 2 from M1 ~ M8 partial replication of main page impact damper or the operation of transferring to corresponding redundancy buffer R1 ~ R3 part.
In this example, three part R1 all in redundancy page buffer, R2, R3 are effective.So when step 3, three fetch phases READ1, READ2, READ3 read M1 ~ M8 part of main page impact damper, and it is present in object page Redundant binary number.In addition, when step 3, after each fetch phase, data are write one of corresponding redundancy buffer R1 ~ R3 part from main page impact damper by a write phase.Corresponding between redundancy register location R1 ~ R3 with main page buffer positions M1 ~ M8 is determined by object page Redundant binary number, and it is replaced by the redundant memory address R1 ~ R3 in the object page one group of defect of object page location M1 ~ M8.But, if when the main page address M1 ~ M8 in both source page Redundant binary number and object page Redundant binary number is repaired, from M1 ~ M8 partial replication of main page impact damper or transfer to corresponding redundancy buffer R1 ~ R3 part and can skip.Therefore, in this example, the 1st write phase Write1 is after the 1st fetch phase READ1, and the 3rd write phase Write3 after the 3rd fetch phase READ3, but skips the 2nd write phase Write2 after the 2nd fetch phase READ2.
The page buffer of stage READ1 and Write1 and the calcspar of other circuit when Figure 14 is the 3rd step.
When the 1st fetch phase Read1, the data of the M1 position of main page impact damper are read.When the 1st write phase Write1, the data of the M1 position of main page impact damper are written in redundancy page buffer position R1.Position M1 in the fundamental purpose page uses the R1 position of the redundancy purpose page to repair by object page Redundant binary number.Can describe in detail the 1st fetch phase Read1 and the 1st write phase Write1 more afterwards.
When the 1st fetch phase Read1, because be not accessed in the data in the position R1 ~ R3 of redundancy page buffer, signal YRED1, YRED2 and YRED3 are 0.Because not having the signal of YREDx to be 1, YDISABLE is 0.YADDR_PB is M1, because to SEG3RED circuit, for the object page, the redundant address of corresponding main address M1 is R1.Because main page buffer address M1 is read, Ymn is M1.The multiplexer MUX of YREDx chooses redundancy section circuit SEG3, for the object page.The multiplexer MUX of YADDR_PB is SEG3, because SEG3RED circuit, the main address of corresponding redundant address R1 is M1.YADDR_RED multiplexer MUX be YADDR because at present not ongoing redundancy ratio comparatively decides the defective locations whether identical main address represents source page and the object page simultaneously.
When the 1st write phase Write1, because Data Migration is in redundancy page buffer R1, signal YRED1 is 1 and signal YRED2 and YRED3 is 0.Because at least one is 1 in signal YREDx, so signal YDISABLE is 1.YADDR_PB is M1, because for the object page, SEG3RED circuit, corresponding main address M1 has redundant address R1.Because main page impact damper M1 ~ M8 is not accessed, Ymn is 0.The multiplexer MUX of YREDx chooses redundancy section circuit SEG3, and for the object page, corresponding main address M1 has redundant address R1.The multiplexer MUX of YADDR_RED is YADDR, because do not have ongoing redundancy ratio at present comparatively decide the defective locations whether identical main address represents source page and the object page simultaneously.
The page buffer of stage READ2 and the calcspar of other circuit when Figure 15 is the 3rd step.
When the 2nd fetch phase Read2, the data of the M3 position of main page impact damper are read.Now do not have the 2nd write phase Write2, because it is skipped.The details of the 2nd fetch phase Read2 is roughly identical with the 1st fetch phase Read1, except the main page buffer positions be read.
The page buffer of stage READ3 and Write3 and the calcspar of other circuit when Figure 16 is the 3rd step.
When the 3rd fetch phase Read3, the data of the M7 position of main page impact damper are read.When the 3rd write phase Write3, the data of the M7 position of main page impact damper are written in redundancy page buffer position R3.Position M7 in the fundamental purpose page uses the R3 position of the redundancy purpose page to repair by object page Redundant binary number.The details of the 3rd fetch phase Read3 is roughly identical with the 1st fetch phase Read1, except the main page buffer positions be read.The details of the 3rd write phase Write3 is roughly identical with the 1st write phase Write1, except the redundancy page buffer position be written into.
Figure 17 displaying duplication writes back a form of programming operation signal value in different step and in the different phase of different step, and its sequence of steps is different with the form of Figure 11.
Below Figure 11 and Figure 17 is compared.Step 1 is identical in Figure 11 and Figure 17.Step 2 in Figure 17 is the steps 3 in Figure 11.But the step 2 in Figure 17 comprises the 2nd write phase Write2 after the 2nd fetch phase Read2.Step 3 in Figure 17 is the steps 2 in Figure 11.
The page buffer of stage READ2 and Write2 and the calcspar of other circuit when Figure 18 is the 2nd step.Step 2 in Figure 18 is slightly made an amendment at the step 3 in Figure 11, comprises the 2nd write phase Write2 after the 2nd fetch phase Read2.
Figure 19 shows the rough schematic view of integrated circuit according to an embodiment of the invention, and it comprises and carries out disclosed herein copying and write back programming operation and page buffer.
Wherein integrated circuit 750 comprises storage array 700.One word-line decoder 701 couples with many wordline 702 along the arrangement of storage array 700 column direction and electrically links up.One bit line (OK) code translator and page buffer circuit 703 couple with the multiple bit lines 704 along the arrangement of storage array 700 line direction and electrically link up.Address is supplied to bit line decoder 701 and bit line decoder and page buffer circuit 703 by bus 705.Sensor circuit (induction amplifier) in square 706 and data input structure, comprise voltage and/or current source couples via data bus 707 and bit line decoder and page buffer circuit 703.Data to be supplied to the data input structure in square 706 via Data In-Line 711 in the inner or outer data source of integrated circuit 750 by the input/output end port on integrated circuit 750 or other.Can comprise other circuit in integrated circuit 750, such as general object processor or specific purposes application circuit, or block combiner is to provide the system single chip supported by memory array 700 function.Data, via DOL Data Output Line 715, are provided to input/output end port on integrated circuit 750 or other data terminals of integrated circuit 750 inner/outer from the induction amplifier square 706.
Controller 709 used in the present embodiment is the use of bias voltage adjustment state machine, to control to adjust voltage and electric current source of supply 708 to apply the application of bias voltage adjustment supply voltage, to carry out many operations described herein by bias voltage.These operations can comprise the reading of wordline and bit line, programming, erasing, erase verification and program verification voltage and/or electric current.This controller 709 also can perform to copy and write back programming operation, source page Redundant binary number when the one or more data of its consideration in bit line decoder and page buffer circuit 703 change and object page Redundant binary number.This controller 709 can utilize specific purposes logical circuit and apply, as well known to the skilled person.In alternative embodiments, this controller 709 includes general object processor, and it can make in same integrated circuit, to perform the operation of a computer program and control device.In another embodiment, this controller 709 is combined by specific purposes logical circuit and general object processor.
For purposes of clarity, in different embodiments, this noun " copies " recasting being used to represent identical data in source with object.In different embodiments, this noun " transfer " is used to represent data from source to the recasting of identical data between object, and wherein source data perhaps can maybe can not change.
The preferred embodiments of the present invention and example are open in detail as above, but should be appreciated that above-mentioned example is only as example, are not used to the scope limiting patent.With regard to those skilled in the art, from modifying and combination to correlation technique according to claim easily.
Claims (23)
1. a memory storage, comprises:
One storage array, is arranged to:
One primary array is divided into multiple section, and it is capable that this primary array comprises multiple primary array; And
One redundant array, comprises multiple redundant array capable, and it is corresponding with this primary array that this redundant array is divided into multiple section;
One group of defective locations in one particular section of wherein this primary array is replaced by the redundant memory in a particular section of this redundant array of correspondence, this group defective locations is the part that in primary array, multiple primary array is capable, further, this part is less than the capable quantity of redundant array;
Control circuit, support the page copy operation between a source page of this storage array and an object page of this storage array, the section that this source page is different in the plurality of section with this object page, this source page is arranged in primary array and redundant array, this object page is arranged in primary array and redundant array, this page copy operation by the Data Migration of this source page part in this redundant array in this object page part of this primary array.
2. memory storage according to claim 1, comprising:
Wherein this page copy operation copies to write back programming operation, and its this source page from this primary array copies this object page in data to primary array and do not need Data Migration to pass in and out this memory storage.
3. memory storage according to claim 1, comprising:
Wherein this page copy operation copies to write back programming operation, its this source page from this storage array copies this object page in data to storage array, and perform following one of at least: Data Migration is gone out this memory storage or by Data Migration to this memory storage.
4. memory storage according to claim 1, comprising:
Wherein this primary array is arranged to rows and columns, this redundant array comprises one group of redundant row, and this sector division becomes this group redundant row of these row of this primary array and this redundant array to be divided into the row of many groups, one group of defective locations in the row of a particular group of this primary array is replaced by the redundant memory in the row of this particular group of this redundant array.
5. memory storage according to claim 1, also comprises:
One page buffer circuit, comprises that a main page impact damper is corresponding with this primary array and a redundancy page buffer is corresponding with this redundant array, wherein
This control circuit, supports this page copy operation, and the data of a copy in this page buffer with this source page are had one or more change.
6. memory storage according to claim 1, also comprises:
One page buffer circuit, comprises that a main page impact damper is corresponding with this primary array and a redundancy page buffer is corresponding with this redundant array, wherein
One source page Redundant binary number uses the specific part of this redundant memory of the corresponding redundancy section of this source page to replace this group defective locations in this primary array of this source page;
One object page Redundant binary number uses the specific part of this redundant memory of the corresponding redundancy section of this object page to replace this group defective locations in this primary array of this object page;
This control circuit, supports this page copy operation, and the data of a copy in this page buffer with this source page are had one or more change, and this source page Redundant binary number and this object page Redundant binary number are considered in this one or more change.
7. memory storage according to claim 1, also comprises:
One page buffer circuit, comprises that a main page impact damper is corresponding with this primary array and a redundancy page buffer is corresponding with this redundant array; And
Temporary register is corresponding with this redundancy page buffer, wherein
This source page has and comprises a main source page in this primary array and the part of a redundancy source page in this redundant array;
This object page has and comprises a fundamental purpose page in this primary array and the part of a redundancy purpose page in this redundant array;
One main addressing mechanism is shared by this main source page, this fundamental purpose page and this main page impact damper, makes the corresponding part in one of this main addressing mechanism main this main source page of address identification, this fundamental purpose page and this main page impact damper;
One redundant address mechanism is shared by this redundancy source page, this redundancy purpose page, this redundancy page buffer and this temporary register, makes the corresponding part of this redundancy source page of a redundant address identification of this redundant address mechanism, this redundancy purpose page, this redundancy page buffer and this temporary register;
One source page Redundant binary number uses the specific part of this redundancy source page to replace this group defective locations in this main source page, and it is the one or more main address that one or more redundant address by distributing this redundancy source page replace this group defective locations in this main source page;
One object page Redundant binary number uses the specific part of this redundancy purpose page to replace this group defective locations in this fundamental purpose page, and it is the one or more main address that one or more redundant address by distributing this redundancy purpose page replace this group defective locations in this fundamental purpose page.
8. memory storage according to claim 7,
Wherein the part of this main address for this primary array in this storage array one phase colleague is identical; And
Wherein the part of this redundant address for this redundant array in this redundant array one phase colleague is identical.
9. memory storage according to claim 7, wherein this control circuit supports this page copy operation by following steps:
Copy this source page to this page buffer and this temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register; And then
At least one specific main address from least one specific redundancy address transferring data of this temporary register to this main page impact damper, wherein this source page Redundant binary number uses at least one specific redundancy address of this redundancy source page to repair at least one specific main address of this main source page.
10. memory storage according to claim 7, wherein this control circuit supports this page copy operation by following steps:
Copy this source page to this page buffer and this temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register; And then
At least one specific redundancy address from least one specific main address transferring data of this main page impact damper to this redundancy page buffer, wherein this object page Redundant binary number uses at least one specific redundancy address of this redundancy purpose page to repair at least one specific main address of this fundamental purpose page.
11. memory storages according to claim 7, wherein this control circuit supports this page copy operation by following steps:
Copy this source page to this page buffer and this temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register;
From one first group of transfer data of one or more specific redundancy addresses of this temporary register to one first group of the one or more specific main address of this main page impact damper, wherein this source page Redundant binary number uses this first group of one or more specific redundancy addresses of this redundancy source page to repair this first group of the one or more specific main address of this main source page; And then
From one second group of transfer data of the one or more specific main address of this main page impact damper to one second group of one or more specific redundancy addresses of this redundancy page buffer, wherein this object page Redundant binary number uses this second group of one or more specific redundancy addresses of this redundancy purpose page to repair this second group of the one or more specific main address of this fundamental purpose page.
12. memory storages according to claim 7, wherein this control circuit supports this page copy operation by following steps:
Copy this source page to this page buffer and this temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register;
From one first group of transfer data of the one or more specific main address of this main page impact damper to one first group of one or more specific redundancy addresses of this redundancy page buffer, wherein this object page Redundant binary number uses this first group of one or more specific redundancy addresses of this redundancy purpose page to repair this first group of the one or more specific main address of this fundamental purpose page; And then
From one second group of transfer data of one or more specific redundancy addresses of this redundancy page buffer to one second group of the one or more specific main address of this main page impact damper, wherein this source page Redundant binary number uses this second group of one or more specific redundancy addresses of this redundancy source page to repair this second group of the one or more specific main address of this main source page.
13. memory storages according to claim 7, wherein this control circuit supports this page copy operation by following steps:
Copy this source page to this page buffer and this temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register;
Respond this source page Redundant binary number and this object page Redundant binary number and repair an identical address of this main source page and this fundamental purpose page, one second redundant address of data to this redundancy page buffer is transferred from one first redundant address of this temporary register, wherein this source page Redundant binary number uses this first redundant address of this redundancy source page and repairs this main identical address of this main source page, and this object page Redundant binary number uses this second redundant address of this redundancy purpose page and repairs this main identical address of this fundamental purpose page.
14. memory storages according to claim 7, wherein this control circuit supports this page copy operation by following steps:
Copy this source page to this page buffer and this temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register;
Respond this source page Redundant binary number and this object page Redundant binary number and repair an identical address of this main source page and this fundamental purpose page, one second redundant address of data to this redundancy page buffer is transferred from one first redundant address of this temporary register, wherein this source page Redundant binary number uses this first redundant address of this redundancy source page and repairs this main identical address of this main source page, and this object page Redundant binary number uses this second redundant address of this redundancy purpose page and repairs this main identical address of this fundamental purpose page, and then
Data at least one specific redundancy address to this redundancy page buffer is transferred from least one specific main address of this main page impact damper, except at this, at least one specific main address is contained in except the situation of this main identical address, wherein this object page Redundant binary number uses at least one specific redundancy address of this redundancy purpose page to repair at least one specific main address of this fundamental purpose page.
15. memory storages according to claim 1, wherein:
In this primary array of this page copy operation, the Data Migration of this source page part is in this object page part of this redundant array.
The method of 16. 1 kinds of operational stores, comprising:
The one group of defective locations being arranged in the particular section comprising the capable primary array of multiple primary array is replaced by the redundant memory that comprises a corresponding particular section of the capable redundant array of multiple redundant array, this group defective locations is the part that in primary array, multiple primary array is capable, further, this part is less than the capable quantity of redundant array;
Perform the page copy operation be separated into by this storage array in by a storage array in multiple section between the source page between this storage array of different section and an object page of this storage array, this source page is arranged in primary array and redundant array, the object page is arranged in primary array and redundant array, this page copy operation comprises the Data Migration of this source page part in this redundant array to the jump operation in this object page part of this primary array, wherein this jump operation is the operation before the stage that the page of data in page buffer is copied to this object page.
17. methods according to claim 16, comprising:
Wherein this page copy operation copies to write back programming operation, and its this source page from this primary array copies this object page in data to primary array and do not need to copy data in the impact damper outside this memory storage.
18. methods according to claim 16, comprising:
Wherein this page copy operation copies to write back programming operation, and its this source page from this primary array copies this object page in data to primary array and do not need Data Migration to pass in and out this memory storage.
19. methods according to claim 16, comprising:
Wherein this primary array is arranged to rows and columns, this redundant array comprises one group of redundant row, and this sector division becomes these row of this primary array and this group redundant row of this redundant array is divided into the row of many groups, one group of defective locations in the row of a particular group of this primary array is replaced by the redundant memory in the row of this particular group of this redundant array.
20. methods according to claim 16,
Wherein this page copy operation, the data of the page buffer in this storage array are carried out one or more change, this page buffer has of this source page and copies version, this source page Redundant binary number and this object page Redundant binary number are considered in this one or more change, this source page Redundant binary number uses this redundant memory specific part of a respective segments of this source page to replace this group defective locations in a primary array of this source page, and this object page Redundant binary number uses this redundant memory specific part of this object page to replace this group defective locations in a primary array of this object page.
21. methods according to claim 16, wherein this page copy operation performs:
Copy this source page to this page buffer and a temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register; And then
At least one specific main address from least one specific redundancy address transferring data of this temporary register to this main page impact damper, wherein this source page Redundant binary number uses at least one specific redundancy address of this redundancy source page to repair at least one specific main address of this main source page.
22. methods according to claim 16, wherein this page copy operation performs:
Copy this source page to this page buffer and a temporary register, make this main source page be copied to this main page impact damper and this redundancy source page is copied to this redundancy page buffer and this temporary register; And then
At least one specific redundancy address from least one specific main address transferring data of this main page impact damper to this redundancy page buffer, wherein this object page Redundant binary number uses at least one specific redundancy address of this redundancy purpose page to repair at least one specific main address of this fundamental purpose page.
23. methods according to claim 16, wherein in this primary array of this page copy operation the Data Migration of this source page part in this object page part of this redundant array.
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