CN103871447B - NAND gate flash memory array and chip and its access, reading and management method - Google Patents

Abstract

The invention discloses a kind of NAND gate flash memory array and chip and its access, reading and management method, it is associated with and can realize on the chip of storage arrangement itself for the creation of inquiry table of bad block mapping and the specific function of use, namely on the additional circuit of identical chips, or even in the instruction of storage arrangement and control logic, to realize the function of inquiry table, to reduce burden.Furthermore, the function of realizing inquiry table on chip can be so that the function of inquiry table instructs with other and the function of control logic is closely integrated, so that NAND gate flash memory can read the higher new command of feature such as instruction and its change using such as continuous page.

Description

NAND gate flash memory array and chip and its access, reading and management method

Technical field

The invention relates to digital memory device, and in particular to the NAND gate flash memory on chip (NAND flash memory) and its managing damage block method.

Background technology

Due to significant advantage on cost, NAND gate flash memory little by little becomes the main flow in market.Additionally, with non- Door flash memory is applicable to be interfaced to including traditional NAND gate simplifies foot position (low pin count) serial circumference interface Multiple different types of interfaces such as (Serial Peripheral Interfaces, SPI).

Memory array is organized as multiple blocks (block) by NAND gate flash memory architecture, and each block has Several pages (page).The page length of standard includes 512 bytes (bytes), 2048 bytes and 4096 bytes.Each Several extra byte (usually 16/64/128 byte) in the page may be used to store error-correcting code (error Correcting code checksum, ECC) check summation (checksum) and sometimes may be used to store files data (metadata).

Managing damage block is commonly executed on NAND gate flash memory.Such memorizer sensitive for damages Block status Impact, bad block state includes the memory cell that block has inefficacy during fabrication, and makes storage due to reuse The memory cell of the inefficacy caused by guarantee for returns.Managing damage block is typically by the device driver in host side operating system Software or independent nonshared control unit chip are executing.When the logical blocks that high order software access damages, device driver Or the logical blocks of damage can be mapped to good physical blocks using bad block mapping table by controller, described damage Block mapping table commonly referred to as inquiry table (look-up table, LUT).The function of inquiry table is to collect unmapped physics Block address is to damage the bad logical block addresses (logical block address, LBA) in area and be mapped as good block The set linking between physical block address (physical block address, PBA).

The use of inquiry table is effective for some usual instructions of the NAND gate flash memory device of standard, for example Read the instruction of the page.And some instruction be then can by limit instruction in specific block sequentially reading and look into being compatible to Complete in the case of the use of inquiry table, instruction is read in such as serial.

However, typically in software or hardware, the function of bad block inquiry table must be using master control set or outside control Device processed is realizing it is thus possible to the burden on software development and hardware spending can be made to increase.

Content of the invention

The invention provides a kind of NAND gate flash memory array and chip and its access, reading and management method, its (on chip) function of bad block inquiry table can be realized on the chip of storage arrangement itself.

One embodiment of the invention is a kind of method of access NAND gate flash memory array.NAND gate flash memory battle array Row have user addressable area, and NAND gate flash memory array is implemented on chip.Chip is in order to read, sequencing And the NAND gate flash memory array of part of erasing.The method of described access NAND gate flash memory array includes： Identification in order to access the logical block addresses of NAND gate flash memory array, logical block addresses by complete be used for erasing deposit Take, and logical block addresses are aided with page address portion and are used for reading access and sequencing access；There is NAND gate Logical block addresses are obtained to the physical areas replacing block in user addressable area on the chip of flash memory array The mapping of block address；And access NAND gate flash memory array using the physical block address replacing block.

Another embodiment of the present invention is to carry out the side of continuous page read operation in a kind of flash memory chip in NAND gate Method, wherein NAND gate flash memory chip have NAND gate flash memory array and page buffer.Page buffer bag Include Data buffer and cache buffer.The side of continuous page read operation is carried out on the described flash memory chip in NAND gate Method includes：On the chip with NAND gate flash memory array maintain inquiry table buffer, inquiry table buffer store to A few logic damage block address and at least one physics corresponding to described logic damage block address replace block ground Location；Multiple caches from cache buffer keep in partly seamless and continuously output data, and Data buffer is organized as right Part should be kept in multiple data that the plurality of cache of cache buffer keeps in part；Set up in order to access NAND gate quick flashing The logical page address of memory array, logical page address includes logical block addresses part；Institute in inquiry table buffer State search in logic damage block address described logic damage block address one of them and logical block addresses part between Whether meet；When the first cache in keeping in partly from the plurality of cache keeps in part output data, from cache buffer In corresponding part transfer data to second cache keep in part, second cache keep in is partially different than the first cache temporary storage part Point；After the first cache keeps in part output data and transfer data keeps in the step of part to the second cache, in the second cache Keep on partly and carry out error-correcting code calculating；Keep in part output data in the first cache and transfer data is temporary to the second cache After the step of nonresident portion, when search step described in logic damage block address all do not meet with logical block addresses part When, from NAND gate flash memory array, page of data is read in Data buffer using logical page address, and ought search When one of them of logic damage block address described in target-seeking step and logic area address part meet, taken using described physics Page of data is read in Data buffer by one of them for block address, wherein said physics replace block address described its One of corresponding to meet logical block addresses part described logic damage block address described one of them；And when from When second cache keeps in part output data, shift data to except the second cache temporary storage part from the corresponding part of Data buffer Point remaining the plurality of cache keep in part one of them, and to remaining the plurality of cache keep in part described in its One of carry out this error-correcting code calculating.

Another embodiment of the present invention is a kind of method carrying out page read operation in flash memory chip in NAND gate, its Middle NAND gate flash memory chip has NAND gate flash memory array and page buffer.Page buffer includes data Buffer and cache buffer.The described method carrying out page read operation in NAND gate flash memory chip includes： Inquiry table buffer is maintained on the chip with NAND gate flash memory array, inquiry table buffer stores at least one and patrols Collect bad block address and at least one physics corresponding to described logic damage block address replaces block address；Set up and use To access the logical page address of NAND gate flash memory array, logical page address includes logical block addresses part；? One of them and logic of described logic damage block address is searched in the described logic damage block address of inquiry table buffer Whether meet between block address part；Using described physics replace block address one of them from NAND gate flash memory In array, page of data is read in Data buffer, wherein said physics replace block address described one of them corresponding to symbol The described logic damage block address of logical block address part described one of them；And carry out on page buffer Error-correcting code calculates.

Another embodiment of the present invention is to carry out the side of continuous page read operation in a kind of flash memory chip in NAND gate Method, wherein NAND gate flash memory chip have NAND gate flash memory array and page buffer.Described with non- The method carrying out continuous page read operation in door flash memory chip includes：In the core with NAND gate flash memory array Inquiry table buffer is maintained on piece, inquiry table buffer stores at least one logic damage block address and patrols corresponding to described At least one physics collecting bad block address replaces block address；Set up in order to access patrolling of NAND gate flash memory array Collect page address, logical page address includes logical block addresses part；Described logic damage block in inquiry table buffer Whether one of them searching described logic damage block address in address meets and logical block addresses part between；Work as search Step described in logic damage block address and logical block addresses part when all not meeting, using logical page address from In not gate flash memory array, page of data is read in Data buffer, and work as logic damage area described in the step searched When one of them of block address is met with logic area address part, using described physics replace block address one of them by number Read in Data buffer according to the page, wherein said physics replace block address described one of them corresponding to meeting logical blocks The described logic damage block address of address part described one of them；Mistake is carried out to the page of data in page buffer Correcting code calculates；And when error-correcting code calculates instruction and cannot correct page read error, if institute in the step searched State logic damage block address all not meeting with logical block addresses part, update continuous page using logical page address and read Bad block address register, and if logic damage block address described in the step searched one of them with this logic Regional address part meets, and reads bad block ground using one of them this continuous page of renewal that described physics replaces block address Location buffer, wherein said physics replace block address described one of them corresponding to the institute meeting logical block addresses part State logic damage block address described one of them.

Another embodiment of the present invention is a kind of NAND gate flash memory chip, including NAND gate flash memory array, row Decoder, page buffer, row decoder, i/o controller, state buffer, continuous page read bad block ground Location buffer, instruction registor, address register, inquiry table buffer, control logic circuit.It is fast that column decoder couples NAND gate Flash memory array.Page buffer couples NAND gate flash memory array.Row decoder couples page buffer.Input/ O controller couples row decoder.State buffer couples i/o controller.Continuous page reads bad block address Buffer couples i/o controller.Instruction registor couples i/o controller.Address register couples input/defeated Go out controller.Inquiry table buffer couples i/o controller.Control logic circuit couples column decoder, row decoder, page Face buffer, state buffer, continuous page read bad block address register, instruction registor, address register and Inquiry table buffer.

Another embodiment of the present invention is a kind of method of the managing damage block for NAND gate flash memory array, with Not gate flash memory array is implemented on chip.The described managing damage block for NAND gate flash memory array Method includes：Inquiry table buffer is maintained on the chip with NAND gate flash memory array；In using the first damage area During the logical block addresses of block access the user access of NAND gate flash memory array, detect the first bad block；With And the inquiry table buffer on access chip is with by the physics of the logical block addresses of the first bad block to the first replacement block The mapping of block address stores to NAND gate flash memory array.

Another embodiment of the present invention is a kind of method of access NAND gate flash memory array.NAND gate flash memory Array is implemented on chip.Chip is in order to read, the NAND gate flash memory array of sequencing and part of erasing.Described The method of access NAND gate flash memory array includes：Identification is in order to access the logical blocks of NAND gate flash memory array Address, logical block addresses are used for, by complete, access of erasing, and logical block addresses are aided with page address portion and are used for Read access and sequencing access；Inquiry table from the chip with NAND gate flash memory array obtains logical blocks Address to corresponding replace block physical block address mapping, when NAND gate flash memory array be standard read, When in the service of sequencing and operation of erasing, inquiry table can be accessed by user, and wherein inquiry table damages area in order to store The mapping of the physical block address to replacement block for the logical block addresses of block；And using the corresponding physical areas replacing block Block address accesses NAND gate flash memory array.

It is that the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings It is described in detail below.

Brief description

Fig. 1 is the function block schematic diagram of NAND gate flash memory device.

Fig. 2 is the organizational structure of NAND gate flash memory array and the inquiry table being associated with NAND gate flash memory Schematic diagram.

Fig. 3 is the flow chart of steps of an implementation of initial interrogation table.

Fig. 4 is the flow chart of steps of the page read operation using bad block mapping.

Fig. 5 is the flow chart of steps of the continuous page read operation using bad block mapping.

Fig. 6 is the flow chart of steps of the addressable continuous page read operation using bad block mapping.

Fig. 7 is the flow chart of steps of the programming operations using bad block mapping.

Fig. 8 is the flow chart of steps of the operation of erasing using bad block mapping.

Fig. 9 is the flow chart of steps of managing damage block technology.

Figure 10 is the flow chart of steps of the particular implementation of the continuous page read operation using bad block mapping.

Figure 11 is the schematic diagram of the mode of operation of page buffer of the steps flow chart according to Figure 10 Yu Figure 12.

Figure 12 is the step stream of the particular implementation of the addressable continuous page read operation using bad block mapping Cheng Tu.

Wherein, description of reference numerals is as follows：

20：NAND gate grid flash memory device

22：Input and output control

23：State buffer

24：CPR address register

25：Instruction registor

26：Address register

27：Inquiry table buffer

28：Mapping logic

29：Address counter

30：Control logic

31：CPR bad block logic

32：CPR bad block buffer

33：High voltage generator

34：Column decoder

36：Row decoder

38：Page buffer

40：NAND gate flash array

42：User addressable area

44：Redundancy block region

46：Inquiry table information block

120：Inquiry table

130：NAND gate memory array

200：Initialization program

202～204,302～312,322～350,362～390,410～450,510～550,610～650,710～ 730th, 750～790,910～970：Step

206、314、460、560、660：Proceed to process

300：Page read operation

320：Continuous read operation

360：The continuous read operation of addressable

400：Receive page programization instruction

500：Receive block erasure instruction

600：Managing damage block

700：The page reads instruction

740：Continuous page reads instruction

810：Data/address bus

820：Error-Correcting Circuit

830：Cache buffer

840：Data buffer

850：NAND gate flash array

852、854：The page

900：Start addressable continuous page to read

CR-0、CR-1：Cache keeps in part

DR-0、DR-1：Data keeps in part

ECC-0、ECC-1：Error-Correcting Circuit section

LBA：Logical block addresses

PBA：Physical block address

CS/、CLK、DI、DO、WP/、HOLD/：Control signal

Specific embodiment

In software or hardware, realize bad block inquiry table using master control set or peripheral control unit, may make The burden obtaining on software development and hardware spending increases.However, the specific function being associated with the creation of inquiry table and use can be On the chip of storage arrangement itself, (on chip) realizes, namely on the additional circuit of identical chips, or even in storage The function of inquiry table is realized, to reduce burden in the instruction of device device and control logic.Furthermore, real on chip The function of existing inquiry table can make that the function of inquiry table is instructed with other and the function of control logic is closely integrated so that with non- Door flash memory can read the higher new command of feature such as instruction and its change using such as continuous page.

Fig. 1 is the function block schematic diagram of NAND gate flash memory device 20.Described NAND gate flash memory dress Put 20 page buffers 38 including NAND gate flash array 40 and correlation.NAND gate flash array 40 includes word-line (OK (column)) and bit line (row (row)), and by user addressable area 42, redundancy block region 44 and inquiry Table information block 46 is formed.NAND gate flash memory device 20 may include other different circuit to support memory program Change, erase and read, such as column decoder 34, row decoder 36, input and output control 22, one or more state buffers 23rd, one or more continuous pages read (continuous page read, CPR) address register 24, instruction registor 25, Location buffer 26, inquiry table buffer 27, control logic 30, CPR bad block logic 31, CPR bad block buffer 32 with And high voltage generator 33.Column decoder 34 can (or can be according to NAND gate flash memory device 20 according to user control Internal control) and select the row of user addressable area 42, and the inside control according to NAND gate flash memory device 20 Make and select redundancy block region 44 and the row of inquiry table information block 46.Described NAND gate flash memory device 20 can Encapsulated with any required form, and can be had any including traditional NAND gate flash memory device interface etc. The interface of type, the control logic 30 of Fig. 1 is come in fact with the SPI and QPI agreement including Multiinputoutput SPI interface exemplaryly Existing.Additional detail with regard to QPI and SPI interface and the circuit related to memory array can be found on July 7th, 2009 and gives 7th, 558, No. 900 United States Patent (USP) of Jigour et al., and January 13 Republic of China Hsinchu City, Taiwan Province winbond electronicses stock in 2011 Publication W25Q64DW of part company limited：“SpiFlash1.8V 64M-Bit Serial Flash Memory with Preliminary amendment C of Dual/Quad SPI＆QPI ", way of reference is expressly incorporated herein above patent in full.

Page buffer 38 includes a page Data buffer (not illustrating), a page cache buffer (not exemplaryly Illustrate) and in order to the page transmission gate from Data buffer replicate data to cache buffer.The present invention is not intended to limit number According to the pattern of buffer and latch in cache buffer, exemplary latch can using back-to-back (back-to-back) even The phase inverter connecing is realizing.The present invention is not intended to limit the form of transmission gate；In the present embodiment, described transmission gate is passed with CMOS Defeated door is realizing.The present invention is not intended to limit Data buffer and the quantity needed for cache buffer, for example, can be according to transmission The cabling of door connect and the operation of control data transmission and determine required quantity.For example, Data buffer and cache Buffer can be made up of respective part respectively, and be utilized respectively the transmission gate group being controlled by corresponding control line and hand over For operation.Page buffer 38 can be operated to the respective traditional approach transmitting gate control line by applying identical control signal Data buffer and cache buffer, or by applying the control signal of appropriate sequential to the blocked operation transmitting gate control line Mode comes peration data buffer and cache buffer.Here realizes a page with two parts exemplaryly, and a page Can be 2K byte, half page (1K) of transmission gate can be controlled by a control line, and second half page (1K) of transmission gate can be subject to Control in another control line, thus Data buffer and cache buffer are arranged as two and half page address portions.Due to described Two parts operate as blocked operation, be can be considered with the page buffer 38 that two parts are realized " table tennis " buffer (ping pong buffer).ECC circuit may be used to carry out ECC calculating in the content of cache buffer.With regard to page buffer 38, ECC circuit And the additional detail of page buffer 38 and the operation of ECC circuit can be found on May 4th, 2012 and applied for by Gupta et al. No. 13/464,535 United States Patent (USP) (" Method and Apparatus for Reading NAND Flash Memory "), way of reference is expressly incorporated herein above patent in full.Described is organized into Data buffer with cache buffer Some and various pieces carry out ECC mode be an exemplary embodiment, other technologies are also dependent on demand And use.

Although NAND gate flash memory device 20 be carry out including continuous page read operation and monoplane with non- Multiple read operation such as error correction on the chip of gate architecture and form and operate, but described framework is only example, described framework Associated change do not depart from the scope of the present invention.In the present embodiment, the page size of full text is taking 2KB as a example, but the present invention Do not limit the capacity of the described page and block.Although here is description clearly being illustrated based on monoplane framework, this exposure It is applied equally to many Flat Architectures.

Fig. 1 also illustrates control signal CS/, CLK for SPI interface, DI, DO, WP/, HOLD/.Standard SPI flash interface Control signal CS/ (chip selection-reverse), CLK (seasonal pulse), DI (serial data-input) and DO (serial data-defeated are provided Go out), and selectable signal WP/ (write protection-complementation) and HOLD/ (keep-complementary).Although 1 in standard SPI interface Bit serial data bus provides simple interface, but its reading circulation is still limited.It is therefore to increase to read circulation, many bits SPI interface then supports dual flow (2 bit interface) and/or quadruple flow (4 bit interface) further.Fig. 1 also illustrates and passes through Optionally redefine four pins function and be used for dual flow SPI and quadruple flow SPI operation excessive data total Line signal, such as I/O (0), I/O (1), I/O (2) and I/O (3).In quadruple flow SPI read operation, I/O can be passed through (0) provide suitable reading instruction with 1 bit standard SPI interface, but the further interface for the output of address data is to be based on The interface (such as 4 bit data bus) of quadruple flow.In another version of quadruple flow SPI, can be compared with 1 by I/O (0) Special standard SPI interface gives to read instruction and address, but the further interface being used for data output is the interface based on quadruple flow (such as 4 bit data bus).Can be using optional virtual clock cycle between address and reading data providing.With in standard Export 1 bit data in SPI read operation to compare, quadruple flow SPI read operation can export 4 bit numbers in a clock cycle According to, and therefore quadruple flow SPI read operation can provide four times high of reading circulation.Although herein using quadruple flow SPI Read operation explains, but is applied equally to other operator schemes, for example standard SPI, dual flow SPI, quadruple flow Perimeter interface (Quad Peripheral Interface, QPI) and double transfer rate (Double Transfer Rate, DTR) read mode.In QPI agreement, complete interface (instruction, the output of address data) is to be completed based on 4.In DTR In agreement, provide output data declining and rising on CLK edge, rather than such as single times of transfer rate (Single Transfer Rate, STR) on declining CLK edge, only provide like that output data in read mode operation.

Managing damage block

Fig. 2 is the organizational structure of NAND gate flash memory array 130 and is associated with NAND gate flash memory array 130 Inquiry table 120 schematic diagram.NAND gate flash memory array 130 comprises three regions, user addressable area, redundancy Block areas and inquiry table information area.Inquiry table 120 comprises the mapping from logical block addresses to physical block address, institute The mapping stated is used for managing damage block., using in the redundancy block region of NAND gate memory array 130 taking Fig. 2 as a example Block being replaced in the quantity of bad block being found during manufacture is processed, namely block 56 (not illustrating) passes through redundant area The block 0 in block region is replaced, and block 214 (not illustrating) is replaced by the block 1 in redundancy block region, and block 215 (is not painted Show) replaced by the block 2 in redundancy block region, block 642 (not illustrating) is taken by the block 3 in redundancy block region Generation, and block 792 (not illustrating) replaced by the block 4 in redundancy block region.As with the manufacturer-supplied, therefore, store Utensil has a untapped redundancy block 5, and comprises 1024 blocks of a complete addressable memory.

Although not illustrating in fig. 2, all blocks that manufacturer may use up in redundancy block region are replacing Bad block, and the Partial Block even used up in user addressable area carrys out replacing damaged block.Skill described herein Art can be applicable to this situation.

Referring once again to Fig. 2 it is assumed that working as memorizer in use, block 1 lost efficacy, secondly block 5, then block 7.Lost efficacy Block be mapped to good block in NAND gate flash memory array 130, to enable devices to persistently use.Citing and Speech, bad block be mapped to first in redundancy block region not using block, be then just mapped to user addressable Shi Yong block in region.First map to redundancy block region and can extend the user addressable storage remaining complete as best one can The time of device load, but any required mapping framework all can be used in this.As shown in Fig. 2 bad block 1 is mapped first To redundancy block 5, then bad block 5 is mapped to the block 1023 in user addressable area, and bad block is reflected When being incident upon the block 1022 in user addressable block, bad block 1 is mapped to redundancy block 5.

The inquiry table 120 of the present invention can be established in inquiry table buffer 27, and can directly access control logic 30 with And mapping logic 28.Inquiry table buffer 27 can be realized using little and quick volatile storage, and for example static random is deposited Its capacity system of access to memory (SRAM) is postponed based on inquiry table and can be allocated trading off to the bad block quantity replacing block Consider and design alternative.For example, inquiry table buffer 27 may be designed as storing the logical blocks of 20 bad blocks The physical block address of the address replacement block related to 20.Inquiry table buffer 27 can chip start (power-up) or The logical block addresses being read from the inquiry table information block of NAND gate flash memory array 130 and physics is inserted during replacement Block address data.Wherein, the bad block of user addressable area all can be labeled, such as in the spare area of first page First bit with non-FFh data in domain, block can be read in order to confirm the logical block addresses inventory in inquiry table 120 Correctness.

Although inquiry table buffer 27 is schematically shown as single buffer, its can by any required by way of realizing.? In one embodiment, inquiry table buffer individually partly can be realized using two, and one of them part can access for user Part, and this part can comprise to be associated with the map information of user addressable area, but do not comprise to be associated with redundancy block The map information in region, and another part therein then portion by being used by inside by NAND gate flash memory Divide, and this part can comprise to be associated with the map information in redundancy block region.

Fig. 3 be initial interrogation table an implementation flow chart of steps, wherein Fig. 3 illustrate in order to chip start or One embodiment of the initialization program 200 of construction inquiry table during replacement.The address providing inquiry table information block uses for internal (step 202) and in order to read inquiry table information to inquiry table buffer to set up inquiry table (step from inquiry table information block Rapid 204).

When described method is applied to Fig. 2 embodiment, initiation sequence may result in inquiry table and has logical blocks ground The block 56 of location index, block 214, block 215, block 642 and block 792, and the RBA corresponding to physical block address Block 0, RBA block 1, RBA block 2, RBA block 3, and RBA block 4 (be expressed as from left to right be staggered downwards). , because in the present embodiment, it is bad block that manufacturer indicates block 56,214,215,642 and 792 for this, and maps described Bad block to the block 0,1,2,3 and 4 in redundancy block region, and the information of described mapping is positioned over inquiry table In information block 46.

Fig. 4, Fig. 5 and Fig. 6 illustrate the exemplary process mode of three kinds of example instructions, and the respectively page reads and instructs, quickly Continuous page mode instruction and addressable continuous page mode instruction.The described type reading instruction can simultaneously (but non-must Need simultaneously) it is implemented in a specific NAND gate flash memory device.The page reads instruction with institute in its page address field One of the memorizer page is read in the address specified.Quick continuous page reads instruction and can be connected in page reading instruction Afterwards, and from the described address specified start continuously to read the page of memorizer.Quick continuous page reads instruction not Comprise address field.Addressable continuous page reads instruction to start continuously to read the page of memorizer from the described address specified Face.

As shown in figure 4, when receiving page reading instruction, the page reads specified page address in instruction and is stored In address register 26 (step 302).Page reading process successively carries out replacing block processes, wherein replaces block processes and relates to And the search in inquiry table buffer 27, look into so that whether the address judging the block address part in address register 26 meets Ask any logical block addresses (step 304) in table buffer 27.Because inquiry table buffer 27 can be little on chip And quick SRAM, therefore its available control logic 30 carries out local access, therefore the action of described search can be not notable Rapidly carry out in the case of impact read access time.(step 304- is no), logical blocks if do not find the search result meeting Address can be used to read in the page to page buffer 38 (step 308).If finding (step 304- during the search result meeting It is), the bad block that need to replace will be instructed to, and replace address register 26 using the physical block address replacing block In logical block addresses to read the required page (step S306).When required page of data is read into page buffer 38 When (step 308), described data carries out error-correcting routine, and suitably sets in one or more state buffers Fixed ECC bit (step 310) producing according to this.Then, export the described page (step 312) and proceed to process 314.

Fig. 5 is the flow chart of steps of the continuous page read operation using bad block mapping, and wherein Fig. 5 illustrates basic Continuous page reading process 320, described continuous page reading process 320 is compatible to be mapped in bad block and comprises to damage Block management.Described processing repeatedly is carried out after setting up suitable initial condition (step 322), and wherein said is suitable Depending on the application according to substantially continuous page reading process 320 for the initial condition system.When NAND gate flash memory device has conjunction During suitable initial condition, continuous page reading process 320 substantially can be used by way of depicted as shown.Here with The mode of prior operation is followed to produce suitable initial condition in continuous reading program 320, but suitable initial condition Also can be produced by other multiple different methods.Described prior operation is, for example, the execution of instruction, due to except quick Continuous page reads outside the decoding of instruction, and the action of execution can start in the case of not having any delay, therefore in the case The operation of described instruction execution can be considered quick continuous page and read (fast continuous page read, FCPR). For example, when the page of Fig. 4 reads instruction termination and do not export page data, it can be used to set up described initial strip Part (step 312).This step leaves initial address in address register, and (described processing method 320 also can be modified Address for beyond tolerable initial address), and make ECC process the data in page buffer using as initial condition (step 322).

Then, three operations substantially simultaneously carrying out are carried out, that is, using the Part I of page buffer as output (step 330), the Part II in page buffer carry out ECC calculating (step 332) and using suitable inquire about list procedure by next Page of data reads in page buffer (step 334), and described inquiry list procedure is, for example, that the step 304 of Fig. 4 is used for 306 grades The processing routine of bad block.Next described page of data can be by with the address counter 29 (Fig. 1) on chip incrementally Address in location buffer 26 is accessing, and to enter followed by the mode of the replacement block processes depicted in for example, Fig. 4 Row replaces block processes (with reference to step 304 and 306).In order to avoid circuit is excessively complicated, replacing block processes only need to be in access Carry out during the border of first page and each operating procedure, and then carry out replacing area in the case of not undermining each page accesses Block is processed.Although in the page read after continue continuous reading when, first time repeat in the case of, in page buffer Carrying out ECC calculating (step 332) system on the Part II of device is unnecessary step, but it still will not undermine described process side Method.If necessary, continuous read operation can be modified to and repeat period of continuous read operation in first time and bypass (bypass) step (step 332) of ECC calculating is carried out on the Part II of page buffer.

Then, carry out two operations substantially simultaneously carrying out, that is, output page buffer Part II (step 340) with And ECC calculating (step 342) is carried out on the Part I of page buffer.Because the partial data page has been output and in shape ECC bit in state buffer 23 is set, therefore can carry out preliminary bad block assessment (step 350).Noticeable It is now not necessarily to complete the reading of the page, if necessary also can be in the operation of step 334 previously, to complete part The operation read of the page replacing the operation originally completing that the complete page reads, and the reading of partial page can and from page Face buffer Part II output action (step 340) and ECC calculating is carried out on the Part I of page buffer Action (step 342) is the operation substantially simultaneously carrying out.

The continuous page continuing can be read and defeated by repeating the step starting from step 330,332 and 334 Go out.Continuous reading is constantly carried out until being terminated by any required mode, for example, pass through to terminate the choosing of seasonal pulse and chip Select signal.

Preliminary bad block assessment (step 350) can be carried out by following embodiment.Described assessment can be led to Cross ECC bit in CPR bad block logic 31, CPR bad block buffer 32 and state buffer 23 to carry out.Here system To indicate no continuous page read error (00), one or more recoverable errors (01), a nothing using two ECC bits The continuous page read error (10) of method correction and the continuous page read error (11) that cannot correct more than, but its His known representation is equally applicable to this.Any the required suitable type of information is maintained all may be used with the buffer of capacity For described CPR bad block buffer 32, for example sustainable follow the trail of no continuous page read error (00), one or more can school Positive mistake (01), a continuous page read error (10) that cannot correct and be more than a continuous page that cannot correct The dibit buffer of read error (11).When the ECC being carried out on the partial data page in page buffer 38 calculates When completing, result of calculation can be write to the ECC bit of state buffer 23 by Error-Correcting Circuit (not illustrating), described calculating Result may be inerrancy (00), recoverable error (01) or uncorrectable error (10).CPR bad block logic 31 ECC bit in inspection state buffer 23, the suitably numerical value in adjustment CPR bad block buffer 32, and if ECC When bit is designated as uncorrectable error (10), page address is write CPR address temporary by CPR bad block logic 31 Device 24.CPR bad block logic 31 then will be temporary for suitable numerical value write state according to the numerical value of CPR bad block buffer 32 The ECC bit of storage 23, and the numerical value of the ECC bit being originally written state buffer 23 is covered by Error-Correcting Circuit.CPR Bad block buffer 32 can be read can not by being read by user or by user.If continuous read operation 320 Be terminated at this moment, then user can read state buffer 23 with see whether occur no continuous page read error (00), One or more correctable continuous page read errors (01), a continuous page read error (10) that cannot correct or The continuous page read error (11) that cannot correct more than one, and user also can read CPR address register 24 with first Step ground identification bad block.If the capacity of CPR address register 24 only be enough to retain a block address, CPR address is temporary The bad block that storage 24 will cover previous either block address and comprise last preliminary identification.If CPR address When the capacity of buffer 24 be enough to retain multiple block address, CPR address register 24 can not cover previous block address In the case of add less than buffer capacity new bad block.

The addressable continuous page being compatible to bad block mapping and comprising managing damage block reads (addressable Continuous page read, ACPR) process 360 as shown in Figure 6.The continuous page reading process 320 of Fig. 5 may be incorporated into described ACPR process 360, and described ACPR process 360 lie in set up suitable initial condition after repeatedly carry out.Can seek In the example that location continuous page reads, described initial condition comprises to instruct provided initial address.Described initial address It is stored in address register 26 (step 362), and using suitable inquiry list procedure, page of data is read in page buffer Device (step 364), the described inquiry list procedure for example, step 304 of Fig. 4 and 306 grades are used for the processing routine of bad block. Then, ECC calculating (step 366) is carried out on the Part I of page buffer.Hereafter, processing routine is with as indicated in the drawings, Persistently carried out by way of repeated execution of steps 370,372,374,380,382 and 390, wherein said step 370, 372nd, 374,380,382 and 390 can correspond to the step 330 of Fig. 5,332,334,340,342 and 350.

Fig. 7 is schematically shown as the example of procedure treatment.First, receive page programization instruction (step 400).Page program Instruction comprises page address field, and the page address being wherein intended to sequencing can obtain from page address field and described desire journey The page address of sequence can be positioned in address register 26.Then, procedure treatment pass through search inquiry table buffer 27 with Judge whether the address in address register 26 meets any logical block addresses (step 410) in inquiry table buffer 27. Because inquiry table buffer 27 can be quick SRAM, namely control logic 30 can carry out local access, therefore described search Operation rapidly can be carried out in the case of not appreciable impact Programming times.If not finding (the step during search result meeting 410- is no), using the page (step 430) of logical block addresses programmed memory.If finding (the step during search result meeting Suddenly 410- is), bad block will be instructed to, and replace address register 26 using the physical block address replacing block In logical block addresses (step 420), with the page (step 430) needed for sequencing.Once obtaining correct page address, Actual pages procedure treatment (step 430) and the process (step 440) for checking sequencing mistake can pass through any institute The mode needing is carrying out.Taking a feasible sequencing verification operation technology as a example, it typically can set in state buffer Pass through/lost efficacy bit (pass/fail bit).After checking sequencing mistake, described sequencing verification operation can foundation Demand carries out managing damage block (step 450) (with reference to Fig. 9).Once after the completion of the managing damage block operation of any mode, Remaining storage operation will proceed to process 460.

Fig. 8 is schematically shown as the example of process of erasing.First, receive instruction (step 500) of erasing.Block erasure instruction comprises area Block address field, the block address wherein to be erased can obtain from block address field and the described block address to be erased Can be positioned in address register 26.Then, block erasure processes and judges address temporary by searching inquiry table buffer 27 Whether the address in device 26 meets any logical block addresses (step 510) in inquiry table buffer 27.Because inquiry table is temporary Storage 27 can be quick SRAM, namely control logic 30 can carry out local access, therefore the operation of described search can not show Write impact and erase and rapidly carry out in the case of the time.(step 510- is no), logic area if do not find the search result meeting Block address can be used for block (step 530) of erasing.If finding during the search result meeting (step 510- is), bad block will It is instructed to, and replace the logical block addresses (step in address register 26 using the physical block address replacing block Rapid 520), with block (step 530) of erasing.Once obtain correct block address, actual block erase process (step 530) and For check the process (step 540) of block erasure mistake by by any required by way of carrying out.With feasible smearing As a example verification operation technology, it typically can be set by/lose efficacy bit in state buffer.Checking mistake of erasing Afterwards, described sequencing verification operation can carry out managing damage block (step 550) (with reference to Fig. 9) according to demand.Once it is any After the completion of the managing damage block operation of mode, remaining storage operation will proceed to process 560.

Fig. 9 is schematically shown as the example of managing damage block, and it can be carried out using various ways, for example, institute That states can be controlled by user by host side or controller, be passed through host side or control in order to distribute the process replacing block Device processed react on bad block labelling and semi-automatically control and the control logic by NAND gate flash memory device and Automatically control.

Managing damage block is to check bad block (step 610) and to decide whether replacing damaged block (step 620) Start.For the example of user control process or semi-automatic process, check bad block and decide whether replacing damaged The operation of block is all to be completed by host side or controller by user.For the example automatically processing, check and damage Bad block and decide whether replacing damaged block operation system to be realized by the control logic of NAND gate flash memory device.Right For read operation, read operation reads (for user control process and half certainly according to the numerical value of state buffer itself For the dynamic example processing) or check (for the example automatically processing) ECC bit.Possible ECC bit reads or examines The fruit that comes to an end for example comprises inerrancy, the mistake of correction, uncorrectable error and multiple uncorrectable error (for even For the continuous page reads).When the timing carrying out multiple bits, possible ECC bit reads or inspection result can further include The bit number of correction, or comprise to indicate merely the maximum number of the bit being corrected.React on ECC bit to read or check It is the mistake of inerrancy and correction that the action of result for example comprises when result, and the mistake of described correction is less than recoverable When the maximum number of bit or marginal value that some are secondary, do not take any action；The mistake being correction when result, and by When the mistake of correction is the maximum number of recoverable bit or marginal value that some are secondary, carry out the substituted operation of block；And When repeating to read successfully and when making the operation that block replaces carry out with uncorrectable error, carry out repeating to read.For For page program and block erasure operation, it is determined by/failure bit based on one or more in state buffer Read (for the example of user control process and semi-automatic process) or check (for the example automatically processing) State buffer.The action of the reading or inspection result that react on state buffer comprises for example when state buffer is designated as " Pass through " when, do not take any action；When state buffer is designated as " inefficacy " when, repetitive routine or the operation erased；And If state buffer is designated as " inefficacy " when, replace to carry out repetitive routine or the operation erased with block.

Although the purpose system of continuous page read operation is in order to export the substantial amounts of page in general, single continuous During page read operation, the situation of the several bad blocks of middle discovery is also more rare.Therefore, continuous page reads CPR address temporary Device 24 only needs the capacity with single page address, but it has the capacity of multiple page addresses also dependent on demand.Right For continuous page read operation, check bad block (step 610) and decide whether to replace this bad block (step 620) operation system is related to the inspection of ECC bit.If necessary, continuous page read operation can be using replacement block come weight Multiple.Just in case tentatively picking out extra bad block, then only repeating managing damage block.

If (step 620- is) selects to replace block (step 630) under the situation that bad block is substituted.For use For the example of person's control process, user sends suitable instruction so that the logical block addresses of bad block map to replacement The physical block address of block.Address of cache instructs as a kind of suitable instruction type, and wherein address of cache instructs as user Determine to replace the physical block address of block in user addressable area 42, and specify the logical blocks ground of bad block Location and the instruction of the selected physical block address replacing block.Bad block mark instructions are originally as another kind of suitable finger Make type.For semi-automatic process and for the example that automatically processes, control logic can react on any suitable instruction and select Select for block.Although can start using special instruction that the operation that block selects is replaced, replace the operation that block selects Also can be started by other instruction types.For example, bad block mark instructions are commonly used for as being suitable in this area Start and replace the instruction that block selects.Although the demand of traditional bad block labelling has been queried table information block 46 (Fig. 1) institute Replace, but retain described bad block mark instructions in old system and also do not result in any infringement.However, it is described Bad block mark instructions can be corrected extraly to make the logical block addresses of bad block map to redundancy block region 44 In available block, use eliminating user and determines replacement the patrolling of block from the available block that redundancy block region 44 is provided Collect the demand of block address.Because redundancy block region 44 and user addressable area 44 all can access NAND gate flash The control logic of device device, therefore replace block and can select only from the redundancy block region 44 of NAND gate flash array 40, or Can select from one of the redundancy block region 44 of NAND gate flash array 40 and user addressable area 42.Any institute The technology needing all may be used to recognize next available replacement block, for example, can be utilized and replaces block address buffer (not Illustrate), wherein said replacement block address buffer comprises the next available physical block address replacing block.Manufacture Business can produce next available replacement block address when initial and be stored to inquiry table information block 46, wherein look into Inquiry table information block 46 can be read in replacing block address buffer when device starts and be stored, and can be in device It is updated in a period of operation.Available replacement block can be determined by any feasible pattern, such as in redundancy block region 44 In from low address to high address, secondly to determine available replacement from high address to low address in user addressable area 42 Block.In order to replace the purpose of block, the block in user addressable area 42 can be retained and be used as replacing block, or inspection Look into each block be selected as to guarantee each block " can use " be not used by before.

In the case of the logical block addresses of bad block and both logical block addresses of replacement block are all known, can Update inquiry table buffer 27 and inquiry table information block 46 (step 640) according to this.The operation updating is in user control process Example in can be instructed by address of cache or bad block mark instructions are to start, can pass through in the example of semi-automatic process Bad block mark instructions, to start, can be started by control logic in the example automatically processing.For making follow-up storage Device access is able to accurately, and inquiry table buffer 27 needs prompting to update.During for making updated inquiry table will not break in the supply Lose, inquiry table buffer information block 46 also needs reasonably to point out to update.The operation updating can utilize any required mode To carry out, for example, the operation that is individually updated, or first passing through renewal inquiry table buffer 27 followed by passes through to inquire about The inquiry table of table buffer 27 writes the operation to be updated to the mode of inquiry table information block 46.

Then data is transferred to replacement block (step 650) from bad block.For example, in inquiry table buffer 27 In, two map indexs are placed to each replacement block, damages in the first map index person's of may be used as addressable area Block logical block address is to the good route replacing block, and second map index then can be extremely right as logical block addresses The route of the good replacement block answered extremely corresponding bad block.Second map index provides the access of bad block, with from Bad block transfer data replaces block to good.In the example of user control process, described transfer operation can be passed through Address of cache instruction or bad block mark instructions and start, in the example of semi-automatic process, described transfer operation can be led to Cross bad block mark instructions and start, in the example automatically processing, described transfer operation can be opened by control logic Dynamic.Can further proceed to process 660.After the operation of block transmission, the access of bad block is avoided by.

From user addressable area 42 select replace block in the case of, user it should be noted that must not access in order to Reading, sequencing or the replacement block erased.In the example of user control process, should be by the user controlling map operation Come to be careful not to access in order to read, sequencing or the replacement block erased.User can be by reading inquiry table buffer 27 To judge whether specific accessing operation is the operation that access replaces block.Additionally, the control of NAND gate flash memory device Logic can automatically judge whether specific accessing operation is the operation that access replaces block.For example, NAND gate flash memory Reservoir device can be before instruction execution, and in leading searching instruction, whether one or more specified addresses meet inquiry table buffer Physical block address in 27.If specified address does not all meet the physical blocks ground in inquiry table buffer 27 in instruction Then it represents that instruction can be performed during location.If specified address meets the physical blocks in inquiry table buffer 27 in instruction Then it represents that user attempts to be directly accessed replacement block during address, therefore instruction should be not carried out.

Continuous reading and managing damage block using ECC

＂ continuously reads ＂ here and represents a kind of type of memory read operations, and the purpose of described continuous reading is it Can be not required to repeat to send page reading instruction in each page, and can be by way of the page continues the page (page-by-page) To read memory array partially or in whole.The example of the NAND gate flash memory 20 with SPI interface depicted in Fig. 1 In son, NAND gate flash memory device 20 can be started by control signal high level to low level transition, then sends Continuous page reads instruction.In this embodiment, continuous page reads the transmission of instruction can make the continuous page can be by sequence Read and export until processing routine stop.Continuous page read can by any required by way of stop.For example, even The continuous page read can by stop seasonal pulse control signal CLK and then by control signal CS/ from low level transition to high level Mode so that continuous page read stopped based on control signal CLK of seasonal pulse.Additionally, continuous page read instruction can be according to According to other independent signals with after reading the default or page of specified quantity, or stop under any other required mode Carry out.

Page buffer for NAND gate flash memory array can be constructed and operate to read the phase in continuous page Between eliminate the gap of output data with discontinuous, the described gap eliminating output data during continuous page reads with do not connect Continuous technology explanation can be found on May 4th, 2012 by apllied No. 13/464,535 United States Patent (USP) of Gupta et al. (" Method and Apparatus for Reading NAND Flash Memory "), above patent way of reference in full It is expressly incorporated herein." addressable continuous page reads " here system corresponds in the apllied patent of Gupta et al. " continuous page reads Take ", and " quick continuous page reads " here corresponds in Gupta et al. apllied patent " modification continuous page reads Take ".

Addition can carry out the quick on chip of local access by control logic (control logic 30 of such as Fig. 1) The advantage of inquiry table buffer (the inquiry table buffer 27 of such as Fig. 1) be, when run into replace block when, inquiry table is kept in In the case that device can postpone not having significant page read access time, opened using damaging defective-area management from NAND gate flash memory Dynamic continuous page reads, and is therefore more conducive to avoid any cross-page gap with block border or discontinuous.

Figure 10 illustrates and is suitable to complete the page buffer composition of continuous page read operation and the step stream of operation using ECC Cheng Tu.The schematic diagram system of the different continuous operation depicted in Figure 11 is associated with depicted different step in Figure 10.Figure 11 Depicted is for example corresponding to the persistent period that each operates, and the present invention does not limit the persistent period of operation.

Figure 11 illustrates data/address bus 810, NAND gate flash array 850 and page buffer.Described page buffer Here to be realized with the exemplary embodiment comprising Data buffer 840.Data buffer 840 comprises to form with two parts Data keep in part DR-0 and DR-1.Described page buffer also comprises cache buffer 830, and cache buffer 830 wraps Keep in part CR-0 and CR-1 containing with the cache of two part compositions.Therefore, can be considered in page buffer to have and comprise cache Buffer CR-0 and the Part I of Data buffer DR-0, and comprise temporary part CR-1 of cache and temporary part DR-1 of data Part II.From unlike not divided page buffer, not divided page buffer only needs one group to control letter Number, two of page buffer partly may need two groups of control signals.In addition although page buffer here is with two parts group Carry out support company as a example the framework becoming to resume studies extract operation, but its associated change is transparent (transparent) for user 's.Programming operations can complete under the standard page size of 2KB, and for example after completing page read operation from cache The standard read operation reading page data also can complete under the standard page size of 2KB.Such internal composition is divided into two Partial page buffer is particularly suitable for continuous page read operation, even and if described page buffer interior part Cut to be divided into two parts mode to realize, the inside division of page buffer is transparent for user.

Figure 11 illustrates an Error-Correcting Circuit 820 also exemplaryly, and it can be in being logically viewable as with Error-Correcting Circuit Section ECC-0 and ECC-1.Error-Correcting Circuit section ECC-0 provides cache to keep in the error correction of the content of part CR-0, and And Error-Correcting Circuit section ECC-1 provides cache to keep in the error correction of the content of part CR-1.Although for clarity, Two different Error-Correcting Circuit section ECC-0 and ECC-1 be schematically shown as respectively with cache keep in part CR-0 interface with CR-1, so And also can keep in part CR-0 with cache using single ECC block simultaneously and interface with CR-1.

Quickly continuous reading instruction does not comprise address field, but relies on the prior instructions comprising address field, for example The page reads instruction.Refer to Figure 10 and Figure 11, the page reads the address of instruction 700 offer initial page 852, wherein initial page The address in face 852 is read and is stored in Data buffer 840 (step 710).For example, from the page 852 transferase 12 K word To Data buffer DR-0 and DR-1, the wherein page 852 can be considered the page -0 of sequence to the data of section.Wherein shift 1K word every time The operation saving to Data buffer DR-0 and DR-1 can be for carrying out simultaneously or asynchronously.The operating time that the page reads is, for example, 20 Microsecond (μ s).

Then, as shown in Figure 10 and Figure 11, the data in Data buffer 840 is transferred to cache buffer 830 (step 720), and to the page data in cache buffer 830 carry out ECC calculating (step 730).From Data buffer 840 to fast Depend on design alternative the transfer time taking buffer 830, but generally between about 1 μ s to about 3 μ s.Error-Correcting Circuit 820 school Just complete the required time depend on the selection of ECC algorithm, internal data bus, on chip sequential cycle oscillator and its His design factor.For example, because each cache that some physical Design can be simultaneous for cache buffer 830 keeps in part CR-0 and CR-1 uses single ECC circuit block, and each cache is kept in part CR-0 and can for example be spent 18 μ s' with CR-1 Time carries out error correction, therefore Error-Correcting Circuit 820 can complete to correct within the time of about 36 μ s.

The page read in the case of no seasonal pulse output data terminate, and continue carry out continuous page read instruction 740.As shown in Figure 10 and Figure 11, here can carry out multiple operations substantially simultaneously.The described multiple operations substantially simultaneously carrying out One of which is to be related to transmission cache to keep in the data of the page -0 in part CR-0 to data/address bus 810, with total via data The operation (step 750) of line 810 output data, the data of the wherein page -0 has already been through the calculating of ECC.Although data/address bus Path between 810 to output port does not illustrate, but such path is many weeks for one skilled in the art Know.

The described multiple operations wherein another one substantially simultaneously carrying out is to be related to shift the page in temporary part DR-1 of data The part of face data to cache keeps in part CR-1, and the page data part keeping in part CR-1 to cache carries out ECC meter The operation (step 760) calculated.Keep in part DR-1 to cache from data and keep in the transfer time of part CR-1 depending on design choosing Select, but generally between about 1 μ s to about 3 μ s.For example, Error-Correcting Circuit section ECC-1 can complete to correct in about 12 μ s. However, it is assumed that send out cache to keep in time of part CR-0 data is that 20 μ s and data keep in part DR-1 to cache temporary storage part The transfer time dividing CR-1 is 2 μ s, then Error-Correcting Circuit section ECC-0 and ECC-1 can be designed in 18 μ s or shorter Interior complete.

The described multiple operations substantially simultaneously carrying out wherein again one be related to from NAND gate flash array 850, next is suitable The 2KB page of the page data 854 (page -1) of sequence reads in the operation (step 770) that data keeps in part DR-0 and DR-1.Look into The processing routine that inquiry table replaces block can be used for each accessing operation, or is only used for first access and transregional block boundary. Although most transfer system is carried out with the operation of step 760 simultaneously, the data that it keeps in part DR-1 in data is transferred to Just proceed by after the operation of cache buffer CR-1.

Although the various operations that Figure 11 illustrates substantially are carried out simultaneously, not all operations all need to carry out simultaneously, only Gap output data can be avoided according to the teaching stated herein is with other discontinuously.

Then refer to Figure 10 and Figure 11, here can carry out multiple operations substantially simultaneously.Described substantially carry out simultaneously Multiple operation one of which are related to send cache keeps in the data of the page -0 in part CR-1 to data/address bus 810, with via The operation (step 780) of data/address bus 810 output data, the data of the wherein page -0 has already been through the calculating of ECC.It is assumed that when Arteries and veins frequency is 100MHz, can send out the data (1KB) that cache keeps in part CR-1 in about 20 μ s.

The described multiple operations wherein another one substantially simultaneously carrying out is to be related to shift the page in temporary part DR-0 of data The part of face data to cache keeps in part CR-0, and the page data part keeping in part CR-0 to cache carries out ECC meter The operation (step 790) calculated.This operating procedure is substantially to carry out similar to the associated description of Figure 11.

Continuous page read operation returns to step 750 by loop and proceeds, and can be by stopping seasonal pulse and control Signal CS/ processed is stopping.Additionally, continuous page read operation also can read predetermined number by changing continuous page reading order The page rear of amount or stopped with the arbitrary other modes needed for designer.

The advantage that continuous page reads instruction is, it can cause and read whole or required part in the page or block border NAND gate flash array when there is no gap or discontinuous situation.This advantage is by reading data in an alternating manner Lai real Existing, for example alternately keep in part CR-0 and reading data CR-1 from cache.

Figure 12 illustrate be suitable to using ECC complete addressable continuous page read operation page buffer composition and operation Flow chart of steps.The schematic diagram system of the different continuous operation depicted in Figure 12 is associated with depicted different step in Figure 11 Suddenly.

As shown in figure 12, by addressable continuous page read in instruction the initial page 852 (page -0) specified from non- The data that door flash array 850 is transferred to Data buffer 840 keeps in part DR-0 and DR-1 (step 910).

Then referring to shown in Figure 11 and Figure 12, the page data of the part in Data buffer 840 is transferred to Page data part in cache buffer 830, and temporary part CR-0 to cache carries out ECC calculating (step 920).

Addressable continuous page read operation substantially can be as the step 930 in Figure 12,940,950,960 and 970 1 As corresponding to step 750,760,770,780 and 790 in Figure 10.Before not yet completing in ECC calculating, data does not also have Be ready for output, therefore step 910 with 912 operation may need consider initial delay.This delay may be about 40 μ s.On the contrary, can stand after user provides instruction, address and selectable virtual seasonal pulse because quick continuous page reads I.e. output data, therefore quick continuous page reads does not have delay.

Although the present invention is disclosed above with embodiment, so it is not limited to the present invention.According to embodiments of the present invention The change of disclosed content and modification are all possibility, and one skilled in the art should be in research this patent document Understand the displacement of various elements and equipollent in embodiment afterwards.In addition, special value mentioned in an embodiment is all example, And can change according to demand.Without departing from the spirit and scope of the present invention, any change and retouching, including in embodiment The displacement of various elements and equalization, all without departing from scope of the invention, wherein protection scope of the present invention is when regarding appended Shen Please the defined person of the scope of the claims be defined.

Claims (9)

1. the method for continuous page read operation is carried out on a kind of flash memory chip in NAND gate it is characterised in that wherein should NAND gate flash memory chip has a NAND gate flash memory array and page buffer, and this page buffer includes One Data buffer and a cache buffer, the method includes：

One inquiry table buffer is maintained on the chip with this NAND gate flash memory array, this inquiry table buffer stores At least one logic damage block address and at least one physics corresponding to described logic damage block address replace block address；

Multiple caches from this cache buffer keep in partly seamless and continuously output data, and this Data buffer is organized It is the temporary part of multiple data of the temporary part of those caches corresponding to this cache buffer；

Set up in order to access a logical page address of this NAND gate flash memory array, this logical page address includes patrolling Collect block address part；

The described logic damage block address of this inquiry table buffer is searched described logic damage block address wherein it Whether meet between one and this logical block addresses part；

When one first cache in keeping in partly from those caches keeps in part output data, right from this cache buffer Data should partly be shifted and keep in part to one second cache, this second cache is kept in and is partially different than this first cache temporary storage part Point；

Keep in part output data in this first cache and shift after data keeps in the step of part to this second cache, this Two caches are kept on partly and are carried out an error-correcting code calculating；

After this first cache keeps in part output data and transfer data keeps in the step of part to this second cache, work as search Step described in logic damage block address and this logical block addresses part when all not meeting, using this logical page address From this NAND gate flash memory array, one page of data is read in this Data buffer, and work as described in the step searched When one of them of logic damage block address and this logic area address part meet, replace block address using described physics This page of data is read in this Data buffer by one of them, and it is corresponding that wherein said physics replaces one of this of block address In the described logic damage block address meeting this logical block addresses part this one of them；And

When keeping in part output data from this second cache, shift data to except this from the corresponding part of this Data buffer Second cache keeps in one of them of the temporary part of remaining those cache of part, and keeps in part to remaining those cache One of them should carry out this error-correcting code calculating.

2. the method carrying out continuous page read operation in NAND gate flash memory chip as claimed in claim 1, it is special Levy and be, the step wherein setting up this logical page address includes being incremented by this logical page address with single page, and the method is also Including：

When crossing over a page boundary, repeat to keep in the step of part output data, set up this logical page (LPAGE) from those caches The step of face address, transfer data to this second cache are kept in the step of part, are carried out the step of this error-correcting code calculating, incite somebody to action This page of data reads in the step of this Data buffer and transfer data is somebody's turn to do to except remaining of the temporary part of this second cache A little caches keep in one of them of part, and remaining those cache is kept in part this one of them carry out this error correction The step that code calculates.

3. the method carrying out continuous page read operation in NAND gate flash memory chip as claimed in claim 2, it is special Levy and be, the step wherein setting up this logical page address also includes being incremented by this logical page address, the method with single page Also include：

When crossing over a block border, repeat to keep in the step of part output data, set up this logical page (LPAGE) from those caches The step of face address, search described logic damage block address one of them whether accord with and this logical block addresses part between The step closed, transfer data to this second cache are kept in the step of part, are carried out the step of this error-correcting code calculating, count this According to the page read in the step of this Data buffer and transfer data to except this second cache keep in part remaining those fast Take temporary part one of them, and remaining those cache is kept in part this one of them carry out this error-correcting code meter The step calculated.

4. the method carrying out continuous page read operation in NAND gate flash memory chip as claimed in claim 1, it is special Levy and be, the step wherein setting up this logical page address also includes being incremented by this logical page address, the method with single page Also include：

When crossing over a page boundary, repeat to keep in the step of part output data, set up this logical page (LPAGE) from those caches The step of face address, search described logic damage block address one of them whether accord with and this logical block addresses part between The step closed, transfer data to this second cache are kept in the step of part, are carried out the step of this error-correcting code calculating, count this According to the page read in the step of this Data buffer and transfer data to except this second cache keep in part remaining those fast Take temporary part one of them, and remaining those cache is kept in part this one of them carry out this error-correcting code meter The step calculated.

5. the method carrying out continuous page read operation in NAND gate flash memory chip as claimed in claim 4, it is special Levy and be, the step wherein setting up this logical page address also includes being incremented by this logical page address, the method with single page Also include：

When crossing over a block border, repeat to keep in the step of part output data, set up this logical page (LPAGE) from those caches The step of face address, search described logic damage block address one of them whether accord with and this logical block addresses part between The step closed, transfer data to this second cache are kept in the step of part, are carried out the step of this error-correcting code calculating, count this According to the page read in the step of this Data buffer and transfer data to except this second cache keep in part remaining those fast Take temporary part one of them, and remaining those cache is kept in part this one of them carry out this error-correcting code meter The step calculated.

6. the method carrying out continuous page read operation in NAND gate flash memory chip as claimed in claim 1, it is special Levy and be, the step wherein setting up this logical page address also includes being incremented by this logical page address, the method with single page Also include：

When crossing over a block border, repeat to keep in the step of part output data, set up this logical page (LPAGE) from those caches The step of face address, search described logic damage block address one of them whether accord with and this logical block addresses part between The step closed, transfer data to this second cache are kept in the step of part, are carried out the step of this error-correcting code calculating, count this According to the page read in the step of this Data buffer and transfer data to except this second cache keep in part remaining those fast Take temporary part one of them, and remaining those cache is kept in part this one of them carry out this error-correcting code meter The step calculated.

7. the method carrying out continuous page read operation in NAND gate flash memory chip as claimed in claim 1, it is special Levy and be, wherein proceed by after the step of the temporary part output data of those caches is during an initial delay, this is first Beginning timing period includes this page of data is read in the time of this Data buffer from this NAND gate flash memory array.

8. the method carrying out continuous page read operation in NAND gate flash memory chip as claimed in claim 1, it is special Levy and be, wherein carry out from the step of the temporary part output data of those caches is not during having an initial delay.

9. a kind of NAND gate flash memory chip is it is characterised in that it includes：

One NAND gate flash memory array；

One column decoder, couples this NAND gate flash memory array；

Page buffer, couples this NAND gate flash memory array；

One row decoder, couples this page buffer；

One i/o controller, couples this row decoder；

One state buffer, couples this i/o controller；

One continuous page reads bad block address register, couples this i/o controller；

One instruction registor, couples this i/o controller；

One address register, couples this i/o controller；

One inquiry table buffer, couples this i/o controller；And

One control logic circuit, couples this column decoder, this row decoder, this page buffer, this state buffer, this is continuous The page reads bad block address register, this instruction registor, this address register and this inquiry table buffer, wherein should Page buffer includes：

One Data buffer, couples this NAND gate flash memory array；And

One cache buffer, couples this Data buffer and this row decoder, it is temporary that this cache buffer is organized as multiple caches Nonresident portion, and this Data buffer is organized as multiple data of the temporary part of those caches corresponding to this cache buffer Temporary part,

Wherein this control logic circuit includes multiple logic elements, and those logic elements are in order to execute following functions：

Maintain this inquiry table buffer, this inquiry table buffer stores at least one logic damage block address and corresponding to described At least one physics of logic damage block address replaces block address；

Multiple caches from this cache buffer keep in partly seamless and continuously output data；

Set up in order to access a logical page address of this NAND gate flash memory array, this logical page address includes patrolling Collect block address part；

The described logic damage block address of this inquiry table buffer is searched described logic damage block address wherein it Whether meet between one and this logical block addresses part；

When one first cache in keeping in partly from those caches keeps in part output data, right from this cache buffer Data should partly be shifted and keep in part to one second cache, this second cache is kept in and is partially different than this first cache temporary storage part Point；

Keep in part output data in this first cache and shift after data keeps in the step of part to this second cache, to this Two caches are kept in part and are carried out an error-correcting code calculating；

After this first cache keeps in part output data and transfer data keeps in the step of part to this second cache, work as search Step described in logic damage block address and this logical block addresses part when all not meeting, using this logical page address From this NAND gate flash memory array, one page of data is read in this Data buffer, and work as described in the step searched When one of them of logic damage block address and this logic area address part meet, replace block address using described physics This page of data is read in this Data buffer by one of them, and it is corresponding that wherein said physics replaces one of this of block address In the described logic damage block address meeting this logical block addresses part this one of them；And

When keeping in part output data from this second cache, shift data to except this from the corresponding part of this Data buffer Second cache keeps in one of them of the temporary part of remaining those cache of part, and keeps in part to remaining those cache One of them should carry out this error-correcting code calculating.