CN105825894A

CN105825894A - Memory reading method and digital memory device

Info

Publication number: CN105825894A
Application number: CN201510005340.8A
Authority: CN
Inventors: 欧伦·麦克
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2015-01-07
Filing date: 2015-01-07
Publication date: 2016-08-03
Anticipated expiration: 2035-01-07
Also published as: CN105825894B

Abstract

The invention provides a memory reading method and a digital memory device. The digital memory device is divided into a data temporary memory and a data buffer of a cache register, an internal error correction code relative to the cache register and set by a user, and a rapid bad block management. When data reading is carried out, the internal error correction code is displayed by an error correction code status bit. The status (1:1) can represent that the output data of the whole multi-page includes a continuous read-out mode of more than 4 bit errors on each page, the state of the error correction code of each page or each page partition are required to be known, for the former, when the output page is finished, the state of the error correction code of the whole page is determined, and is stored in a state buffer; for the latter, before the corresponding page partition is output, the state of the error correction code of each page partition is determined and output. The error correction code treatment is integrated, and waiting time is not required.

Description

Memory reading method and digital memory device

Technical field

The present invention is related to digital memory device and operational approach thereof, integrates, particularly with regard to having, NAND gate flash memory and the operational approach thereof that error correcting code processes.

Background technology

NAND gate flash memory quite receives an acclaim in data store, because using single-layer type (singlelevelcell, SLC) memory cell dimensions of NAND gate flash memory is the least so that the single-layer type NAND gate flash memory of more than 512Mb at cost to quite having advantage in density.

NAND gate flash memory also data storage beyond various application in become the most welcome, including code mapping (codeshadowing).Limit although normally used single-layer type NAND gate flash memory has framework, usefulness, data integrity and failure area, making it be difficult to the application supporting to be suitable for the high speed code mapping of serial nor gate flash memory, various technology are developed so that NAND gate flash memory can be suitable for these application.

The problem that error correcting code (ErrorCorrectionCode, EEC) algorithm has been developed to manage data integrity.In a method, internal error correcting code calculates and has been performed when the page writes, and the error correcting code information of generation is stored in 64 extra character group (byte) regions being referred to as spare area of each page.When data read operation, error correcting code engine verifies data according to previously stored error correcting code information, and carries out the correction specified in limited scope.Checking and more positive status are by the first error correcting code state bit ECC-0 and the second error correcting code state bit ECC-1, according to following mode.When second error correcting code state bit ECC-1, the state of the first error correcting code state bit ECC-0 are (0:0), represent whole data and be output as successfully correcting without any error correcting code.When second error correcting code state bit ECC-1, the state of the first error correcting code state bit ECC-0 are (0:1), representing whole data and be output as successfully, the error correcting code of needs 1～4 bits/page corrects single page or multiple page.When second error correcting code state bit ECC-1, the state of the first error correcting code state bit ECC-0 are (1:0), represent the output of whole data in single page, only include the mistake of more than 4 bits, and cannot be repaired by error correcting code, these data are not suitable for using.In continuous read mode, an extra instruction can be used to read the page address (PageAddress, PA) of the page including this mistake.When second error correcting code state bit ECC-1, the state of the first error correcting code state bit ECC-0 are (1:1), represent the whole data output each page in multiple pages and include the mistake of more than 4 bits.In continuous read mode, extra instruction provides the page address having last page vicious, and other page addresses having the vicious page can't be carried report.

Summary of the invention

The present invention provides a kind of memory reading method and digital memory device, solves prior art and is difficult to support the problem that the high speed code mapping being suitable for serial nor gate flash memory is applied.

One embodiment of the invention is a kind of memory reading method, it is applicable to read data continuously from a digital memory device, the most above-mentioned digital memory device includes NAND gate flash memory array and the page buffer being mutually coupled, above-mentioned page buffer is at least divided into a Part I and a Part II, and memory reading method includes: from one first data of above-mentioned NAND gate flash memory array access one first page；In the above-mentioned Part I of above-mentioned page buffer, set up one first error correcting code from above-mentioned first data and process data；Judge that above-mentioned first error correcting code processes one first error correcting code state of data；Export above-mentioned first error correcting code from the above-mentioned Part I of above-mentioned page buffer and process data；First error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, sets up one second error correcting code from above-mentioned first data and process data in the above-mentioned Part II of above-mentioned page buffer；The above-mentioned first error correcting code state of data is processed and within the above-mentioned time setting up the step that above-mentioned second error correcting code processes data from above-mentioned first error correcting code, determining one second error correcting code state of one second data of a second page, above-mentioned second data include that above-mentioned first error correcting code processes data and above-mentioned second error correcting code processes data；Above-mentioned second error correcting code state is stored in a state buffer；First error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, from the data of above-mentioned NAND gate flash memory array access one first continuous page；Export above-mentioned second error correcting code from the above-mentioned Part II of above-mentioned page buffer and process data；Second error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, sets up one the 3rd error correcting code process data from the data of above-mentioned first continuous page in the above-mentioned Part I of above-mentioned page buffer；Judge that above-mentioned 3rd error correcting code processes one the 3rd error correcting code state of data；Export above-mentioned 3rd error correcting code from the above-mentioned Part I of above-mentioned page buffer and process data；Threeth error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, in the above-mentioned Part II of above-mentioned data buffer, sets up one the 4th error correcting code from the data of above-mentioned first continuous page and processes data；From above-mentioned 3rd error correcting code process data above-mentioned 3rd error correcting code state and in above-mentioned set up above-mentioned 4th error correcting code process data step time, judging one the 4th error correcting code state of one the 3rd data in a page 3 face, above-mentioned 3rd data include that above-mentioned 3rd error correcting code processes data and above-mentioned 4th error correcting code processes data；Store above-mentioned 4th error correcting code state in above-mentioned state buffer；And above-mentioned with above-mentioned output the 3rd error correcting code process data the step equitant time in, from the data of above-mentioned NAND gate flash memory array access one second continuous page.

Another embodiment of the present invention is a kind of digital memory device, including: a NAND gate flash memory array；One row decoder, is coupled to above-mentioned NAND gate flash memory array；One Data buffer, is coupled to above-mentioned NAND gate flash memory array, and includes at least one first data division and one second data division；One cache buffer, is coupled to above-mentioned Data buffer, and includes at least one first cache part and one second cache part, and above-mentioned first data division is corresponding to above-mentioned first cache part, and above-mentioned second data division is corresponding to above-mentioned second cache part；One error correcting code circuit, is coupled to above-mentioned cache buffer；One column decoder, is coupled to above-mentioned cache buffer；And a control circuit, it is coupled to above-mentioned row decoder, above-mentioned column decoder, above-mentioned Data buffer, above-mentioned cache buffer and above-mentioned error correcting code circuit.Above-mentioned control circuit includes multiple logic element and multiple buffer element, in order to perform following function: be loaded into one first data of a first page to above-mentioned Data buffer from above-mentioned NAND gate flash memory array；From the above-mentioned first cache part of above-mentioned cache buffer, one first data segments of one first data of above-mentioned first page is copied to the above-mentioned first cache part of above-mentioned cache buffer；Above-mentioned first data segments of above-mentioned first data is set up in the above-mentioned first cache part of above-mentioned cache buffer one first error correcting code and processes data；Judge that above-mentioned first error correcting code processes one first error correcting code state of data；Data are processed from above-mentioned first above-mentioned first error correcting code of cache part output of above-mentioned cache buffer；From above-mentioned second data division of above-mentioned Data buffer, one second data segments of above-mentioned first data of above-mentioned first page is copied to the above-mentioned second cache part of above-mentioned cache buffer；First error correcting code above-mentioned with above-mentioned output processes in the function equitant time of data, in the above-mentioned second cache part of above-mentioned cache buffer, set up one second error correcting code from above-mentioned second data segments of above-mentioned first data of above-mentioned first page and process data；From above-mentioned first error correcting code process data above-mentioned first error correcting code state and when part above-mentioned set up above-mentioned second error correcting code process data function when, determining one second error correcting code state of one second data of a second page, above-mentioned second data include that above-mentioned first error correcting code processes data and above-mentioned second error correcting code processes data；Above-mentioned second error correcting code state is stored in a state buffer；First error correcting code above-mentioned with above-mentioned output processes in the function equitant time of data, from above-mentioned NAND gate flash memory array, the data of one first continuous page is loaded into above-mentioned Data buffer；Data are processed from above-mentioned second above-mentioned second error correcting code of cache part output of above-mentioned cache buffer；One first continuous page section of the data of above-mentioned first continuous page is copied to from above-mentioned first data division of above-mentioned Data buffer the above-mentioned first cache part of above-mentioned cache buffer；Second error correcting code above-mentioned with above-mentioned output processes in the function equitant time of data, sets up one the 3rd error correcting code from the above-mentioned first continuous page section of the data of above-mentioned first continuous page and processes data in the above-mentioned first cache part of above-mentioned cache buffer；Judge that above-mentioned 3rd error correcting code processes one the 3rd error correcting code state of data；Data are processed from above-mentioned first above-mentioned 3rd error correcting code of cache part output of above-mentioned cache buffer；From above-mentioned second data division of above-mentioned Data buffer, one second continuous page section of the data of above-mentioned first continuous page is copied to the above-mentioned second cache part of above-mentioned cache buffer；Threeth error correcting code above-mentioned with above-mentioned output processes in the function equitant time of data, in the above-mentioned second cache part of above-mentioned cache buffer, set up one the 4th error correcting code from the above-mentioned second continuous page section of the data of above-mentioned first continuous page and process data；The above-mentioned 3rd error correcting code state of data is processed and when the above-mentioned function setting up above-mentioned 4th error correcting code process data of part from above-mentioned 3rd error correcting code, judging one the 4th error correcting code state of one the 3rd data in a page 3 face, above-mentioned 3rd data include that above-mentioned 3rd error correcting code processes data and above-mentioned 4th error correcting code processes data；Store above-mentioned 4th error correcting code state in above-mentioned state buffer；And threeth error correcting code above-mentioned with above-mentioned output process data the function equitant time in, from above-mentioned NAND gate flash memory array, the data of one second continuous page are loaded into above-mentioned Data buffer.

Another embodiment of the present invention is a kind of memory reading method, it is applicable to read data continuously from a digital memory device, the most above-mentioned digital memory device includes NAND gate flash memory array and the page buffer being mutually coupled, above-mentioned page buffer is at least divided into a Part I and a Part II, and described memory reading method includes: from one first data of above-mentioned NAND gate flash memory array access one first page；In the above-mentioned Part I of above-mentioned page buffer, set up one first error correcting code from above-mentioned first data and process data；Judge that above-mentioned first error correcting code processes one first error correcting code state of data；Export above-mentioned first error correcting code from the above-mentioned Part I of above-mentioned page buffer and process data；First error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, sets up one second error correcting code from above-mentioned first data and process data in the above-mentioned Part II of above-mentioned page buffer；The above-mentioned first error correcting code state of data is processed and within the above-mentioned time setting up the step that above-mentioned second error correcting code processes data from above-mentioned first error correcting code, determining one second error correcting code state of one second data of a second page, above-mentioned second data include that above-mentioned first error correcting code processes data and above-mentioned second error correcting code processes data；Store above-mentioned second error correcting code state；First error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, from the data of above-mentioned NAND gate flash memory array access one first continuous page；Export above-mentioned second error correcting code from the above-mentioned Part II of above-mentioned page buffer and process data, and export above-mentioned second error correcting code state from the step of the above-mentioned second error correcting code state of above-mentioned storage；Second error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, sets up one the 3rd error correcting code process data from the data of above-mentioned first continuous page in the above-mentioned Part I of above-mentioned page buffer；Judge that above-mentioned 3rd error correcting code processes one the 3rd error correcting code state of data；Export above-mentioned 3rd error correcting code from the above-mentioned Part I of above-mentioned page buffer and process data；Threeth error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, sets up one the 4th error correcting code from the data of above-mentioned first continuous page and process data in the above-mentioned Part II of above-mentioned data buffer；From above-mentioned 3rd error correcting code process data above-mentioned 3rd error correcting code state and in above-mentioned set up above-mentioned 4th error correcting code process data step time, judging one the 4th error correcting code state of one the 3rd data in a page 3 face, above-mentioned 3rd data include that above-mentioned 3rd error correcting code processes data and above-mentioned 4th error correcting code processes data；Store above-mentioned 4th error correcting code state；Threeth error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, from the data of above-mentioned NAND gate flash memory array access one second continuous page；And export above-mentioned 4th error correcting code process data from the above-mentioned Part II of above-mentioned page buffer, and export above-mentioned 4th error correcting code state from the step of the above-mentioned 4th error correcting code state of above-mentioned storage.

Another embodiment of the present invention is a kind of memory reading method, it is applicable to read data continuously from a digital memory device, the most above-mentioned digital memory device includes NAND gate flash memory array and the page buffer being mutually coupled, above-mentioned page buffer is at least divided into a Part I and a Part II, and described memory reading method includes: from one first data of above-mentioned NAND gate flash memory array access one first page；In the above-mentioned Part I of above-mentioned page buffer, set up one first error correcting code from above-mentioned first data and process data；Judge that above-mentioned first error correcting code processes one first error correcting code state of data；Export above-mentioned first error correcting code and process data；After above-mentioned first error correcting code of above-mentioned output processes the step of data, export above-mentioned first error correcting code from the above-mentioned Part I of above-mentioned page buffer and process data；First error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, from above-mentioned NAND gate flash memory array access one first continuous page data；First error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, sets up one second error correcting code from above-mentioned first data and process data in the above-mentioned Part II of above-mentioned page buffer；Determine that one second error correcting code processes one second error correcting code state of data；Export above-mentioned second error correcting code state；After the step of the above-mentioned second error correcting code state of above-mentioned output, export above-mentioned second error correcting code from the above-mentioned Part II of above-mentioned page buffer and process data；Second error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, sets up one the 3rd error correcting code process data from the data of above-mentioned first continuous page in the above-mentioned Part I of above-mentioned page buffer；Judge that above-mentioned 3rd error correcting code processes one the 3rd error correcting code state of data；Export above-mentioned 3rd error correcting code and process data；After above-mentioned 3rd error correcting code of above-mentioned output processes the step of data, export above-mentioned 3rd error correcting code from the above-mentioned Part I of above-mentioned page buffer and process data；Threeth error correcting code above-mentioned with above-mentioned output processes in the step equitant time of data, from the data of above-mentioned NAND gate flash memory array access one second continuous page；And threeth error correcting code above-mentioned with above-mentioned output process data the step equitant time in, set up one the 4th error correcting code from the data of above-mentioned first continuous page in the above-mentioned Part II of above-mentioned page buffer and process data.

The present invention provides a kind of memory reading method and digital memory device, has less pin number purpose encapsulated type；Error correcting code can be integrated process, it is not necessary to the waiting time；Damage block management is not interfered with on the premise of ensureing data output speed and seriality.

Accompanying drawing explanation

Fig. 1 shows the flow chart operating in a continuous reading according to the NAND gate flash memory described in one embodiment of the invention；

Fig. 2 shows according to the functional schematic during the reading continuously an of part of Fig. 1 of the page buffer with Data buffer and cache buffer described in one embodiment of the invention；

Fig. 3 shows the functional schematic during the reading continuously of another part of Fig. 1 of the page buffer with Data buffer and cache buffer；

Fig. 4 shows the functional schematic during the reading continuously of another part of Fig. 1 of the page buffer with Data buffer and cache buffer；

Fig. 5 shows the functional block diagram of the pipeline circuit for error correcting code state pipeline operation；

Fig. 6 shows the signal timing diagram participating in having the various signals of the page buffer of Data buffer and cache buffer as Figure 1-Figure 4；

Fig. 7 shows that NAND gate flash memory operates in the flow chart of reading continuously；

Fig. 8 shows the signal timing diagram participating in having the various signals of the page buffer of Data buffer and cache buffer as shown in Figure 7；

Fig. 9 shows that NAND gate flash memory operates in the flow chart of reading continuously；

Figure 10 shows the signal timing diagram participating in having the various signals of the page buffer of Data buffer and cache buffer as shown in Figure 9；

Figure 11 shows the signal timing diagram of the various signals of the page buffer of the deformation participating in Fig. 9；And

Figure 12 shows the functional block diagram of serial NAND gate flash memory.

Symbol description:

210 data bus-bars；220 error correcting code circuit；

230 cache buffers；240 Data buffer；

250 NAND gate flash memory arrays；

252 first pages；254 second pages；

260 very first time axles；270 second time shafts；

280 the 3rd time shafts；300 error correcting code blocks；

302 next page error correcting code state bits；

304 current page fault more code mode bit units；

310 page datas read instruction；330,360 waiting time；

340,370 data command is read；

320,350,380 reading state buffer instruction；

390FFh instructs；

600 serial NAND gate flash memories；

622 i/o controllers；623 state buffers；

624 continuous pages read address register；

625 order buffers；626 address registers；

627LUT buffer；628 counterlogics；

629 address counters；630 control logic；

631 continuous pages read failure area logic；

632 continuous page failure area buffers；

633 high voltage generators；634 row decoders；

635 power-on detector；636 column decoders；

638 page buffers；

640 NAND gate flash memory arrays；

The 642 addressable regions of NAND gate flash memory array user；

644 redundancy block regions；646LUT information block；

647 buffer mode flags；648ECC-E flag；

650, ECC-0 the first error correcting code state bit；

651, ECC-1 the second error correcting code state bit；

652, the busy bit of BUSY；

DR-0 the first data division；DR-1 the second data division；

CR-0 the first cache part；CR-1 the second cache part；

A first period；The B second phase；

Between the C1+C2 third phase；Between the D fourth phase；

The E period 5；During F1+F2+F3 the 6th；

During G the 7th；During H the 8th；

During I the 9th；During J1+J2 the tenth；

BS confirms busy bit；CLK clock signal；

The chip select signal that/CS is anti-phase；

DI input serial data signal；DO serial data output signal；

ES error correcting code state bit；I/O input/output；

LUT look-up table；SP spare area；

The write protect signal that/WP is anti-phase；

Maintenance signal anti-phase for/HOLD；ECC_EN enable signal；

ECC_UPDATE more new signal；VCC power line supply voltage；

GND earth terminal；

100～160,400～442,500～542 process steps.

Detailed description of the invention

NAND memory device can make, including (1) multi input/output (I/O) Serial Peripheral Interface (SPI) (SPI)/FASTTRACK (QPI) interface with the characteristic that the numerous characteristics of AND OR NOT gate storage arrangement is compatible；(2) less pin number purpose encapsulated type (density is 256Mb or higher 8*6mm), such as, the WSON of 8 contact points, the SOIC of 16 foot positions and the BGA type package of 24 balls, have and use the big elasticity encapsulating (as is common for the VBGA-63 of the most parallel or general serial NAND Flash formula memorizer)；(3) high clock frequency operation (such as 104MHz) is to high transfer rate (such as the 50MHz/ second)；(4) map, for fast coding, the leap page boundary applied read continuously and there is error correcting code process, without the waiting time；(5) via being sent to external system and not having dysgenic damage block management (badblockmanagement) in the speed and seriality of output, the memorizer that logicality ground continuous print indicates；And (6) set by user or manufacturer set value, determine export initial address be in logical zero or memory array the address that user can be specified any one.Continuously read mode is particularly suitable for coding mapping to performing (execute-in-place, XIP) and big message, image, word and the data segments of quick-searching in random access memory (RAM), chip.

Many skills can reach rapidly and effectively read operation continuously, as the Data buffer of cache buffer of Data buffer and subregion with subregion, user can configure the internal error correcting code relevant with cache buffer and quickly damage block management.In order to the skill overcoming framework, usefulness, unreliability and damage block to limit, make it difficult to support high spped coding mapping and entitled " MethodandApparatusforReadingNANDFlashMemory ", inventor Guptaetal., announce in the US patent number 8 on March 4th, 2014,667,368；Entitled " On-ChipBadBlockManagementforNANDFlashMemory ", inventor Michaeletal., it is disclosed in December, 2013 U.S. Patent Publication No. of 26 days 2013/0346671；And entitled " NANDFlashMemory ", inventor Jigouretal., apply for the patent application number 13/799,215 on March 13rd, 2013；And the application performed in the chip of relative NAND gate flash memory, all these all it is expressly incorporated herein it at this all as reference.

The W25N01GV that one device of continuous read operation is produced by the winbond electronics company (WinbondElectronicsCorporation) being positioned at San Jose,California,USA is provided, it is described as winbond electronics company W25N01GV in the preliminary version B that on November 26th, 2013 proposes, there is two/tetra-Serial Peripheral Interface (SPI)s and the 3V Serial Peripheral Interface (SPI) flash type 1G bit serial single-layer type NAND gate flash memory read continuously, at this, entire contents is incorporated in this.W25N01GV device is incorporated to a traditional large-scale NAND gate non-volatility memorizer space, particularly arranges the 1G bit memory array to 2048 bit groups of 65536 programmable page.This device is also incorporated into Serial Peripheral Interface (SPI) (SerialPeripheralInterface, SPI), Serial Peripheral Interface (SPI) includes single bit serial (bit-serial) Serial Peripheral Interface (SPI), and Double-bit serial (dualserial), nibble serial (quadserial) and four input/output Serial Peripheral Interface (SPI)s.Serial Peripheral Interface (SPI) clock frequency can support up to 104MHz, when dual input/output/tetra-input/output instruction is quickly read in use, permission equivalent clocking rate 208MHz (104MHz*2) is to dual input/output, and allows equivalent clocking rate 416MHz (104MHz*4) to four input/output.W25N01GV is installed between the buffering read mode (BUF=1) of the data in order to access page buffer and the continuous read mode (BUF=0) in order to the whole memory array that access has one reading command efficiently and switches.

W25N01GV device has effective error correcting code ability to manage the integrity of data.When data read operation, data verified in a limited degree by error correcting code engine, and correct.Checking and more positive status can be by represented by the second error correcting code state bit ECC-1 and the first error correcting code state bit ECC-0.Such as, when the state of the second error correcting code state bit ECC-1, the first error correcting code state bit ECC-0 is (1:1), it is only applicable to continuous read mode, represents the output of whole data and includes each page mistake more than 4 bits at multi-page.In continuous read mode, extra instruction provides the page address (PageAddress, PA) having the vicious last page, and the address of other mistake pages can't be carried report.Second error correcting code state bit ECC-1, the state of the first error correcting code state bit ECC-0 be (1:1) generally the most enough because the bit mistake per-page in the page accessed is the most rare more than 4 bits.But, in certain embodiments, some error correcting code state that may wish to know each page.

Fig. 1 is in order to show the operational flowchart performing have the continuous page read step 100 of the error correcting code state of one page then one page, Fig. 2-Fig. 4 display performs many operations in the particular electrical circuit of NAND gate flash memory device, and Fig. 6 shows the various signals participating in these operations.One page then one page error correcting code state model can be with any desired mode enable and anergy, and an exemplary skill is set by the bit set by a user (set) and reset (reset).

No matter responding page data when automatically powering on (such as NAND gate flash memory array page zero) or reset to read instruction (with reference to the page data reading instruction 310 of Fig. 6) or in the way of any other needs, it is loaded into a page to page buffer (step 110).As shown in Figure 2, two single page buffer cooperations and page buffer is provided, particularly Data buffer 240 is divided into the first data division DR-0 and the second data division DR-1, and cache buffer 230 is divided into the first cache part CR-0 and the second cache part CR-1 corresponding the first data division DR-0 and the second data division DR-1 to Data buffer 240.nullWhen first period A，First page 252 is loaded into Data buffer 240，First page 252 is copied to cache buffer 230 at second phase B subsequently, and (first page 252 can the most all replicate，Or reproducible first cache part CR-0 to cache buffer 230 of the first data division DR-0 of only Data buffer 240)，And C1+C2 performs between the third phase in the first cache part CR-0 of cache buffer 230 error correction coded program，Time needed for wherein C1 represents and transferred data to the first error correcting code state bit ECC-0 of error correcting code circuit 220 by the first cache part CR-0，C2 is similarly represented as being transferred data to the time needed for the first cache part CR-0 by the first error correcting code state bit ECC-0.If necessary, error correction coded program also can be implemented in the second cache part CR-1 of cache buffer 230 between the fourth phase in (not display in figure), these operations are all continuous print, and therefore these times are accumulation, as shown in very first time axle 260.

With further reference to Fig. 1, confirm reading state buffer (0Fh/05h) instruction (with reference to the reading state buffer instruction 320 of Fig. 6) of the address of the available state buffer with busy bit BUSY of state (step 120) of busy bit (BS).State buffer bit is moved to D0 foot position at the falling edge of clock signal CLK subsequently.Error correcting code state bit (ES) can also this mode access, although may be left in the basket at this moment.The instruction of reading state buffer can be used for any time, therefore allow to confirm busy bit BUSY and determine when loop ends and whether device can accept another instruction, state buffer can read continuously, and this instruction can be completed to high logic level by driving anti-phase chip select signal/CS.

When after the time taking buffer instruction 320 (Fig. 6) in read states, when busy bit BUSY is eliminated (step 120 is confirmed as no) and receives reading data command 340 (Fig. 6) (step 122 is confirmed as), a continuous page reading can be carried out by performing error correction coded program, and can alternately export data from the first cache part CR-0 of cache buffer 230 and the second cache part CR-1, further coordinate and replicate from the data of Data buffer 240 to cache buffer 230 and the loading of the page subsequently, as being loaded into continuous second page 254 to the Data buffer 240 from NAND gate flash memory array 250.As shown in step 130, step 132 and step 134, read data command 340 (Fig. 6) and betide three different operatings of substantially overlapping identical time and carry out simultaneously, namely outputting data to data bus-bar 210 from the first cache part CR-0 of cache buffer 230, perform error correcting code in the second cache part CR-1 of cache buffer 230 and the continuous second page 254 of NAND gate flash memory array 250 is loaded into Data buffer 240.As shown in Figure 3, the data of output betide D between the fourth phase, error correction coded program betides the 6th period F1+F2+F3 and the page is loaded into and betides the 7th period G, wherein between the fourth phase, D, the 6th period F1+F2+F3 and the 7th period G are just as shown in the second time shaft 270, the most overlapped.Second cache part CR-1 of the E the second data division DR-1 to cache buffer 230 in order to replicate Data buffer 240 between the short fifth phase, when between the fifth phase after E the followed by the 6th period F1+F2+F3 and the 7th period G, can and the fourth phase between D overlap.

Carry out the first cache part CR-0 of cache buffer 230 and the second cache part CR-1 for the page data of error correction coded program reads the first reading data command after instruction, the period 5 E and the 6th period F1+F2+F3 of error correction coded program replicating data to be omitted.

The error correcting code state bit of the page and next page may utilize pipeline at present, has ensured that the data synchronised of error correcting code state bit and output.When the error correction coded program of the page register of Part II completes, the error correcting code state bit of the page can be finally confirmed (step 132) at present, it is latching to state buffer subsequently in the 6th period F3 (Fig. 3), make in the case of adjusting the error correcting code state bit in state buffer the most too early, to determine the error correcting code state bit of next page.Fig. 5 shows the demonstrative circuit being adapted for carrying out pipeline operation.When, after the signal ECC_EN enable that is enabled, error correcting code block 300 performs error correction coded program.Next page error correcting code state bit 302 can update the next page error correcting code state from error correcting code block 300 according to clock signal CLK.When completing next page error correcting code state bit 302 and essentially becoming current page fault more code mode bit unit, current page fault can be latching to and updated code state bit 304 under the control of more new signal ECC_UPDATE and clock signal CLK.If necessary, current page fault more code mode bit unit 304 can be stored in state buffer.Current page fault in state buffer more code mode bit unit thus with output page synchronization, the new next page error correcting code state bit 302 of next page in the case of adjusting the error correcting code state bit in state buffer the most too early, can be determined.

Then, as shown in step 140 and step 142, two different operatings betide in the most equitant time, namely output data to data bus-bar 210 from the second cache part CR-1 of cache buffer 230, and when the first cache part CR-0 of cache buffer 230 performs error correcting code, start to determine error correcting code state.As shown in Figure 4, the data of output betide the 8th substantially overlapping period H shown in the 3rd time shaft 280 and the tenth period J1+J2.Betide the error correction coded program of the tenth period J1+J2 and start to determine next page error correcting code state bit, but adequate measures, such as pipeline operation, may be used to guarantee that the page dimensions of output is held effectively by current page fault more code mode bit unit.First cache part CR-0 of the 9th short period I the first data division DR-0 to cache buffer 230 in order to replicate Data buffer 240, when after the 9th period I then the tenth period J1+J2, then overlapping with the 8th period H.

Then, continuous page reads and can suspend in page boundary (step 150), in order to read the error correcting code state bit of the corresponding just page of output.The technology being suitable for suspending continuous page reading is, after reading last page bit group, anti-phase chip select signal/CS to be pulled to high logic level.When enable one page then one page error correction pattern, the when that anti-phase chip select signal/CS being changed into high logic level, suspend built-in function so that controller may utilize reading state buffer instruction (step 160) (with reference to the reading state buffer instruction 350 of Fig. 6) and reads the error correcting code state of the just page of output.When busy bit is eliminated (not display) and (with reference to the waiting time 360 of Fig. 6) after suitable latent period, then send reading data command (with reference to the reading data command 370 of Fig. 6) to recover continuous page read operation.

After reading the error correcting code state bit of the last page of continuous page read operation (with reference to the reading state buffer instruction 380 of Fig. 6), can terminate that there is the carrying out that the continuous page of one page then one page error correcting code reads in any desired mode, as by sending FFh after the page boundary FFh of the Fig. 6 (instruction 390) and instruct suspending, or when page data exports, anti-phase chip select signal/CS is pulled to high logic level.

Fig. 7 shows the flow chart performing have the various operations of the continuous read step 400 of one page then one page error correcting code state, wherein continuous page reads instruction and effectively exports the continuous page of not only data, more exports the error correcting code state bit of each continuous page.For example, the most as shown in figs 2-4 and the corresponding mode described, page buffer is provided in conjunction with the page register of one page subregion and the cache buffer of one page subregion.Fig. 8 shows the various signals participating in these operations.One page then one page error correcting code state model can be with any desired mode enable and anergy, and an exemplary skill is set by the bit set by a user (set) and reset (reset).

With reference to Fig. 7, when energising automatically (page 0 of such as NAND gate flash memory array) or responding page data reads instruction or in any other desired mode, a page is loaded into page buffer (step 410).This page is copied to cache buffer (this page can all be replicated, or the Part I of only Data buffer can be copied to the Part I of cache buffer) subsequently, and error correction coded program can be implemented in the Part I of cache buffer.

Referring again to Fig. 7, reading state buffer (0Fh/05h) instruction of the address of the available state buffer with busy bit, confirm the state of busy bit (BS).State buffer bit when the negative edge of clock signal CLK, is moved to serial data output signal DO subsequently.When busy bit is eliminated, data command (step 422 is yes) is read in (step 420 is no) and reception, the available error correction coded program performing data carries out continuous page reading, and can alternately export data from the first cache part CR-0 of cache buffer and the second cache part CR-1, further coordinate and replicate to the data of cache buffer from Data buffer and be loaded into Data buffer from the page subsequently of NAND gate flash memory array.As shown in step 430, step 432 and step 434, read data and betide three different operatings of substantially overlapping identical time and carry out simultaneously, namely outputting data to data bus-bar from the first cache part CR-0 of cache buffer, perform error correcting code in the second cache part CR-1 of cache buffer and the continuous page of NAND gate flash memory array is loaded into Data buffer.The at present page and the error correcting code state bit of next page, can as shown in Figure 3-Figure 5 and the mode of narration and pipeline operation, to guarantee the page synchronised of error correcting code state bit and output.Then, as shown in step 440 and step 442, two different operations betide in the most identical time, namely after outputting data to data bus-bar from the second cache part CR-1 of cache buffer, output error more code mode bit unit, and at the first cache part CR-0 execution error correcting code of cache buffer.

After the last page of continuous page read operation and the error correcting code state bit of the last page are read, the continuous page with one page then one page error correcting code reads and can terminate in any desired mode, as in output page data shown in Fig. 8 when, anti-phase chip select signal/CS is pulled to high logic level.

Fig. 9 shows that the continuous page performing have an a subregion then subregion error correcting code state reads the flow chart of the various operations of 500, wherein continuous page reads instruction not only to exporting the data of continuous page effectively, also effective to the error correcting code state bit of each subregion of each continuous page.Furthermore, error correcting code state can supply in the page premise of output.In this way, user can learn whether these data can use before reading data, it is also possible to grasps the position of mistake bit the most accurately at which.For example, generally as shown in Fig. 2-Fig. 4 figure and narration mode, provide page buffer in conjunction with the page register of one page subregion and the cache buffer of one page subregion.Figure 10 shows the various signals participating in these operations.An one subregion then subregion error correcting code state model can be with any desired mode enable and anergy, and an exemplary skill is set by the bit set by a user (set) and reset (reset).

With reference to Fig. 9, no matter automatically powering on (such as NAND gate flash memory) or responding page data and read instruction or in the way of any other needs, it is loaded into a page to page buffer (step 510).This page is copied to cache buffer (this page can overall be replicated or the Data buffer of only Part I is copied to the cache buffer of Part I) subsequently, and error correction coded program is implemented in the cache buffer of Part I.

Referring again to Fig. 9, instruct by having the reading state buffer (0Fh/05h) of the address of the state buffer of busy bit, confirm the state (step 520) of busy bit (BS).State buffer bit when the negative edge of clock signal CLK, is moved to serial data output signal DO subsequently.When busy bit is eliminated (step 520 is no) and receives reading data command (step 522 is yes), the available error correction coded program performing data carries out continuous page reading, and can alternately export data from the first cache part CR-0 of cache buffer and the second cache part CR-1, further coordinate and replicate to the data of cache buffer from Data buffer and be loaded into Data buffer from the page subsequently of NAND gate flash memory array.As shown in step 530, step 532 and step 534, read data and betide three different operatings of substantially overlapping identical time and carry out simultaneously, namely outputting data to data bus-bar (step 530) from the first cache part CR-0 of cache buffer, perform error correcting code in the second cache part CR-1 of cache buffer and result be latching to error correcting code state bit (step 532) and the continuous page of NAND gate flash memory array is loaded into Data buffer (step 534).The page and the error correcting code state bit of next page at present, can as shown in Figure 3-Figure 5 and narration mode and pipeline operation, to guarantee the page synchronised of error correcting code state bit and output, and error correcting code state can be reseted after latching every time.Then, as shown in step 540 and step 542, two different operations betide in the most identical time, namely export the first error correcting code state bit to data bus-bar (step 540) from the second cache part CR-1 of cache buffer, and at the first cache part CR-0 execution error correcting code of cache buffer, and result is latching to error correcting code state bit (step 542).

After the last page of continuous page read operation and the error correcting code state bit of the last page are read, the continuous page with an a subregion then subregion error correcting code reads and can terminate in any desired mode, such as in page data exports when (not display), anti-phase chip select signal/CS is pulled to high logic level.

In certain embodiments, user may want to access the data of the spare area of each page.The method of Fig. 9 can somewhat be adjusted to, and utilizes and exports the part data of spare area along with the Part I data of cache buffer, and export the part data of spare area along with the Part II data of cache buffer, and reaches this purpose.As shown in figure 11, wherein SP represents spare area (sparearea) to corresponding signal, and EC represents error correcting code state bit.It addition, whole spare area can be as the Part I data of the cache buffer of part or Part II data.

Serial NAND gate flash memory framework

Figure 12 shows the functional block diagram of serial NAND gate flash memory 600, serial NAND gate flash memory 600 can provide the continuous reading crossing over page boundary, and from the reading of continuous print storage address in logic without waiting for the time, serial NAND gate flash memory 640 also is able to provide the error correcting code status information of one page then one page.Serial NAND gate flash memory 600 includes NAND gate flash memory array 640 and relevant page buffer 638.NAND gate flash memory array 640 includes wordline (OK) and bit line (arranging), and is positioned over the addressable region of NAND gate flash memory array user 642, redundancy block region (redundantblockarea) 644 and look-up table (LUT) information block 646.Any required flash memory monotechnics can be used for the flash memory unit of NAND gate flash memory array 640.Serial NAND gate flash memory 600 can include other circuit various to support memorizer write, to wipe and read, as row decoder 634, column decoder 636, i/o controller 622, state buffer 623, continuous page read address register 624, order buffer 625, address register 626, look-up table (LUT) buffer 627, control logic 630, continuous page reads bad block logic 631, continuous page bad block buffer 632 and high voltage generator 633.Row decoder 634 user control and in certain embodiments under internal control, NAND gate flash memory array selects the row in the addressable region of user 642, and selects redundancy block region 644 and the row of look-up table (LUT) information block 646 under internal control.Power line is utilized to supply voltage VCC and earth terminal GND, it is provided that all circuit (not display in figure) of power supply to serial NAND gate flash memory 600.When serial NAND gate flash memory 600 can encapsulate in any desired mode and have the interface of any pattern, including general NAND gate flash memory interface, the control logic 630 of Figure 12 exemplarily realizes Serial Peripheral Interface (SPI) (SPI)/FASTTRACK (QPI) agreement, including multiple input and output Serial Peripheral Interface (SPI).The details of other Serial Peripheral Interface (SPI)s (SPI)/FASTTRACK (QPI) interface and the various different circuit of memorizer, the US patent number 7 that can propose on July 7th, 2009 in Jigouretal., 558, entitled " SerialFlashSemiconductorMemory " of 900 and aforementioned winbond electronics are in the preliminary version B that on November 26th, 2013 proposes, there is two/tetra-Serial Peripheral Interface (SPI)s and the W25N01GV of the continuous 3V1G bit serial single-layer type NAND gate flash memory read, at this, entire contents is incorporated in this.

If pattern switching is as expection, it is possible to provide buffer mode flag (BUF) 647.If necessary, it is possible to provide buffer mode flag (BUF) 647 is as a bit of state buffer 623.Power-on detector 635 is provided in control logic 630, to start the setting of AD HOC and to be loaded into the default page when an energising.

Busy bit 652 is the only read bit unit of state buffer, and when device energising or execution many instructions, busy bit 652 can be set to the state of logic 1, reads instruction including page data and reads instruction continuously.

Page buffer 638 includes single page Data buffer (not display in figure), single page cache buffer (not display in figure) and single page gate (not display in figure), in order to the data of Data buffer are copied to cache buffer.Any applicable latch or memory technology can be used for Data buffer and cache buffer, and any suitable gate technology can be used for the data of Data buffer are copied to cache buffer.Data buffer and cache buffer can the block of any be intended to number arrange, and such as transmission gate (transmissiongate) is line and for controlling the transmission of data.For example, Data buffer and cache buffer are respectively divided into two different parts, and use indivedual groups of transmission gate by unit control line traffic control and alternately operate.The Data buffer of page buffer 638 and cache buffer identical can control signal to individual transport lock control line and operate in a conventional manner by applying, maybe can apply suitable time control signal to transmission gate control line blocked operation.For example, in two-part embodiment, the page is 2K character group, the half page (1K) of transmission gate can be controlled by a control line, second half page (1K) of transmission gate can be controlled by another control line, therefore arranges Data buffer and cache buffer in the part of two and half pages (1K).Because two part blocked operations, can be considered " table tennis (pingpong) " buffer with the page buffer 638 that two parts realize.Error correcting code circuit (not display in figure) may be used to according to ECC-E flag (ECC-E) 648, performs the content to cache buffer and performs error correcting code calculating.First error correcting code state bit (ECC-0) 650 and the second error correcting code state bit (ECC-1) 651 are in order to represent the error condition of the data in related pages, after completing read operation and verify that data complete, can confirm that the error condition of data in the page.If necessary, ECC-E flag (ECC-E) the 648, first error correcting code state bit (ECC-0) 650 and the second error correcting code state bit (ECC-1) 651 can be as the parts of state buffer 623.

If necessary, different size of page buffer can be used, and/or page buffer is divided into and also may be used more than two parts or unequal part.Possible two groups of control signals of needs are to two parts of page buffer, unlike only needing one group of control signal to undivided page buffer.Furthermore, the difference of the NAND gate flash memory array of logicality and physical property, do not interfere with teaching in this.For example, physical property NAND gate flash memory array can have two pages (the even number 2KB page and the odd number 2KB page) in a wordline so that a wordline can be the NAND gate flash memory bitcell array of 4KB.In order to understand expression, description in this and accompanying drawing are all according to logicality NAND gate flash memory array.Error correcting code circuit 220 can be considered have part the first error correcting code state bit ECC-0 of the content false more code in order to provide the first cache part CR-0 of a part and in order to provide part the second error correcting code state bit ECC-1 of the content false more code of the second cache part CR-1 in logic.Various error correcting code algorithms all be suitable for use, including as Hamming error correcting code algorithm, BCH error correcting code algorithm, Reed-Solomon error correcting code algorithm and other etc..When docking with the first cache part CR-0 and the second cache part CR-1 respectively for the purpose of simplifying the description and by the first error correcting code state bit ECC-0 and the second error correcting code state bit ECC-1, the error correcting code block of two physical properties or a single one physical error correcting code block may be used to connect with the first cache part CR-0 and the second cache part CR-1 interface.About page buffer 638, error correcting code circuit and other related contents of its operation, can be in the US patent number 8 of aforementioned entitled " MethodandApparatusforReadingNANDFlashMemory ", obtain in 667,368, only entire contents is incorporated in this at this.Continuous page described herein reads in aforesaid patent specifications, is referred to as " adjusting continuous page to read ".Data buffer and cache buffer enter the portion schedules of the page and the part of the page perform the mode of error correcting code only in order to purposes of discussion, are used as other technologies if necessary.

When serial NAND gate flash memory 600 is in order to perform various read operation, including continuous page read operation and perform error correcting code on chip in single plane NAND gate flash memory framework, these frameworks are exemplary and its deformation is understood that.It is understood that the example of the page-size of 2KB and particular block size is only in order to purposes of discussion, the most also can be different.Furthermore, because the big I of actual pages is different according to design factor, concrete dimension reference not one-sided are by literal upper explanation, such as this term can include the main region spare area plus extra 64 character groups of 2048 character groups, wherein spare area is in order to store error correcting code and other information, such as background data (metadata).The term of 1KB can be main region and the spare area of 32 character groups of 1024 character groups.For convenience of description, when description in this is according to single plane framework, teaching in this is also equally applicable to many Flat Architectures.When using multiple physical property plane, one or many wordline can be shared and make accumulator system can service the multi input/output simultaneously required.Each plane provides a page of data, and includes Data buffer and the cache buffer of a corresponding page-size of a corresponding page-size.Skill described herein can be applied individually to any each plane, make each Data buffer and cache buffer be arranged in different parts, or can be applicable to many planes and make each Data buffer and cache buffer be itself multi-page Data buffer and a part for cache buffer.

Figure 12 displays that the anti-phase chip select signal/CS for Serial Peripheral Interface (SPI), clock signal CLK, input serial data signal DI, serial data output signal DO, anti-phase write protect signal/WP and anti-phase maintenance signal/HOLD.The Serial Peripheral Interface (SPI) flash type interface of standard is along with anti-phase write protect signal/WP and anti-phase maintenance signal/HOLD, it is provided that anti-phase chip select signal/CS, clock signal CLK, input serial data signal DI and serial data output signal DO.When the bit serial data bus-bar in standard Serial Peripheral interface, (data input via input serial data signal DI, and data export via serial data output signal DO) provide simple interface and with start when the compatibility of many controllers of single Serial Peripheral Interface (SPI) pattern, which limit the probability reaching higher handling capacity (thru-put).The interface of many bits Serial Peripheral Interface (SPI) thus add, and support that the dual pathways (two bit interfaces) and/or four-way (nibble interface) are to increase the handling capacity read extraly.Figure 12 displays that dual pathways Serial Peripheral Interface (SPI) and the extra data bus signals of four-way Serial Peripheral Interface (SPI) operation, namely by optionally redefining I/O (0), I/O (1), I/O (2) and the function of I/O (3) these four foot positions.Four-way Serial Peripheral Interface (SPI) read operation (also contemplating in other embodiments) in the embodiment of an explanation, an available bit standard Serial Peripheral interface provides suitable reading instruction via I/O (0), but the interface of address and output data can be four-way (namely nibble data bus-bar).Compared with the data exporting a bit in standard Serial Peripheral interface read operation, four-way Serial Peripheral Interface (SPI) read operation can export the data of nibble in a clock cycle, thus four-way Serial Peripheral Interface (SPI) read operation can provide four times of high read throughputs.Four-way Serial Peripheral Interface (SPI) read operation in this is merely to illustrate and is used, teaching in this also can be applied in the same manner to other operator schemes, include but not limited to single serial peripheral bus-bar, dual pathways serial peripheral bus-bar, four Peripheral Interface (QuadPeripheralInterface, and the read mode such as double transfer rate (DoubleTransferRate, DTR) QPI).In four Peripheral Interface agreements, complete interface (operation code, address and data output) is based on nibble.In double transfer rate is reached an agreement on, output data are provided in the just triggering edge of clock signal CLK and negative triggering edge, rather than as in single transfer rate (SingleTransferRate, STR) read mode, the only negative triggering edge in clock signal CLK provides output data.

The narration of the present invention includes that it is only purposes of discussion in this application carried and advantage, and is not used to the scope limiting the invention in claim.The deformation of embodiment described herein and amendment are all possibility, and those skilled in the art also both know about actual replacement and are equal to the various elements of the present invention, can obtain via research patent specification.For example, although many embodiments described herein are for serial NAND gate flash memory, particular mechanics described herein such as power-up sequence, model selection and cross over page boundary with from logicality ground connected storage address and without waiting for Time Continuous data output etc., can be used for parallel NAND gate flash memory.Furthermore, at this, given special value is purposes of discussion, can revise voluntarily if necessary.Vocabulary such as " first " and " second " etc., is construed to implicit order or a holistic specific part for distinguishing vocabulary.The deformation of these or other embodiment described herein and adjustment, including replacement and the equivalent of embodiment described herein, can obtain, including the claim of the present invention under without departing substantially from the scope of the present invention and spirit.

Claims

1. a memory reading method, it is characterized in that, it is applicable to read data continuously from a digital memory device, wherein said digital memory device includes NAND gate flash memory array and the page buffer being mutually coupled, described page buffer is at least divided into a Part I and a Part II, and described memory reading method includes:

One first data from described NAND gate flash memory array access one first page；

In the described Part I of described page buffer, set up one first error correcting code from described first data and process data；

Judge that described first error correcting code processes one first error correcting code state of data；

Export described first error correcting code from the described Part I of described page buffer and process data；

First error correcting code described with described output processes in the step equitant time of data, sets up one second error correcting code from described first data and process data in the described Part II of described page buffer；

The described first error correcting code state of data is processed and within the described time setting up the step that described second error correcting code processes data from described first error correcting code, determining one second error correcting code state of one second data of a second page, described second data include that described first error correcting code processes data and described second error correcting code processes data；

Described second error correcting code state is stored in a state buffer；

First error correcting code described with described output processes in the step equitant time of data, from the data of described NAND gate flash memory array access one first continuous page；

Export described second error correcting code from the described Part II of described page buffer and process data；

Second error correcting code described with described output processes in the step equitant time of data, sets up one the 3rd error correcting code process data from the data of described first continuous page in the described Part I of described page buffer；

Judge that described 3rd error correcting code processes one the 3rd error correcting code state of data；

Export described 3rd error correcting code from the described Part I of described page buffer and process data；

Threeth error correcting code described with described output processes in the step equitant time of data, in the described Part II of described data buffer, sets up one the 4th error correcting code from the data of described first continuous page and processes data；

From described 3rd error correcting code process data described 3rd error correcting code state and in described set up described 4th error correcting code process data step time, judging one the 4th error correcting code state of one the 3rd data in a page 3 face, described 3rd data include that described 3rd error correcting code processes data and described 4th error correcting code processes data；

Store described 4th error correcting code state in described state buffer；And

Threeth error correcting code described with described output processes in the step equitant time of data, from the data of described NAND gate flash memory array access one second continuous page.

2. memory reading method as claimed in claim 1, it is characterised in that

Described page buffer includes a cache buffer and a Data buffer, described cache buffer is at least divided into one first cache part and one second cache part, described Data buffer is at least divided into one first data division and one second data division, described first data division is corresponding to described first cache part, and described second data division is corresponding to described second cache part；

The described step setting up described second error correcting code process data, is included in the described second cache part of described cache buffer execution error correction coded program and sets up described second error correcting code in described second cache part and process data；

The step of described first continuous page of described access, including being loaded into described first continuous page to described Data buffer；

Described second error correcting code of described output processes the step of data, including from the described second cache part of described cache buffer, exports described second error correcting code and processes data；

The described step setting up described 3rd error correcting code process data, the described first cache part being included in described cache buffer performs error correction coded program, sets up described 3rd error correcting code in described first cache part and processes data；

Described 3rd error correcting code of described output processes the step of data, processes data including from described first described 3rd error correcting code of cache part output of described cache buffer；And

The step of described second continuous page of described access, including being loaded into described second continuous page to described Data buffer.

3. memory reading method as claimed in claim 1, it is characterised in that described digital memory device also includes the input receiving a chip select signal, and described memory reading method also includes:

After completing the step of the described second error correcting code state of described storage, the step of the described second error correcting code process data of described output and the described step setting up described 3rd error correcting code process data, postpone described 3rd error correcting code of described output and process the step of data, to respond the transition of described chip select signal；

Receive a reading state buffer instruction；

Export described state buffer, to respond the step of described reception described reading state buffer；

After completing the step of described output described state buffer, receive a buffer readout order；And

The step that threeth error correcting code described with described output processes data together responds the step of the described buffer readout order of described reception.

4. a digital memory device, it is characterised in that described digital memory device includes:

One NAND gate flash memory array；

One row decoder, is coupled to described NAND gate flash memory array；

One Data buffer, is coupled to described NAND gate flash memory array, and includes at least one first data division and one second data division；

One cache buffer, is coupled to described Data buffer, and includes at least one first cache part and one second cache part, and described first data division is corresponding to described first cache part, and described second data division is corresponding to described second cache part；

One error correcting code circuit, is coupled to described cache buffer；

One column decoder, is coupled to described cache buffer；And

One control circuit, it is coupled to described row decoder, described column decoder, described Data buffer, described cache buffer and described error correcting code circuit, wherein said control circuit includes multiple logic element and multiple buffer element, in order to perform following function:

It is loaded into one first data of a first page to described Data buffer from described NAND gate flash memory array；

From described first data division of described Data buffer, one first data segments of described first data of described first page is copied to the described first cache part of described cache buffer；

Described first data segments of described first data is set up in the described first cache part of described cache buffer one first error correcting code and processes data；

Data are processed from described first described first error correcting code of cache part output of described cache buffer；

From described second data division of described Data buffer, one second data segments of described first data of described first page is copied to the described second cache part of described cache buffer；

First error correcting code described with described output processes in the function equitant time of data, in the described second cache part of described cache buffer, set up one second error correcting code from described second data segments of described first data of described first page and process data；

The described first error correcting code state of data is processed and when carrying out the described function setting up described second error correcting code process data of part from described first error correcting code, determining one second error correcting code state of one second data of a second page, described second data include that described first error correcting code processes data and described second error correcting code processes data；

Described second error correcting code state is stored in a state buffer；

First error correcting code described with described output processes in the function equitant time of data, from described NAND gate flash memory array, the data of one first continuous page is loaded into described Data buffer；

Data are processed from described second described second error correcting code of cache part output of described cache buffer；

One first continuous page section of the data of described first continuous page is copied to from described first data division of described Data buffer the described first cache part of described cache buffer；

Second error correcting code described with described output processes in the function equitant time of data, sets up one the 3rd error correcting code from the described first continuous page section of the data of described first continuous page and processes data in the described first cache part of described cache buffer；

Data are processed from described first described 3rd error correcting code of cache part output of described cache buffer；

From described second data division of described Data buffer, one second continuous page section of the data of described first continuous page is copied to the described second cache part of described cache buffer；

Threeth error correcting code described with described output processes in the function equitant time of data, in the described second cache part of described cache buffer, set up one the 4th error correcting code from the described second continuous page section of the data of described first continuous page and process data；

The described 3rd error correcting code state of data is processed and when the described function setting up described 4th error correcting code process data of part from described 3rd error correcting code, judging one the 4th error correcting code state of one the 3rd data in a page 3 face, described 3rd data include that described 3rd error correcting code processes data and described 4th error correcting code processes data；

Store described 4th error correcting code state in described state buffer；And

Threeth error correcting code described with described output processes in the function equitant time of data, from described NAND gate flash memory array, the data of one second continuous page is loaded into described Data buffer.

5. a memory reading method, it is applicable to read data continuously from a digital memory device, it is characterized in that, described digital memory device includes NAND gate flash memory array and the page buffer being mutually coupled, described page buffer is at least divided into a Part I and a Part II, and described memory reading method includes:

Store described second error correcting code state；

Export described second error correcting code from the described Part II of described page buffer and process data, and export described second error correcting code state from the step of the described second error correcting code state of described storage；

Threeth error correcting code described with described output processes in the step equitant time of data, sets up one the 4th error correcting code from the data of described first continuous page and process data in the described Part II of described data buffer；

Store described 4th error correcting code state；

Threeth error correcting code described with described output processes in the step equitant time of data, from the data of described NAND gate flash memory array access one second continuous page；And

Export described 4th error correcting code from the described Part II of described page buffer and process data, and export described 4th error correcting code state from the step of the described 4th error correcting code state of described storage.

6. a memory reading method, it is applicable to read data continuously from a digital memory device, it is characterized in that, described digital memory device includes NAND gate flash memory array and the page buffer being mutually coupled, described page buffer is at least divided into a Part I and a Part II, and described memory reading method includes:

Export described first error correcting code and process data；

After described first error correcting code of described output processes the step of data, export described first error correcting code from the described Part I of described page buffer and process data；

First error correcting code described with described output processes in the step equitant time of data, from described NAND gate flash memory array access one first continuous page data；

Determine that one second error correcting code processes one second error correcting code state of data；

Export described second error correcting code state；

After the step of the described second error correcting code state of described output, export described second error correcting code from the described Part II of described page buffer and process data；

Export described 3rd error correcting code and process data；

After described 3rd error correcting code of described output processes the step of data, export described 3rd error correcting code from the described Part I of described page buffer and process data；

Threeth error correcting code described with described output processes in the step equitant time of data, sets up one the 4th error correcting code process data from the data of described first continuous page in the described Part II of described page buffer.

7. memory reading method as claimed in claim 6, it is characterised in that described memory reading method also includes:

Simultaneously, corresponding described first error correcting code of output processes one first spare area of data to the step of the first error correcting code state described with described output；

Simultaneously, corresponding described second error correcting code of output processes one second spare area of data to the step of the second error correcting code state described with described output；And

Simultaneously, corresponding described 3rd error correcting code of output processes one the 3rd spare area of data to the step of the 3rd error correcting code state described with described output.