CN105824719B - A kind of detection method and system of random access memory - Google Patents
A kind of detection method and system of random access memory Download PDFInfo
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- CN105824719B CN105824719B CN201610150312.XA CN201610150312A CN105824719B CN 105824719 B CN105824719 B CN 105824719B CN 201610150312 A CN201610150312 A CN 201610150312A CN 105824719 B CN105824719 B CN 105824719B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Abstract
The present invention provides a kind of detection method of random access memory and systems, which comprises the connectivity port of second processor monitoring first processor and primary random access memory；Data are written to the first address of the primary random access memory if listening to the first processor, obtain the data, and the second address that spare random access memory will be written after the data-conversion；If listening to first address reading data of the first processor from the primary random access memory, obtain the data that the first processor is read from first address, and from second address reading data, the data read from first address are compared with the data read from second address, detection signal is exported according to comparison result.As it can be seen that the present invention can the data transmission in real time to primary random access memory detect, and do not need that data are all written in all addresses, to reduce time-consuming.And common cause failure factor can be avoided well.
Description
Technical field
The present invention relates to industrial control fields, more particularly, to the detection method and system of a kind of random access memory.
Background technique
Synchronous DRAM (English: Synchronous Dynamic Random Access Memory, referred to as
) etc. SDRAM random access memory have the characteristics that price is low, data transmission rate is high, manufacturing process is simple, are widely used in digital electricity
In the system of road.
However, there are certain lists when data are transmitted for random access memory since electromagnetic interference or defective workmanship etc. influence
The probability of bit status overturning mistake, the data transmission of mistake may result in system operation and mistake occurs, or even threaten system
Safety.Due to random access memory usually not self-checking function, how the data transmission of random access memory is detected, be to protect
Hinder the key factor of system safety operation.
A kind of common detection mode is, before the formal use of random access memory, to all addresses of random access memory
Write-in data and the data for reading write-in detect random access memory by being compared the data of reading with the data of write-in
Data transmission it is whether normal.
However, this detection mode can only be detected before the formal use of random access memory, real-time is very poor, cannot
Detect the overturning mistake occurred in use process.And it needs that number is all written in all addresses of random access memory when detecting
According to detection takes a long time.
Summary of the invention
Present invention solves the technical problem that be to provide the detection method and system of a kind of random access memory, it can with realization
The data transmission of random access memory is detected in real time, and does not need that number is all written in all addresses of random access memory
According to reduce time-consuming.
For this purpose, the technical solution that the present invention solves technical problem is:
The present invention provides a kind of detection methods of random access memory, which comprises
The connectivity port of second processor monitoring first processor and primary random access memory；
If listen to the first processor to the first address of the primary random access memory be written data, described second
Processor obtains the data, and the second address that spare random access memory will be written after the data-conversion；
If listening to first address reading data of the first processor from the primary random access memory, described second
Processor obtains the data that the first processor is read from first address, and from the second of the spare random access memory
Address reading data；
The data that the first processor that the second processor will acquire, described is read from first address, and from institute
The data for stating the reading of the second address are compared, and export detection signal according to comparison result.
Optionally, it if the comparison result indicates the data read from second address, is read with from first address
Match after the data-conversion taken, the detection signal is initial signal；
If the comparison result indicates the data read from second address, with the data read from first address
It is mismatched after negating, the detection signal is abnormal signal.
Optionally, described to include: according to comparison result output detection signal
Detection signal is exported to the first processor according to comparison result.
Optionally, if the detection signal is abnormal signal；The method also includes:
The second processor receives the clear signal that the first processor is sent；
The second processor exports initial signal to the first processor.
Optionally, second address is determined according to first address.
Optionally, further includes:
If listening to the first processor data are written to the third address of the primary random access memory and receive
When error injection signal, the second processor obtains the data being written to the third address, and writes direct described spare
4th address of random access memory；
If listening to third address reading data of the first processor from the primary random access memory, described second
Processor obtains the data that the first processor is read from the third address, and from the 4th of the spare random access memory the
Address reading data；
The data that the first processor that the second processor will acquire, described is read from the third address, and from institute
The data for stating the reading of the 4th address are compared, and generate testing result according to comparison result.
The present invention provides a kind of detection system of random access memory, first processor is connected with primary random access memory,
Second processor is connected with the connectivity port of first processor and primary random access memory, and with spare random access memory phase
Even；The system comprises: the second processor and the spare random access memory；
The second processor is for monitoring the connectivity port；If listen to the first processor to it is described it is primary with
Data are written in first address of machine memory, obtain the data, and described spare deposit at random will be written after the data-conversion
Second address of reservoir；If listening to first address reading data of the first processor from the primary random access memory,
The data that the first processor is read from first address are obtained, and are read from the second address of the spare random access memory
Access evidence；
The second processor is also used to, the data that the first processor will acquire, described is read from first address,
It is compared with the data read from second address, detection signal is exported according to comparison result.
Optionally, it if the comparison result indicates the data read from second address, is read with from first address
Match after the data-conversion taken, the detection signal is initial signal；
If the comparison result indicates the data read from second address, with the data read from first address
It is mismatched after negating, the detection signal is abnormal signal.
Optionally, the second processor is also connected with the first port of the first processor, and the first port is not
It is same as the connectivity port；
When exporting detection signal according to comparison result, the second processor is specifically used for according to comparison result to described
The first port output detection signal of first processor.
Optionally, the second processor is also connected with the second port of the first processor, and the second port is not
It is same as the connectivity port；
If the detection signal is abnormal signal, the second processor is also used to receive the institute of the first processor
The clear signal for stating second port transmission exports initial signal to the first port of the first processor.
Optionally, second address is determined according to first address.
Optionally, the second processor is also connected with the third port of the first processor, and the third port is not
It is same as the connectivity port；
The second processor is also used to, if listening to third of the first processor to the primary random access memory
When address is written data and receives the error injection signal that the third port is sent, obtain to third address write-in
Data, and write direct the 4th address of the spare random access memory；If listening to the first processor from described primary
The third address reading data of random access memory, obtains the data that the first processor is read from the third address, and from
4th address reading data of the spare random access memory；
The second processor is also used to, the data that the first processor will acquire, described is read from the third address,
It is compared with the data read from the 4th address, testing result is generated according to comparison result.
According to the above-mentioned technical solution, in the embodiment of the present invention, second processor can monitor first processor and primary
The connectivity port of random access memory is written when listening to the first processor to the first address of the primary random access memory
The second address of spare random access memory can will be written in data after the data-conversion, when listen to the first processor from
First address reading data of the primary random access memory, the second processor can obtain the first processor from described
The data that first address is read, and from the second address reading data of the spare random access memory, and will be from first ground
The data that location and second address are read are compared, and export detection signal according to comparison result.As it can be seen that the embodiment of the present invention
In can the data transmission in real time to random access memory detect, and do not need that data are all written in all addresses, from
And it reduces time-consuming.In addition, the embodiment of the present invention when to spare random access memory storing data, can carry out inversion operation to data
It is stored again afterwards, can be avoided common cause failure factor.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, it can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is a kind of Transmission system in the prior art；
Fig. 2 is a kind of flow diagram of embodiment of the method provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of storage system provided in an embodiment of the present invention；
Fig. 4 is the flow diagram of another embodiment of the method provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another storage system provided in an embodiment of the present invention；
Fig. 6 is the data flow schematic diagram of CPLD provided in an embodiment of the present invention.
Specific embodiment
The Transmission system of random access memory from first processor 101 to random access memory 102 as shown in Figure 1, can be written
Data can also read data from random access memory 102 by first processor 101.Usually not certainly due to random access memory
How checking functions detect the data transmission of random access memory, are the key factors of safeguards system safe operation.
A kind of common detection mode is, before random access memory use, is written to all addresses of random access memory
Data and the data for reading write-in detect the number of random access memory by being compared the data of reading with the data of write-in
It is whether normal according to transmitting.However, this detection mode real-time is very poor, the overturning occurred in use process mistake cannot be detected
Accidentally.And detection takes a long time.Additionally there are two types of detection modes, and one is the address of cache function using embedded OS
It is able to achieve the self-test of random access memory, another kind is the error detection and report machine built-in using embedded processor architecture
System is detected.Both modes are required dependent on embedded processing systems, and development cost is high, and broad applicability is poor.
The embodiment of the present invention provides the detection method and system of a kind of random access memory, can be in real time to random with realization
The data transmission of memory is detected, and does not need that data are all written in all addresses of random access memory, to reduce
It is time-consuming.Also, it does not need to be succeeded in developing low to which broad applicability is high by means of embedded processing systems.In addition it is used
It is bypass detection mode, the normal use of random access memory will not be impacted detection function error.
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without creative efforts, all should belong to protection of the present invention
Range.
Referring to Fig. 2, the embodiment of the invention provides a kind of embodiments of the method for the detection method of random access memory.
The present embodiment can be used in storage system as shown in Figure 3, the system include first processor 301, it is primary with
Machine memory 302, second processor 303 and spare random access memory 304.Wherein, first processor 301 and primary random storage
Device 302 is connected, so that first processor 301 can carry out data transmission with primary random access memory 302, for example, the first processing
Device 301 is written data or first processor 301 to primary random access memory 302 and reads number from primary random access memory 302
According to.
The embodiment of the present invention method includes:
S201: the connectivity port of second processor 303 monitoring first processor 301 and primary random access memory 302.
Wherein, second processor 303 is connected with the connectivity port of first processor 301 and primary random access memory 302, from
And the connectivity port is monitored, determine whether first processor 301 carries out data transmission with primary stochastic processor 302.
S202: if listen to first processor 301 to the first address of primary random access memory 302 be written data, second
Processor 303 obtains the data that are written to first address of first processor 301, and will be written after the data-conversion it is spare with
Second address of machine memory 304.
In the embodiment of the present invention, if data, second processor is written to primary random access memory 302 in first processor 301
303 can listen to the write operation, and get the writing address (i.e. the first address) of the write operation, and the data are taken
Second address of the spare random access memory 304 of write-in after anti-.Wherein, the second address can be determined according to the first address.For example, the
One address is identical as the second address, and the first address can be the 0th to the 15th, and the second address may be the 0th to the 15th
Position.Second processor 303 is corresponding to store first address and second address.
Wherein, second processor 303 is not directly to write data into spare random access memory 304, but understand logarithm
It is stored again according to after being negated, common cause failure factor (mistake as caused by same problem) can be avoided well.It takes
Inverse operations is referred to the low and high level reversion in data.
S203: if listening to first address reading data of the first processor 301 from primary random access memory 302, second
Processor 303 obtains the data that read from the first address of primary random access memory 302 of first processor 301, and from it is spare with
Second address reading data of machine memory 304.
If first processor 301 reads the data having been written into, 303 meeting of second processor from primary random access memory 302
The read operation is listened to, the first address of the read operation is got, and obtains the data of read operation reading.In addition,
Second processor 303 can also get corresponding second address in the first address, and from the second address of spare random access memory 304
Read data.
S204: second processor 303 will acquire, first processor 301 is from the first address of primary random access memory 302
The data of reading are compared with second processor 303 from the data that the second address of spare random access memory 304 is read, root
Detection signal is exported according to comparison result.
Wherein, it if the comparison result indicates the data read from second address, is read with from first address
Data-conversion after match, the detection signal is initial signal, that is, indicates that this transmission is normal.Match and also refers to
Identical or identical ratio reaches predetermined percentage etc..If what the comparison result expression was read from second address
Data are mismatched with after the data-conversion that first address is read, and the detection signal is abnormal signal error_flag,
Indicate that mistake occurs in this transmission.
According to the above-mentioned technical solution, in the embodiment of the present invention, second processor 203 can monitor first processor 201
With the connectivity port of primary random access memory 202, when listening to first processor 201 to the first of primary random access memory 202
Data are written in address, and the second address of spare random access memory 204 can will be written after the data-conversion, when listening at first
First address reading data of the device 201 from primary random access memory 202 is managed, second processor 203 can obtain first processor 201
The data read from first address, from the second address reading data of spare random access memory 204, and will be from described first
The data that address and second address are read are compared, and export detection signal according to comparison result.As it can be seen that the present invention is implemented
For that the data to primary random access memory 202 can transmit in real time in the use process of primary random access memory 202 in example
It is detected, and is not needed that data are all written in all addresses, to reduce time-consuming.In addition, the embodiment of the present invention is to standby
When with 204 storing data of random access memory, stored again after inversion operation being carried out to data, can avoid well it is total because
Failure Factors.
In addition, method provided in an embodiment of the present invention is not needed by means of embedded processing systems, succeed in developing it is low to
Broad applicability is high.In addition it, will not be to primary random storage detection function error using bypass detection mode
The normal use of device impacts, to avoid the interruption of first processor read-write operation.If second processor or it is spare with
When machine memory occurs abnormal, it can be replaced using error detection error correction (Error Correcting Code, ECC) module, from
And realize the detection and recovery of wrong data.
In the present embodiment, first processor 301 can be central processing unit (Central Processing Unit, CPU)
Deng, and second processor 304 can for field programmable gate array (Field-Programmable Gate Array,
FPGA), Complex Programmable Logic Devices (Complex Programmable Logic Device, CPLD) etc..The present embodiment
In, primary random access memory 302 and spare random access memory 304 can be any random access devices, such as static random
Memory (Static Random Access Memory, SRAM), synchronous DRAM (Synchronous
Dynamic Random Access Memory, SDRAM), Double Data Rate synchronous DRAM (Double Data
Rate, DDR), DDR2, DDR3 etc..
In the embodiment of the present invention, second processor 303 can export detection signal to first processor 301.For example, if
Two processors 303 export initial signal (such as 0) to first processor 301, indicate that this transmission is normal, if second processor
303, to 302 output abnormality signal error_flag (such as 1) of first processor, indicate this transmission abnormality.Wherein, at first
Manage device 301 can by way of interruption processing detection signal.
If second processor 303 receives exception to 301 output abnormality signal of first processor, first processor 301
Corresponding processing mode, such as alarm etc. are made after signal, guarantee to find in time when data transmission exception.Wherein, first
Processor 301 can also send clear signal to second processor 303, after second processor 303 receives clear signal, according to
The clear signal exports initial signal.For example, the output of second processor 303 1, after receiving clear signal, output 0.
Error injection mode is also supported in the present embodiment, that is to say, that second processor 303 is to spare random access memory 304
It is written before data without inversion operation, but directly data is written.So that the inspection that second processor 303 exports
It surveys signal one and is set to abnormal signal, detect function for detecting the bypass that second processor 303 and spare random access memory 304 are realized
Can whether normal.
Specifically, if the method can also include: to listen to first processor 301 to primary random access memory 302
When third address is written data and receives error injection signal, second processor 303 obtains the data being written to third address,
And write direct the 4th address of spare random access memory 304；If listening to first processor 301 from primary random access memory
302 third address reading data, second processor 303 obtain third of the first processor 301 from primary random access memory 302
The data that address is read, and from the 4th address reading data of spare random access memory 304；That second processor 303 will acquire,
The data that first processor 301 is read from third address are compared, according to comparison result with the data read from the 4th address
Generate testing result.
The present invention is illustrated by a specific embodiment below.
Referring to Fig. 4, the embodiment of the invention provides another embodiments of the method for the detection method of random access memory.
The present embodiment is introduced by taking system shown in fig. 5 as an example, which includes CPU501, SDRAM502, CPLD503
And SDRAM504.Wherein, CPLD may include parsing module, data control block and diagnostic module.As it can be seen that in the present embodiment with
First processor is specially CPU, and second processor is specially CPLD, and random access memory is specially that SDRAM carries out exemplary introduction,
And it to this and is not limited in the embodiment of the present invention.
The embodiment of the present invention method includes:
S401: the connectivity port of parsing module monitoring CPU501 and SDRAM502.
S402: if parsing module, which listens to CPU501, sends control signal 01 to SDRAM502, which is solved
SDRAM504 is sent to as control signal 02 after analysis, it is ensured that SDRAM504 and SDRAM502 executes identical movement.
Such as shown in Fig. 6, control signal 01 includes address signal addr_bi [12:0], row gating signal cas_i, column selection
Messenger res_i and write enable signal we_i.Control signal 02 includes: address signal backup_addr_bo [12:0], row choosing
Messenger cas_o, column selection messenger res_o and write enable signal we_o.Wherein, write enable signal we_i and we_o is for enabling
Write operation, address signal addr_bi [12:0] write data into the first address, such as the 0th to the 15th, address for indicating
Signal backup_addr_bo [12:0] writes data into the second address, such as the 0th to the 15th for indicating.Row gating letter
Number and column selection messenger for enabling row address strobe and column address strobe.
S403: parsing module listen to CPU501 to SDRAM502 send control signal 01 when, data control block obtain
The data dq [15:0] that CPU501 is sent to SDRAM502, and obtained after data dq [15:0] is negated backup_dq [15:
0], data backup_dq [15:0] is sent to SDRAM504.The data that SDRAM502 can will be received according to control signal 01
The first address is written.The second address can be written according to control signal 02 in the data received by SDRAM504.
In the present embodiment, CPU501 can carry out 8 bits, 16 bits, 24 bits or burst mode to SDRAM502
Read-write operation, CPLD503 carry out the read-write operation of model identical to SDRAM504.
S404: if parsing module, which listens to CPU501, sends control signal 03 to SDRAM502, which is solved
SDRAM504 is sent to as control signal 04 after analysis.
Control signal 03 include address signal addr_bi [12:0], row gating signal cas_i, column selection messenger res_i and
Read enable signal rd_i.Control signal 04 includes: address signal backup_addr_bo [12:0], row gating signal cas_o, column
Gating signal res_o and reading enable signal rd_o.Wherein, enable signal rd_i and rd_o are read for enabling read operation, address letter
Number addr_bi [12:0] is for indicating that, from the first address reading data, address signal backup_addr_bo [12:0] is used for table
Show from the second address reading data.Row gating signal and column selection messenger are for indicating enabled row address strobe and column address choosing
It is logical.
S405: parsing module listen to CPU501 to SDRAM502 send control signal 03 when, data control block obtain
The data that CPU501 is read from SDRAM502, and data control block reads data from SDRAM504.Due to SDRAM502 and
SDRAM504 be respectively received control signal 03 and control signal 04, what data control block was got at this time be respectively from
The data that the first address of SDRAM502 and the second address of SDRAM504 are read, and the data read from the two addresses are sent out
It is sent to diagnostic module.
S406: diagnostic module will be compared from the data that the first address and the second address are read respectively, if comparison result
Indicate that the data low and high level read from the two addresses is opposite, then it represents that this transmission is normal, exports initial letter to CPU501
Number, this transmission abnormality is otherwise indicated, to CPU501 output abnormality signal.Such as shown in Fig. 6, diagnostic module output abnormality signal
error_flag.After diagnostic module receives the clear signal of CPU501, diagnostic module exports initial signal, and no longer exports
Abnormal signal error_flag.
Wherein, parsing module may also listen for other letters in addition to control signals that CPU501 is sent to SDRAM502
Number, such as configuration signal (including initial configuration), self refresh signal.Parsing module can believe configuration signal, self-refresh at this time
SDRAM504 is sent to after number equal parsing.
The present embodiment also supports error injection mode.If CPU501 sends error injection signal to CPLD503, data control
The data of reading can be write direct SDRAM504 by molding block, without inversion operation.
Corresponding above method embodiment, the present invention also provides a kind of implementations of method of the detection system of random access memory
Example.
As shown in figure 3, first processor 301 is connected with primary random access memory 302 in the present embodiment, second processor
303 are connected with the connectivity port of first processor 301 and primary random access memory 302, and second processor 303 and it is spare with
Machine memory 304 is connected；The embodiment of the present invention detection system includes: second processor 303 and spare random access memory 304.
In the present embodiment, second processor 303 is used to monitor the company of first processor 301 and primary random access memory 302
Connect port.So that it is determined that whether first processor 301 carries out data transmission with primary stochastic processor 302.
Second processor 303 is also used to, if listening to first processor 301 to the first ground of primary random access memory 302
Data are written in location, and second processor 303 obtains the data, and spare random access memory 304 will be written after the data-conversion
The second address.
Wherein, the second address can be determined according to the first address.For example, the first address is identical as the second address, the first ground
Location can be the 0th to the 15th, and the second address may be the 0th to the 15th.Second processor 303 is also used to correspondence and deposits
Store up first address and second address.
Second processor 303 is not directly to write data into spare random access memory 304 in the present embodiment, but meeting
It is stored again after being negated to data, common cause failure factor can be avoided well.
Second processor 303 is also used to, if listening to first processor 301 from the first ground of primary random access memory 302
Data are read in location, and second processor 303 obtains what first processor 301 was read from the first address of primary random access memory 302
Data, and from the second address reading data of spare random access memory 304.
Second processor 303 is also used to, and will acquire, first processor 301 is from the first ground of primary random access memory 302
The data that location is read, are compared with the data read from the second address of spare random access memory 304, defeated according to comparison result
Signal is detected out.
Wherein, it if the comparison result indicates the data read from second address, is read with from first address
Data-conversion after match, the detection signal is initial signal, that is, indicates that this transmission is normal.Match and also refers to
Identical or identical ratio reaches predetermined percentage etc..If what the comparison result expression was read from second address
Data are mismatched with after the data-conversion that first address is read, and the detection signal is abnormal signal error_flag,
Indicate that mistake occurs in this transmission.
As it can be seen that the detection system of the present embodiment is used in the use process of primary random access memory 202, it can be right in real time
The data transmission of primary random access memory 202 is detected, and does not need that data are all written in all addresses, to reduce consumption
When.In addition, the embodiment of the present invention is when to spare 204 storing data of random access memory, data can be carried out after inversion operation again
It is stored, common cause failure factor can be avoided well.
In addition, detection system provided in an embodiment of the present invention does not need to be succeeded in developing low by means of embedded processing systems
To which broad applicability is high.In addition it, will not be to primary random detection function error using bypass detection circuit
The normal use of memory impacts, to avoid the interruption of first processor read-write operation.If second processor is standby
When occurring abnormal with random access memory, it can be replaced using ECC module, to realize the detection and recovery of wrong data.
In the present embodiment, first processor 301 can be CPU etc., and second processor 304 can be FPGA, CPLD etc..
In the present embodiment, primary random access memory 302 and spare random access memory 304 can be any random access devices, such as
SRAM, SDRAM, DDR, DDR2, DDR3 etc..
In the embodiment of the present invention, second processor 303 can also be connected with the first port of first processor 301, described
First port is different from the connectivity port.Second processor 303 can be exported to the first port of first processor 301 and be detected
Signal.For example, indicate that this transmission is normal if second processor 303 exports initial signal (such as 0) to first port, if the
Two processors 303 indicate this transmission abnormality to first port output abnormality signal error_flag (such as 1).Wherein, first
Processor 301 can by way of interruption processing detection signal.
If second processor 303 is to the first port output abnormality signal of first processor 301, first processor 301
Corresponding processing mode, such as alarm etc. are made after receiving abnormal signal, guarantees to find in time when data transmission exception.
Wherein, second processor 303 can also be connected with the second port of first processor 301, and the second port is different from described
Connectivity port, first processor 301 can also send clear signal, second processor to the second port of second processor 303
After 303 receive clear signal, initial signal is exported to first port according to the clear signal.For example, second processor 303 to
First port output 1, after receiving clear signal, to first port output 0.
Error injection mode is also supported in the present embodiment, that is to say, that second processor 303 is to spare random access memory 304
It is written before data without inversion operation, but directly data is written.So that the inspection that second processor 303 exports
It surveys signal one and is set to abnormal signal, whether the detection system for detecting the present embodiment works normally.
Specifically, second processor 303 is also connected with the third port of first processor 301, and the third port is different
In the connectivity port.Second processor 303 is also used to, if listening to first processor 301 to primary random access memory 302
When third address is written data and receives the error injection signal that the third port is sent, obtains and write to the third address
The data entered, and write direct the 4th address of spare random access memory 304；If listen to first processor 301 from it is primary with
The third address reading data of machine memory 302 obtains first processor 301 from the third address of primary random access memory 302
The data of reading, and from the 4th address reading data of spare random access memory 304；Second processor 303 is also used to, will be from institute
The data for stating the reading of third address, are compared with the data read from the 4th address, are generated and are detected according to comparison result
As a result.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided by the present invention, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can be personal computer, server or the network equipment etc.) executes the complete of each embodiment the method for the present invention
Portion or part steps.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), magnetic or disk etc. are various can store journey
The medium of sequence code.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although referring to before
Stating embodiment, invention is explained in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (10)
1. a kind of detection method of random access memory, which is characterized in that the described method includes:
The connectivity port of second processor monitoring first processor and primary random access memory；
Data, the second processing is written to the first address of the primary random access memory if listening to the first processor
Device obtains the data, and the second address that spare random access memory will be written after the data-conversion；
If listening to first address reading data of the first processor from the primary random access memory, the second processing
Device obtains the data that the first processor is read from first address, and from the second address of the spare random access memory
Read data；
The data that the first processor that the second processor will acquire, described is read from first address, and from described
The data that double-address is read are compared, and export detection signal according to comparison result；
If listening to the first processor data are written to the third address of the primary random access memory and receive mistake
When Injection Signal, the second processor obtains the data being written to the third address, and writes direct described spare random
4th address of memory；
If listening to third address reading data of the first processor from the primary random access memory, the second processing
Device obtains the data that the first processor is read from the third address, and from the 4th address of the spare random access memory
Read data；
The data that the first processor that the second processor will acquire, described is read from the third address, and from described
The data that four addresses are read are compared, and generate testing result according to comparison result.
2. the method according to claim 1, wherein if the comparison result indicates to read from second address
Data, match with after the data-conversion that first address is read, the detection signal be initial signal；
If the comparison result indicates the data read from second address, with the data-conversion read from first address
After mismatch, the detection signal be abnormal signal.
3. the method according to claim 1, wherein described include: according to comparison result output detection signal
Detection signal is exported to the first processor according to comparison result.
4. according to the method described in claim 3, it is characterized in that, if the detection signal is abnormal signal；The method is also
Include:
The second processor receives the clear signal that the first processor is sent；
The second processor exports initial signal to the first processor.
5. the method according to claim 1, wherein second address is determined according to first address.
6. a kind of detection system of random access memory, which is characterized in that first processor is connected with primary random access memory, and second
Processor is connected with the connectivity port of first processor and primary random access memory, and is connected with spare random access memory；Institute
The system of stating includes: the second processor and the spare random access memory；
The second processor is for monitoring the connectivity port；If listening to the first processor primary to deposit at random to described
Data are written in first address of reservoir, obtain the data, and the spare random access memory will be written after the data-conversion
The second address；If listening to first address reading data of the first processor from the primary random access memory, obtain
The data that the first processor is read from first address, and number is read from the second address of the spare random access memory
According to；
The second processor is also used to, the data that the first processor will acquire, described is read from first address, with from
The data that second address is read are compared, and export detection signal according to comparison result；
The second processor is also connected with the third port of the first processor, and the third port is different from the connection
Port；
The second processor is also used to, if listening to the first processor to the third address of the primary random access memory
When data are written and receiving the error injection signal that the third port is sent, the number being written to the third address is obtained
According to, and write direct the 4th address of the spare random access memory；If listen to the first processor from it is described it is primary with
The third address reading data of machine memory, obtains the data that the first processor is read from the third address, and from institute
State the 4th address reading data of spare random access memory；
The second processor is also used to, the data that the first processor will acquire, described is read from the third address, with from
The data that 4th address is read are compared, and generate testing result according to comparison result.
7. system according to claim 6, which is characterized in that if the comparison result indicates to read from second address
Data, match with after the data-conversion that first address is read, the detection signal be initial signal；
If the comparison result indicates the data read from second address, with the data-conversion read from first address
After mismatch, the detection signal be abnormal signal.
8. system according to claim 6, which is characterized in that the second processor also with the first processor
Single port is connected, and the first port is different from the connectivity port；
When exporting detection signal according to comparison result, the second processor is specifically used for according to comparison result to described first
The first port output detection signal of processor.
9. system according to claim 8, which is characterized in that the second processor also with the first processor
Two-port netwerk is connected, and the second port is different from the connectivity port；
If the detection signal is abnormal signal, the second processor is also used to receive described the of the first processor
The clear signal that Two-port netwerk is sent exports initial signal to the first port of the first processor.
10. system according to claim 6, which is characterized in that determined according to first address second address.
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| CN107516546B (en) * | 2017-07-07 | 2020-09-22 | 中国航空工业集团公司西安飞行自动控制研究所 | Online detection device and method for random access memory |
| KR102131230B1 (en) * | 2018-11-26 | 2020-07-08 | 현대오트론 주식회사 | Method for self diagnosis of ram error detection logic in powertrain ecu system and apparatus thereof |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110675911B (en) * | 2019-09-24 | 2021-08-24 | 上海闻泰电子科技有限公司 | DDR (double data Rate) repairing method, device, terminal and storage medium |
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