CN102486938A - Method for rapid detection of memory and device - Google Patents
Method for rapid detection of memory and device Download PDFInfo
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Abstract
The invention provides a method for rapid detection of a memory. The method comprises: configurating data written into a memory address so as to make at least part of the data to traverse at least part of data bits in the memory for detecting the correctness of each of the data bits; traversing all memory addresses to conduct read-write detection; judging whether the written data traverse all the data bits, if not, repeating the following steps until the data traverse all the data bits: configurating data rewritten into the memory addresses from a first memory address so as to make the data to traverse undetected data bits for detecting the correctness of each of the data bits; traversing the memory addresses with written data for read-write detection. Correspondingly, the invention also provides a device for rapid detection of a memory. The method and device of the invention can conduct rapid parallel detection to an address line and a data line of a memory, with a simple realization method and without adding system complexity.
Description
Technical field
The present invention relates to technical field of information storage, relate in particular to a kind of method and device of fast detecting storer.
Background technology
Storer has obtained being widely used in various data control systems as memory device, and its stability and reliability directly have influence on the performance of The whole control system.Such as, in the control system of high speed transmission data, in order to guarantee the real-time of data; Need the high-speed transfer lot of data; Therefore, in this control system, need to use jumbo storer that data are carried out buffer memory, at this moment; The read or write speed of storer and the bandwidth availability ratio of storer directly have influence on the transmission speed of total system, and operability and stability that storer can reliablely and stablely be worked and will be had influence on total system especially.Therefore, when using storer, need the correctness of detection of stored device device itself and the accuracy of welding, and before system's operate as normal at every turn, need the employed storer of detection system whether can operate as normal first.After the detection of stored device can operate as normal, restart total system work, thereby guarantee to use the reliability and the correctness of the system of this storer.
Some storer detection techniques have been proposed at present; The basic ideas of center branch detection technique are at first with in the writing data into memory; And then from the storer data of reading back, and data that write and the data of reading back are compared, thereby judge whether memory read/write is correct.Such as; At application number is in the detection method that proposes of 00115308.0 Chinese patent " automatic testing method of random access memory and testing circuit thereof "; Through configuration testing data suitably with arrange test data to write and read sequential to come each test data is tested one by one, thereby realize high-level efficiency detection to data line and address wire; At application number is in the detection method that proposes of 200710073427.4 Chinese patent " a kind of memory device detecting method "; Divide three detection-phases that storer is detected, comprise that read-write detects, data line detects and address wire detects, wherein;, data line only need utilize the first address and the last address in the sector address space that need detect when being detected; When address wire is detected, only need utilize considerably less address location, thereby further improve detection efficiency; At application number is in the detection method that proposes of the one Chinese patent application " a kind of detection method of external memory storage and device " of 200810119303.X; Not testing of data one by one; But with the pseudo-random code that produces once in the write store; And then read back, and data of reading back and the pseudo-random code that writes are compared.
There is following problem in said method: 1, can not walk abreast and carry out, that is to say for the test of data line and address wire, can only be earlier to a kind of detection the in data line and the address wire, and then another kind is detected; 2, need store the test data of write store.
Summary of the invention
To the problems referred to above, the present invention provides a kind of method of fast detecting storer, to realize the fast parallel detection of data line and address wire.
In order to realize above purpose; The method of fast detecting storer provided by the invention may further comprise the steps: configuration writes the data of storage address, so that the correctness of each data bit in these data bit is detected in the position of partial data at least of the traversal of the partial data at least in these data storer; Travel through all storage addresss so that each storage address is read and write detection; Judge whether the data that write have traveled through all data bit; If the data that write have not traveled through all data bit; Then repeat following steps; Till having traveled through all data bit: configuration begins the data of write store address again from the storer first address, so that the also undetected data bit of these data traversals detects the correctness of each data bit in these data bit; Traversal writes the memory of data address again so that each storage address in these storage addresss is read and write detection.
Preferably, before traversal storage address and data bit, according to the address size of storer and all data of the pre-configured write store of data bits address.
Preferably, said read-write detects and may further comprise the steps: traversal will write the memory of data address, write data; Traversal writes the memory of data address, reading of data, and data that read and the data that write are compared; If the data that read from storage address are identical with the data that write this storage address; Judge that then the corresponding data line of data bit that is detected with the corresponding address wire of this storage address with these data is in proper working order, otherwise judge corresponding address wire and/or data line operation irregularity according to the data bit that these storage address and/or these data detected.
Preferably, whether monitoring read data and write data have traveled through all storage addresss and all data bit, and according to monitoring result dispose the data that write storage address, write data, reading of data and data that read and the data that write are compared.
Preferably, write to storage address data, reading of data and data that read and the data that write are compared one by one.
Preferably, before all storage addresss of traversal, the data that configuration writes storage address are this storage address itself; When all storage addresss of traversal; After writing the memory of data address reading data, when the address size of the no more than storer of data bits of storer, the low m position of the data that read and this storage address is compared; Wherein, m is the data bits of storer; When the data bits of storer during, directly the data that read and this storage address are compared more than the address size of storer; After having traveled through all storage addresss, if the data that write have not also traveled through all data bit, the data that then dispose again the write store address are the move to left value of n position of this storage address, and wherein, n is the address size of storer; After writing the memory of data address reading data again, the move to left value of n position of the data that read and this storage address is compared.
Preferably, be provided with respectively that write data has traveled through the zone bit of all storage addresss and zone bit that write data has traveled through all data bit representes whether write data has traveled through all storage addresss and whether write data has traveled through all data bit; When the zone bit that has traveled through all storage addresss when write data represented that write data travel through all storage addresss, disposing the data that write storage address was this storage address itself; After the storage address reading of data, if the address size of the no more than storer of data bits of storer, then the low m position with the data that read and this storage address compares; If the data bits of storer more than the address size of storer, then directly compares the data that read and this storage address; When the zone bit that has traveled through all storage addresss when write data represented that write data has traveled through all storage addresss, the data that configuration writes storage address were the move to left value of n position of this storage address; When the zone bit that has traveled through all data bit when write data represented that write data has traveled through all data bit, the move to left value of n position of the data that will read from storage address and this storage address compared.
Preferably, when configuration writes the storage address data, the length that config memory reads and writes data at every turn.
Preferably, judge according to the amount of capacity of storer and the length that reads and writes data of configuration at every turn whether write data and read data have traveled through all storage addresss; The length that at every turn reads and writes data according to amount of capacity, data bits and the configuration of storer judges whether write data and read data have traveled through all data bit.
Correspondingly; The present invention provides a kind of device of fast detecting storer; Comprise: dispensing unit; It was used for before all storage addresss of traversal, and configuration writes the data of storage address, so that the correctness of each data bit in these data bit is detected in the position of partial data at least of the traversal of the partial data at least in these data storer; After all storage addresss of traversal; If the data that write have not also traveled through all data bit; Then dispose from the storer first address and begin the data of write store address again, so that the also undetected data bit of these data traversals detects the correctness of each data bit in these data bit; Write data unit, it is used for writing the writing data into memory address of memory of data address with configuration according to the data traversal of dispensing unit configuration; Reading data unit, it is used for traversal and writes the memory of data address from the storage address reading of data; Comparing unit; The data that data that it is used for reading data unit is read from storage address and write data unit write this storage address compare; If the data that read are identical with the data that write; Judge that then the corresponding data line of data bit that is detected with the corresponding address wire of this storage address with these data is in proper working order, otherwise judge corresponding address wire and/or data line operation irregularity according to the data bit that these storage address and/or these data detected.
Preferably, dispensing unit is according to the address size of storer and all data of the pre-configured write store of data bits address.
Preferably; This device also comprises monitoring means; It is used to monitor read data and write data and whether has traveled through all storage addresss and all data bit, dispensing unit, write data unit, reading data unit and comparing unit respectively according to the monitoring result of monitoring means dispose the data that write storage address, write data, reading of data and data that read and the data that write are compared.
Preferably, write data unit, reading data unit and comparing unit write to storage address data, reading of data one by one and data that read and the data that write are compared.
Preferably, said dispensing unit is carried out following configuration operation: before all storage addresss of traversal, the data that configuration writes storage address are this storage address itself; After having traveled through all storage addresss, if the data that write have not also traveled through all data bit, the data that then dispose again the write store address are the move to left value of n position of this storage address, and wherein, n is the address size of storer.
Preferably; Said comparing unit is carried out following compare operation: when all storage addresss of traversal; After writing the memory of data address reading data, when the address size of the no more than storer of data bits of storer, the low m position of the data that read and this storage address is compared; Wherein, m is the data bits of storer; When the data bits of storer during, directly the data that read and this storage address are compared more than the address size of storer; After writing the memory of data address reading data again, the move to left value of n position of the data that read and this storage address is compared.
Preferably; This device also comprises monitoring means; It is used to monitor write data and whether read data has traveled through all storage addresss and data bit; And be provided with respectively that write data has traveled through the zone bit of all storage addresss and zone bit that write data has traveled through all data bit representes whether write data has traveled through all storage addresss and whether write data has traveled through all data bit; The zone bit that travel through all storage addresss when the write data that receives from monitoring means is represented write data having traveled through all storage addresss, and it is this storage address itself that dispensing unit disposes the data that write storage address; After the storage address reading of data, if the address size of the no more than storer of data bits of storer, then comparing unit compares the low m position of the data that read and this storage address at reading unit; If the data bits of storer is more than the address size of storer, then comparing unit directly compares the data that read and this storage address; When the zone bit that travel through all storage addresss when the write data that receives from monitoring means represented that write data has traveled through all storage addresss, it was the value of this n position, storage address left and right sides that dispensing unit disposes the data that write storage address; When the zone bit that has traveled through all data bit when write data represented that write data has traveled through all data bit, the move to left value of n position of the data that comparing unit will read from storage address and this storage address compared.
Preferably, when dispensing unit writes the storage address data in configuration, the length that config memory reads and writes data at every turn.
Preferably, monitoring means judges according to the amount of capacity of storer and the length that reads and writes data of configuration at every turn whether write data and read data have traveled through all storage addresss; The length that at every turn reads and writes data according to amount of capacity, data bits and the configuration of storer judges whether write data and read data have traveled through all data bit.
Through above technical scheme; Can obtain following technique effect: all data bit that the data of the write store that 1, passes through to be disposed can travel through storer are come the correctness of each data bit of detection of stored device; Like this; Can when can the traversal storage address detect each storage address and correctly read and write data, go back the correctness of each data bit of ergodic data position checking, thereby can carry out the concurrent reading and concurrent writing detection to the address wire of storer with data line apace; Implementation method is simple, does not increase the complexity of system; 2, be storage address through data configuration, needn't safeguard and store these data, thereby make detection method easier the write store address.
Description of drawings
Fig. 1 is the process flow diagram according to the method for the fast detecting storer of the embodiment of the invention;
Fig. 2 is the block diagram according to the device of the fast detecting storer of the embodiment of the invention.
Embodiment
Below, will describe the present invention with reference to accompanying drawing and embodiment.
In following embodiment with description; The data that configuration writes storage address are storage address; Like this; With regard to only needing the data that read and storage address are simply relatively come whether operate as normal of verifying memory, and needn't the data that configuration writes storage address be safeguarded and store, thereby further simplified memory device detecting method.Below, m representes the data bits of storer, n representes the address size of storer.
Traversal when can realize all storage addresss and all data bit, the main technical schemes of present embodiment is following.
When the address size of the no more than storer of data bits of storer, that is, the address size of storer more than or when equaling the data bit of storer, the data that write each storage address are this storage address itself.At this moment, when having traveled through all data bit, all storage addresss have not been traveled through, so still need continue in writing the memory of data address, not write data.At this moment; Not writing the data of being write in the memory of data address to these still can directly be storage address itself; But, after reading of data from these storage addresss, because the actual data that write have only the m position; So need the low m position of data value of reading and storage address be compared, up to having traveled through all storage addresss.
When the data bits of storer during more than the address size of storer; After having traveled through all storage addresss, still have part high position data position not test, therefore; Need recycle the address of storer; But at this moment the value of write store address need simply be handled, and no longer directly is storage address itself, the value of n position but storage address moves to left.
Fig. 1 is the process flow diagram according to the fast detecting memory approach of the embodiment of the invention.With reference to Fig. 1, this method may further comprise the steps:
The detection of step S100, startup primary memory;
Add up behind every write primary memory since 0 automatically in the address of step S101, configurable write storer, this address; Dispose the data value that each storage address writes and be this storage address itself; The pattern of configurable write storer promptly is provided with the length that at every turn reads and writes data;
Step S102, according to the memory write address of configuration, the operation of a memory write of the data of write store address and the length of write data initiation;
Step S103, judge based on the amount of capacity of selected memory model and the length that reads and writes data that has disposed at every turn whether write data has traveled through all storage address; If traveled through all storage address; Then continue execution in step S104; If do not traveled through all storage address, then jumped to step S102;
The operation of step S104, a memory read of initiation, wherein whenever read to add up automatically behind the primary memory since 0 in the address of memory read;
Whether step S105, the data that relatively read correct, particularly, when the address size of storer more than or when equaling data bits, whether the low m position of data that relatively read and memory read address consistent; When the address size of storer is less than data bits, data that directly relatively read and storer whether read the address consistent.If the data that this time read are correct, then continue execution in step S106, if the data that this time read are incorrect, then execution in step S114 reports an error, with error flag position 1, this EOT;
Step S106, judge based on the amount of capacity of memory model and the length that reads and writes data that has disposed at every turn whether read data has traveled through all storage address; If traveled through all storage address; Then continue execution in step S107; If do not traveled through all storage address, then jumped to step S104;
Step S107, based on the amount of capacity of memory model; Data bits and the length that at every turn reads and writes data that has disposed are judged and are write all data bit whether data have traveled through memory; If traveled through all data bit, execution in step S114 then, this EOT; If do not traveled through all data bit, then execution in step S108;
Step S108, to reconfigure the memory write address be 0, after having write primary memory, adds up automatically; The data that dispose again the write store address are to write the move to left value of n position of this storage address; The reason of carrying out this step is owing to implement data bits that this step just representes storer more than address size; When having traveled through all memory device addresses; All data bit have not also been traveled through; At this moment need recycle the address of storer, in storage address, write the data that are used to travel through the data bit that does not also travel through again, thereby realize the traversal of all data bit is detected;
Step S109, according to the memory write address of configuration, the operation of a memory write of the data of write store address and the pattern of memory write initiation;
Step S110, the amount of capacity based on the memory model, data bits and the length that at every turn reads and writes data that has disposed are judged and are write all data bit whether data have traveled through memory; If traveled through all data bit; Execution in step S111 then; If do not traveled through all data bit, then jumped to step S109;
The operation of step S111, a memory read of initiation, wherein whenever read to add up automatically behind the primary memory since 0 in the address of memory read;
Whether step S112, the data that relatively read be correct, and particularly, owing to implement data bits that this step promptly representes storer more than address size, therefore, whether the move to left value of n position of the data that relatively read and storage address is consistent; If the data that this time read are correct, then continue execution in step S113, if the data that this time read are incorrect, then report an error, with error flag position 1, execution in step S114, this EOT;
Step S113, the amount of capacity based on the memory model, data bits and the length that at every turn reads and writes data that has disposed judge whether read data has traveled through all data bit of memory; If traveled through all data bit; Execution in step S114 then; If do not traveled through all data bit, then jumped to step S111;
Step S114, this EOT.
In order to realize above method, the present invention provides the device of fast detecting storer shown in Figure 2.With reference to Fig. 2, this device comprises dispensing unit 201, write data unit 202, reading data unit 203, monitoring means 204 and comparing unit 205.The concrete operations of each unit are following.
Monitoring means 204 monitoring reads and writes data whether traveled through all storage addresss, and generation reads and writes data and traveled through the zone bit of all storage addresss; Monitoring reads and writes data whether traveled through all data bit, and generation reads and writes data and traveled through the zone bit of all data bit.When zone bit was 0, expression read data or write data had not traveled through all storage addresss or all data bit, and when zone bit was 1, expression expression read data or write data had traveled through all storage addresss or all data bit.
The address of the each read-write memory of dispensing unit 201 configurations, adding up after having read and write data since 0 in this address at every turn automatically, after having traveled through all memory addresss, adds up again since 0.Dispensing unit 201 also disposes the data that write each storage address based on the flag bit that data travel throughs all storage address of writing that receives from monitoring means 204; If this flag bit is 0, then disposes the data that write each storage address and be this storage address itself; If flag bit is 1, then the configuration data that write each storage address are the move to left value of n position of this storage address.Dispensing unit 201 is the pattern of configurable write storer also,, disposes the data length of each read-write memory that is.In addition, dispensing unit 201 also can dispose according to the amount of capacity of storer model and the length that reads and writes data that has disposed at every turn and will travel through the needed number of times that reads and writes data of all storage addresss and configuration will travel through the needed number of times that reads and writes data of all data bit.At this moment, monitoring means 204 can and travel through the needed number of times that reads and writes data of all data bit according to the intact needed number of times that reads and writes data of all storage addresss of the traversal of dispensing unit 201 configurations and detect to read and write data whether traveled through all storage addresss and all data bit.
Write data unit 202 travel through the address of the zone bit of all storage addresss and all data bit, memory write that dispensing unit 201 is disposed according to the write data that receives from monitoring means 204 and has write the data of each storage address, to write data of storer startup.Particularly; When the zone bit that has traveled through all storage addresss when the write data that receives from monitoring means 204 is 0; Continuation is according to dispensing unit 201 memory write address that is disposed and the data that write each storage address; Start a write data to storer, up to when this zone bit is 1, write data has traveled through all storage addresss.When the zone bit that has traveled through all data bit when the write data that receives from monitoring means 204 is 0; Continuation is according to dispensing unit 201 memory write address that is disposed and the data that write each storage address; Start a write data to storer; Up to when this zone bit is 1, write data has traveled through all data bit.
The data that the zone bit that comparing unit 205 travel through all storage addresss and all data bit according to the write data that receives from monitoring means 204 comes data that comparison reading unit 203 reads and write data unit 202 to write.Particularly, when the zone bit that has traveled through all storage addresss when the write data that receives from monitoring means 204 is 1, when the address size of storer more than or when equaling data bits, whether the low m position of data that relatively read and memory read address consistent; When the address size of storer is less than data bits, data that directly relatively read and storer whether read the address consistent.When the zone bit that has traveled through all data bit when the write data that receives from monitoring means 204 was 1, whether the move to left value of n position of the data that relatively read and memory read address was consistent.
Below, will come the inventive method is further specified through two concrete examples.
(first example)
In this example, storer to be detected is dynamic RAM SDRAM, and selected SDRAM model is MT48LC32M8A2, selects for use 4 this model SDRAM as storage stack, and the address size of this group storer is 25 like this, and data bits is 32.The length that at every turn reads and writes data of SDRAM can be set at 2,4,8 (unit is the data numbers); Perhaps can adopt the full-page pattern that the length that at every turn reads and writes data is set; That is, through the correlation parameter of SDRAM being set, each reading and writing data of realizing random length in admissible scope.About the particular content of the setting of the length that reads and writes data of SDRAM, can be referring to the service manual of MT48LC32M8A2 chip.In this example, the SDRAM according to selected model takes the full-page pattern, is the length setting that reads and writes data at every turn 512 (unit is the data numbers).
Before system's operate as normal, start the detection of a SDRAM, produce the address of writing SDRAM automatically, add up behind every write primary memory since 0 automatically in this address; Dispose the data value that each write address writes and be this write address, promptly 0 write data 0 in the address, 1 writes data 1 in the address, by that analogy, is superlatively writing data 1FFFFFF among the 1FFFFFF of location.Write data has traveled through after all SDRAM addresses, begins to start once from the SDRAM reading of data, and the address of reading of data that read and SDRAM is compared.In reading data course when the data that from SDRAM, read and memory read address are inconsistent; Like the data of from the 1FFFFFF of address, reading is 1FFFFFE; Explaining that then the lowest order data bit has problem, is 0 like the data of from the 1FFFFFF of address, reading, and then the corresponding memory address 1FFFFFF of explanation has problem; Do not have the correct data that write in this address, finish this and detect and the reporting errors position.When the data that from SDRAM, read were consistent with the memory read address, this time read data was correct, started next time from the SDRAM reading of data, had traveled through all address bits up to read data.When all storage addresss have traveled through, because data bits has 32, so only checked low 25 of data this moment; And high 7 of data also do not test, and therefore need recycle storage address, write data to address 0 again; At this moment 0 data that write no longer are 0 in the address; Should be that write address with this moment moves to left 25, promptly this moment, the data that write be 2000000, up to the data accumulation that writes to FFFFFFFF.Start again and read SDRAM; This moment the data that read and SDRAM being read the value that the address moves to left after 25 compares; In reading data course, move to left value after 25 when inconsistent when the data that from SDRAM, read and memory read address; Then corresponding data bit or the address bit of explanation has problem, finishes this and detects and the reporting errors position.When data that from SDRAM, read and memory read address move to left value after 25 when consistent; This time read data is correct, starts next time from the SDRAM reading of data, has traveled through all data bit up to read data; Thereby all data bit are all tested this EOT.
Be noted that in this example; Again before address 0 writes data; It is full that storage address has been write, and writes data more again after should reading these data earlier and finishing comparison, in order to avoid cover data that write originally but also do not read out when recycling address space.
With reference to Fig. 1, the concrete implementation procedure of this example is following:
Step S100, before system's operate as normal, start the detection of a SDRAM;
Step S101, automatically produce the address of writing SDRAM, this address is since 0, adds up automatically after whenever writing a SDRAM; Dispose the data value that each write address writes and be write address; Configuration full-page pattern;
Step S102, startup be write data in SDRAM once;
Step S103, judge whether write data has traveled through all SDRAM addresses; If write data does not have to have traveled through all SDRAM addresses, then repeated execution of steps S102 starts write data next time; If write data has traveled through all SDRAM addresses, then continue execution in step S104;
Step S104, startup be reading of data from SDRAM once;
Step S105, the address of reading of data that read and SDRAM is compared, inconsistent if result relatively finds, then finish this and detect and the reporting errors position; If result relatively is consistent, then continue execution in step S106;
Step S106, judge whether read data has traveled through all SDRAM addresses,, then jump to step S104 if read data does not have to have traveled through all SDRAM addresses; If read data has traveled through all SDRAM addresses; That is, SDRAM is read sky, then execution in step S107;
Step S107, judge whether write data has traveled through all data bit, in this example, at this moment, because data bits has 32, and address size has only 25, so this moment, write data travel through all data bit, therefore, continuation execution in step S108;
The data that step S108, configuration write the SDRAM address again are move to left 25 value of SDRAM address;
Step S109, startup are once to the SDRAM write data;
Step S110, judge whether write data has traveled through all data bit,, then jump to step S109 if write data has traveled through all data bit, if write data has traveled through all data bit, execution in step S111 then;
Step S111, startup are once from the SDRAM reading of data;
Step S112, the data that read and SDRAM are read the value that the address moves to left after 25 compare,, then finish this and detect and the reporting errors position if the result who finds is inconsistent; If result relatively is consistent, then execution in step S113;
Step S113, judge whether read data has traveled through all data bit,, then jump to step S111 if read data has traveled through all data bit, if read data has traveled through all data bit, this EOT.
(second example)
In this example, selected SDRAM model is MT48LC32M8A2, selects for use 2 this model SDRAM as storage stack, and the address size of this group storer is 24 like this, and data bits is 16.SDRAM according to selected model takes the full-page pattern, is the length setting that reads and writes data at every turn 512 (unit is the data numbers).
Before system's operate as normal, start the detection of a SDRAM, produce the address of writing SDRAM automatically, add up behind every write primary memory since 0 automatically in this address; Dispose the data value that each write address writes and be this write address, promptly 0 write data 0 in the address, 1 writes data 1 in the address, by that analogy.Because address size is 24, so the address is up to FFFFFF, after writing data FFFFFF at address FFFFFF; All storage addresss have traveled through; Begin to start, but because data have 16, the data that in fact FFFFFF writes in the address are FFFF once from the SDRAM reading of data; So whether the low m position of data that when reading the SDRAM data, only need relatively read and memory read address consistent getting final product; When the value of the low m position of data that from SDRAM, read and memory read address was inconsistent, then corresponding data bit or the address bit of explanation had problem, finishes this and detects and the reporting errors position in reading data course.When the value of the low m position in the data that from SDRAM, read and memory read address is consistent, continue startup next time from the SDRAM reading of data, traveled through all storage addresss up to read data.When the address size of selected storer during, when having traveled through storage address, inevitablely all data bit have also been traveled through greater than data bits.
With reference to Fig. 1, the concrete implementation procedure of this example is following:
Step S100, before system's operate as normal, start the detection of a SDRAM;
Step S101, automatically produce the address of writing SDRAM, this address is since 0, adds up automatically after whenever writing a SDRAM; The data that configuration writes each SDRAM address are this address;
Step S102, startup be write data in SDRAM once;
Step S103, judge whether write data has traveled through all SDRAM addresses; If write data does not have to have traveled through all SDRAM addresses, then repeated execution of steps S102 starts write data next time; If write data has traveled through all SDRAM addresses, then continue execution in step S104;
Step S104, startup be reading of data from SDRAM once;
Step S105, the low m position of reading the address of data that read and SDRAM is compared, inconsistent if result relatively finds, then finish this and detect and the reporting errors position; If result relatively is consistent, then continue execution in step S106;
Step S106, judge whether read data has traveled through all SDRAM addresses,, then jump to step S104 if read data does not have to have traveled through all SDRAM addresses; If read data has traveled through all SDRAM addresses; That is, SDRAM is read sky, then execution in step S107;
Step S107, judge whether write data has traveled through all data bit, in this example, at this moment, because address size greater than data bits, therefore, has traveled through all data bit, this EOT this moment.
Below with reference to accompanying drawing and embodiment the present invention is described in detail; But; Should be appreciated that the present invention is not limited to above disclosed specific embodiment, modification that any those skilled in the art expects on this basis easily and modification all should be included in protection scope of the present invention.Such as, except storage address, also can be data with the data configuration of write store address according to all data bit of certain rule traversal.In addition, except judging whether that earlier having traveled through all storage addresss judges whether to have traveled through all data bit again, also can judge whether to have traveled through all data bit earlier, and then judge whether to have traveled through all storage addresss.In this case, do not traveled through all data bit when judgement reads and writes data, also need whether travel through all storage address based on reading and writing data is that condition decides how to dispose the data that write.
Claims (18)
1. the method for a fast detecting storer may further comprise the steps:
Configuration writes the data of storage address, so that the correctness of each data bit in these data bit is detected in the position of partial data at least of the traversal of the partial data at least in these data storer; Travel through all storage addresss so that each storage address is read and write detection;
Judge whether the data that write have traveled through all data bit, if the data that write have not traveled through all data bit, then repeat following steps, till having traveled through all data bit:
Configuration begins the data of write store address again from the storer first address, so that the also undetected data bit of these data traversals detects the correctness of each data bit in these data bit; Traversal writes the memory of data address again so that each storage address in these storage addresss is read and write detection.
2. method according to claim 1 is characterized in that, before traversal storage address and data bit, according to the address size of storer and all data of the pre-configured write store of data bits address.
3. method according to claim 1 is characterized in that, said read-write detects and may further comprise the steps:
Traversal will write the memory of data address, write data;
Traversal writes the memory of data address, reading of data, and data that read and the data that write are compared;
If the data that read from storage address are identical with the data that write this storage address; Judge that then the corresponding data line of data bit that is detected with the corresponding address wire of this storage address with these data is in proper working order, otherwise judge corresponding address wire and/or data line operation irregularity according to the data bit that these storage address and/or these data detected.
4. method according to claim 3 is characterized in that,
Whether monitoring read data and write data have traveled through all storage addresss and all data bit, and according to monitoring result dispose the data that write storage address, write data, reading of data and data that read and the data that write are compared.
5. method according to claim 3 is characterized in that,
Write to storage address data, reading of data one by one and data that read and the data that write are compared.
6. method according to claim 3 is characterized in that,
Before all storage addresss of traversal, the data that configuration writes storage address are this storage address itself; When all storage addresss of traversal; After writing the memory of data address reading data, when the address size of the no more than storer of data bits of storer, the low m position of the data that read and this storage address is compared; Wherein, m is the data bits of storer; When the data bits of storer during, directly the data that read and this storage address are compared more than the address size of storer;
After having traveled through all storage addresss, if the data that write have not also traveled through all data bit, the data that then dispose again the write store address are the move to left value of n position of this storage address, and wherein, n is the address size of storer; After writing the memory of data address reading data again, the move to left value of n position of the data that read and this storage address is compared.
7. method according to claim 6 is characterized in that,
Be provided with respectively that write data has traveled through the zone bit of all storage addresss and zone bit that write data has traveled through all data bit representes whether write data has traveled through all storage addresss and whether write data has traveled through all data bit;
When the zone bit that has traveled through all storage addresss when write data represented that write data travel through all storage addresss, disposing the data that write storage address was this storage address itself; After the storage address reading of data, if the address size of the no more than storer of data bits of storer, then the low m position with the data that read and this storage address compares; If the data bits of storer more than the address size of storer, then directly compares the data that read and this storage address;
When the zone bit that has traveled through all storage addresss when write data represented that write data has traveled through all storage addresss, configuration write the value of the data of storage address for this n position, storage address left and right sides; When the zone bit that has traveled through all data bit when write data represented that write data has traveled through all data bit, the move to left value of n position of the data that will read from storage address and this storage address compared.
8. method according to claim 1 is characterized in that,
When configuration writes the storage address data, the length that config memory reads and writes data at every turn.
9. method according to claim 8 is characterized in that,
Judge according to the amount of capacity of storer and the length that reads and writes data of configuration at every turn whether write data and read data have traveled through all storage addresss;
The length that at every turn reads and writes data according to amount of capacity, data bits and the configuration of storer judges whether write data and read data have traveled through all data bit.
10. the device of a fast detecting storer comprises:
Dispensing unit, it was used for before all storage addresss of traversal, and configuration writes the data of storage address, so that the correctness of each data bit in these data bit is detected in the position of partial data at least of the traversal of the partial data at least in these data storer; After all storage addresss of traversal; If the data that write have not also traveled through all data bit; Then dispose from the storer first address and begin the data of write store address again, so that the also undetected data bit of these data traversals detects the correctness of each data bit in these data bit;
Write data unit, it is used for will writing the writing data into memory address of memory of data address with configuration according to the data traversal of dispensing unit configuration;
Reading data unit, it is used for traversal and writes the memory of data address from the storage address reading of data;
Comparing unit; The data that data that it is used for reading data unit is read from storage address and write data unit write this storage address compare; If the data that read are identical with the data that write; Judge that then the corresponding data line of data bit that is detected with the corresponding address wire of this storage address with these data is in proper working order, otherwise judge corresponding address wire and/or data line operation irregularity according to the data bit that these storage address and/or these data detected.
11. device according to claim 10 is characterized in that, dispensing unit is according to the address size of storer and all data of the pre-configured write store of data bits address.
12. device according to claim 10 is characterized in that, also comprises monitoring means, it is used to monitor read data and whether write data has traveled through all storage addresss and all data bit,
Dispensing unit, write data unit, reading data unit and comparing unit respectively according to the monitoring result of monitoring means dispose the data that write storage address, write data, reading of data and data that read and the data that write are compared.
13. device according to claim 10 is characterized in that,
Write data unit, reading data unit and comparing unit write to storage address data, reading of data one by one and data that read and the data that write are compared.
14. device according to claim 10 is characterized in that, said dispensing unit is carried out following configuration operation:
Before all storage addresss of traversal, the data that configuration writes storage address are this storage address itself; After having traveled through all storage addresss, if the data that write have not also traveled through all data bit, the data that then dispose again the write store address are the move to left value of n position of this storage address, and wherein, n is the address size of storer.
15. device according to claim 14 is characterized in that, said comparing unit is carried out following compare operation:
When all storage addresss of traversal; After writing the memory of data address reading data, when the address size of the no more than storer of data bits of storer, the low m position of the data that read and this storage address is compared; Wherein, m is the data bits of storer; When the data bits of storer during, directly the data that read and this storage address are compared more than the address size of storer;
After writing the memory of data address reading data again, the move to left value of n position of the data that read and this storage address is compared.
16. device according to claim 14; It is characterized in that; Also comprise monitoring means; It is used to monitor write data and whether read data has traveled through all storage addresss and data bit, and is provided with respectively that write data has traveled through the zone bit of all storage addresss and zone bit that write data has traveled through all data bit representes whether write data has traveled through all storage addresss and whether write data has traveled through all data bit
The zone bit that travel through all storage addresss when the write data that receives from monitoring means is represented write data having traveled through all storage addresss, and it is this storage address itself that dispensing unit disposes the data that write storage address; After the storage address reading of data, if the address size of the no more than storer of data bits of storer, then comparing unit compares the low m position of the data that read and this storage address at reading unit; If the data bits of storer is more than the address size of storer, then comparing unit directly compares the data that read and this storage address;
When the zone bit that travel through all storage addresss when the write data that receives from monitoring means represented that write data has traveled through all storage addresss, it was the value of this n position, storage address left and right sides that dispensing unit disposes the data that write storage address; When the zone bit that has traveled through all data bit when write data represented that write data has traveled through all data bit, the move to left value of n position of the data that comparing unit will read from storage address and this storage address compared.
17. device according to claim 10 is characterized in that,
When dispensing unit writes the storage address data in configuration, the length that config memory reads and writes data at every turn.
18. device according to claim 17 is characterized in that,
Monitoring means judges according to the amount of capacity of storer and the length that reads and writes data of configuration at every turn whether write data and read data have traveled through all storage addresss; The length that at every turn reads and writes data according to amount of capacity, data bits and the configuration of storer judges whether write data and read data have traveled through all data bit.
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