CN105823972B - A kind of computational methods of organic field effect tube memory minimum memory depth - Google Patents
A kind of computational methods of organic field effect tube memory minimum memory depth Download PDFInfo
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- CN105823972B CN105823972B CN201610145044.2A CN201610145044A CN105823972B CN 105823972 B CN105823972 B CN 105823972B CN 201610145044 A CN201610145044 A CN 201610145044A CN 105823972 B CN105823972 B CN 105823972B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The present invention relates to a kind of computational methods of electret type organic field effect tube memory minimum memory depth, belong to semicon industry memory technology field.The method includes：Preparing has certain thickness electret type organic field effect tube memory；It tests and extracts memory window data of the memory under different program voltages；The memory window data are subjected to linear fit, calculate minimum program voltage needed for polymer electret type organic field effect tube memory；The electric field strength in polymer electret is calculated according to the minimum program voltage；According to the energy level difference of organic semiconductor layer material and polymer electret material, minimum tunneling barrier is calculated；According to the minimum tunneling barrier and electric field strength, the minimum memory depth of polymer electret type organic field effect tube memory is calculated.It the composite can be widely applied to the organic field effect tube memory of all kinds of polymer, solvable small molecule electret type.
Description
Technical field
The invention belongs to semicon industry memory technology fields, and in particular to a kind of organic field effect tube memory
The computational methods of minimum memory depth.
Background technology
With the high speed development of modern information technologies, the information exchange of magnanimity to the processing speed of data, transmission speed, deposit
The indexs such as storage density propose urgent great demand.Storage product prepared by traditional inorganic semiconductor material, it is difficult to meet
These requirements.In contrast, the semi-conducting materials such as organic polymer, small molecule are wide with raw material sources, can carry out electronic structure
Design, it is cheap the advantages that, and with it is flexible, can the Conventional inorganic semiconductors material such as large area preparation, low temperature preparation do not have
Standby feature, therefore apply it among highdensity field-effect transistor memory (OFET) design, there is huge answer
Use foreground.
Current organic field effect tube memory stores the material of active layer according to it, is divided into ferroelectric type, floating gate type
And electret type three categories.Wherein ferroelectric type OFET adjusts the polarized state of ferroelectric material by grid voltage, realizes to information
Record；For floating gate type OFET by metal, inorganic nano-particle or small molecule as charge-trapping center, signal is deposited in realization
Storage；Its memory module of the OFET of electret type and mechanism, still remain dispute, it is generally recognized that its charge is the work in Interface electric field
It under, is stored in the form of tunnelling inside interface or the electret layer of semiconductor layer and electret layer, also or semiconductor
Layer is internal.
In addition, for ferroelectric type OFET, because it changes storage state by the polarization of electric field, because easily causing to information
Destructive read.And in the basic structure of floating gate type OFET, need tunnel layer and floating gate layer, technique relative complex.Compared to it
Under, the OFET of electret type is simple in structure, can by simple solution processing technology can large area prepare, therefore pass through theory
The mode of Binding experiment calculates the storage location and storage depth of electret type OFET memories, will efficiently contribute to improve people
Research and product design and optimization for this type memory.
Therefore, for electret type OFET, calculating its minimum memory depth is very important.How electret type is calculated
The minimum memory depth of OFET is also the technical issues of being badly in need of solving.
Invention content
For existing electret type OFET memory problem encountered, the present invention proposes a kind of electret type organic field effect
Answer the computational methods of transistorized memory minimum memory depth.The present invention does not increase on the basis of existing universal test characterizes equipment
Enlarged test technology, technical difficulty provide a kind of simple method and calculate minimum storage depth, have extremely strong pervasive
Property.
In order to solve the above-mentioned technical problem, technical solution proposed by the present invention is：
A kind of computational methods of electret type organic field effect tube memory minimum memory depth, which is characterized in that
Including step in detail below：
(1), electret type organic field effect tube memory is prepared, electret body thickness is d1, dielectric constant k1, grid
Thickness of insulating layer is d2, dielectric constant k2；
(2), it tests and extracts the memory in different program voltage VProgUnder memory window data Δ VTH；It is described
Memory window data Δ VTH, refer to and threshold voltage value be calculated according to transfer curve, the threshold voltage after definition programming with it is initial
The difference of the threshold voltage absolute value of state is memory window data, further comprises at least obtaining 3-5 group memory window data；
(3), the memory window data are subjected to linear fit, calculated thickness d1Electret type organic effect it is brilliant
Minimum program voltage V needed for body pipe memoryProg-min；The minimum program voltage VProg-min, refer to and done according to memory window data
Go out Δ VTH~VProgRelational graph, by Δ VTHCarry out itself and V after linear fitProgThe intersection point of axis, is defined as VProg-min；
(4), the electric field strength E in electret is calculated according to the minimum program voltageTH, enable ETH=VProg-min/(d1+
d2k1/k2)；
(5), according to the energy level difference of organic semiconductor layer material and electret, minimum tunneling barrier Δ φ is calculated；
(6), according to the minimum tunneling barrier and electric field strength, electret type organic field effect tube is calculated and deposits
The minimum memory depth d of reservoirmin；The minimum memory depth dmin, it is defined as in certain thickness electret, is compiled in minimum
Journey electricity is depressed, and the depth capacity of charge tunnelling enables value dmin=Δ φ/ETH。
Wherein, the electret layer in the organic field effect tube memory is selected from polymer material or small molecule material
Material.
A series of program voltage VProgInclude a series of positive and negative grid programmed by aided programming means (such as illumination)
The absolute value of voltage, program voltage is incremented by the form of arithmetic progression.When operation, the semiconductor analysis of voltage pulse module is carried
Instrument can be Agilent Agilent B1500A, Keithley KEITHLEY 4200-SCS.
The minimum tunneling barrier Δ φ, is organic semiconductor layer and electret for calculating the system that carrier is electronics
The absolute difference of the lowest unoccupied molecular orbital (LUMO) of material；It is organic partly to lead for calculating the system that carrier is hole
The absolute difference of the highest occupied molecular orbital (HOMO) of body layer and electret.
The electret type organic field effect tube memory has following feature：Including including lining from bottom to up
Bottom, gate electrode, gate insulation layer, electret layer, organic semiconductor layer, source-drain electrode；
The material of the substrate is selected from highly doped silicon chip, sheet glass or plastics PET；
The material that the gate electrode uses is selected from highly doped silicon, aluminium, copper, silver, gold, titanium or tantalum；
The material that the gate insulation layer uses is selected from silica, aluminium oxide, zirconium oxide, polystyrene PS or polyethylene pyrrole
The film thickness of pyrrolidone PVP, the gate insulation layer are 300nm；
The film thickness of the electret layer is 30~100nm；
The material that the organic semiconductor layer uses for pentacene, aphthacene, titan bronze, fluorination titan bronze, rubrene or
Anthracene；The organic semiconductor layer is formed a film using thermal vacuum evaporation film-forming method, is covered on electret layer surface and is formed conduction
Raceway groove, thickness are 40~50nm；
The source-drain electrode materials are metal or organic conductor material, and thickness is 60~100nm.Preferably, the source
The material of drain electrode is copper.
The present invention has the advantages that：
1, the present invention provides a kind of computational methods of electret type organic field effect tube memory minimum memory depth,
It can need not increase additional analysis of test system, energy under the premise of being tested using semiconductor analysis instrument general at present
The minimum memory depth for preferably calculating electret type OFET, there is higher calculating fineness and preferable effect of visualization；
2, this method for calculating electret type OFET memory minimum memory depth provided by the invention, establishes one
Simple physical model can effectively analyze the memory mechanism of electret type OFET, improve researcher to electret type OFET
The cognition of storage component part physical layer provides a kind of feasible think of for organic memory of the design with high storage density
Road.
Description of the drawings
The present invention is described further below in conjunction with the accompanying drawings.
Fig. 1 is electret type OFET memory construction schematic diagrames used by present example；
Fig. 2 is the schematic diagram of the minimum program voltage of calculating provided according to the embodiment of the present invention 1；
Fig. 3 is the schematic diagram of the according to embodiments of the present invention 2 minimum program voltages of calculating provided；
Specific implementation mode
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, below in conjunction with embodiment and
The present invention will be described in detail for attached drawing, it is mentioned that attached drawing be suitable only for following embodiments, it is common for this field
For technical staff, other attached drawings can also be obtained according to method mentioned in the present invention.But protection scope of the present invention
It is not limited to following embodiments.
Embodiment 1
A kind of computational methods of electret type organic field effect tube memory minimum memory depth, including：
(1), electret type organic field effect tube memory, thickness d are prepared1, dielectric constant sees k1=3.0,
Structural schematic diagram is as shown in Figure 1；
Specifically comprise the following steps：When practical preparation, laboratory room temperature is maintained at 25 DEG C or so, and indoor humidity is stored in
30% or less.
(a) polymer polyethylene base carbazole (PVK) solution is configured, PVK is used into 1 ' 2- dichloroethanes (DCE) as solvent and is matched
Solution, solubility 10mg/ml is made；
(b) surface d is selected2The heavily doped silicon of=300nm silica is as substrate and gate insulation layer, k2=3.9, it uses
Acetone, ethyl alcohol, deionized water are cleaned by ultrasonic 10 minutes with 80KHZ respectively, are dried in 120 DEG C of vacuum drying oven thereafter；
(c) substrate dried in step (b) is put into UV ozone and handles 3min；
(d) solution configured in the substrate surface spin-coating step (a) handled well in step (c), film thickness are
100nm；
(e) film prepared by step (d) is put into drying in 80 DEG C of vacuum constant temperature baking ovens, cooling is spare；
(f) vacuum evaporation organic semiconductor layer and source-drain electrode on the dried thin polymer film of step (e).Described
Vacuum evaporation semi-conducting material is pentacene, and evaporation rate isVacuum degree control is 5 × 10-4Pa is hereinafter, control vapor deposition is thin
Film thickness is 40~50nm；The vacuum evaporation source-drain electrode is copper, evaporation rateThickness is controlled in 60~100nm.
(2), it is tested by Agilent B1500 semiconductor analysis instrument and extracts the memory in different program voltages
VProgUnder memory window data Δ VTH；The program voltage VProgIncluding positive and negative gate voltage and corresponding aided programming means
The absolute value of (such as illumination), program voltage is incremented by the form of arithmetic progression；The memory window data Δ VTH, refer to bent according to transfer
Line computation obtains threshold voltage value, and the difference of the threshold voltage absolute value of threshold voltage and original state after definition programming is to deposit
Window data is stored up, further comprises at least obtaining 3~5 groups of memory window data.
(3), the memory window data are subjected to linear fit, as shown in Fig. 2, the electret type that calculated thickness is d has
Minimum program voltage V needed for field effect transistors memoryProg-min；The minimum program voltage VProg-min, refer to according to storage
Window data makes Δ VTH~VProgRelational graph, by Δ VTHCarry out itself and V after linear fitProgThe intersection point of axis, is defined as
VProg-min；According to fig. 2, required minimum program voltage when calculating the PVK of 100nm thickness as OFET memory electrets,
For -48.6V.
(4), the electric field strength E in certain thickness electret is calculated according to the minimum program voltageTH；The thickness
It is 1.46MV/cm for electric field strength in the electret of 100nm-1。
(5), according to the energy level difference of organic semiconductor layer material and electret, minimum tunneling barrier Δ φ is calculated；Institute
Minimum tunneling barrier Δ φ is stated, is that semiconductor layer and the minimum of electret do not account for for calculating the system that carrier is electronics
The absolute difference of molecular orbit (LUMO)；It is semiconductor layer and electret for calculating the system that carrier is hole
The absolute difference of highest occupied molecular orbital (HOMO).
(6), according to the minimum tunneling barrier and electric field strength, certain thickness electret type organic field effect is calculated
Answer the minimum memory depth d of transistorized memorymin；The minimum memory depth dmin, it is defined as in certain thickness electret
In, under minimum program voltage, the depth capacity of charge tunnelling enables value dmin=Δ φ/ETH.It is calculated according to the present invention
Electric field strength and minimum memory depth when the PVK of 100nm thickness is as OFET memory electrets, is 3.4nm, meets and reported
Tunneling theory numberical range.
Embodiment 2
A kind of computational methods of electret type organic field effect tube memory minimum memory depth, including：
(1), electret type organic field effect tube memory, thickness d are prepared1, dielectric constant sees k1=3.0,
Structural schematic diagram is as shown in Figure 1；
Specifically comprise the following steps：When practical preparation, laboratory room temperature is maintained at 25 DEG C or so, and indoor humidity is stored in
30% or less.
(a) polymer poly (9,9- dioctyl fluorene acene thiadiazoles) (F8BT) solution is configured, uses toluene as molten F8BT
Agent is configured to solution, solubility 10mg/ml；
(b) surface d is selected2The heavily doped silicon of=300nm silica is as substrate and gate insulation layer, k2=3.9, it uses
Acetone, ethyl alcohol, deionized water are cleaned by ultrasonic 10 minutes with 80KHZ respectively, are dried in 120 DEG C of vacuum drying oven thereafter；
(c) substrate dried in step (b) is put into UV ozone and handles 3min；
(d) solution configured in the substrate surface spin-coating step (a) handled well in step (c), film thickness are
30nm；
(e) film prepared by step (d) is put into drying in 80 DEG C of vacuum constant temperature baking ovens, cooling is spare；
(f) vacuum evaporation organic semiconductor layer and source-drain electrode on the dried thin polymer film of step (e).Described
Vacuum evaporation semi-conducting material is pentacene, and evaporation rate isVacuum degree control is 5 × 10-4Pa is hereinafter, control vapor deposition is thin
Film thickness is 40~50nm；The vacuum evaporation source-drain electrode is copper, evaporation rateThickness is controlled in 60~100nm.
(2), it is tested by Agilent B1500 semiconductor analysis instrument and extracts the memory in different program voltages
VProgUnder memory window data Δ VTH；
(3), the memory window data are subjected to linear fit, as shown in Fig. 2, the electret type that calculated thickness is d has
Minimum program voltage V needed for field effect transistors memoryProg-min；The F8BT for calculating 30nm thickness is stayed as OFET memories
Required minimum program voltage, is -27.2V when polar body.
(4), the electric field strength E in certain thickness electret is calculated according to the minimum program voltageTH；The thickness
It is 1.08MV/cm for electric field strength in the electret of 100nm-1。
(5), according to the energy level difference of organic semiconductor layer material and electret, minimum tunneling barrier Δ φ is calculated.
(6), according to the minimum tunneling barrier and electric field strength, certain thickness electret type organic field effect is calculated
Answer the minimum memory depth d of transistorized memorymin.According to the calculated electric field strength of the present invention and minimum memory depth, 30nm
When thick F8BT is as OFET memory electrets, it is 8.3nm, meets the tunneling theory numberical range reported.
All test results show electret type organic field effect tube memory minimum memory according to the present invention
The computational methods of depth, computation model have theory support, and data reliability is high, and calculating process is easy to operate, of low cost,
Organic field effect tube memory suitable for current electret type.
Invention is not limited to the above embodiment the specific technical solution, all technical sides formed using equivalent replacement
Case be the present invention claims protection domain.
Claims (6)
1. a kind of computational methods of electret type organic field effect tube memory minimum memory depth, which is characterized in that packet
Include step in detail below：
(1), electret type organic field effect tube memory is prepared, electret body thickness is d1, dielectric constant k1, gate insulation
Layer thickness is d2, dielectric constant k2；
(2), it tests and extracts the memory in different program voltage VProgUnder memory window data Δ VTH；The storage
Window data Δ VTH, refer to and threshold voltage value, the threshold voltage after definition programming and original state be calculated according to transfer curve
Threshold voltage absolute value difference be memory window data, further comprise at least obtain 3-5 group memory window data；
(3), the memory window data are subjected to linear fit, calculated thickness d1Electret type organic field effect tube
Minimum program voltage V needed for memoryProg-min；The minimum program voltage VProg-min, refer to and make Δ according to memory window data
VTH~VProgRelational graph, by Δ VTHCarry out itself and V after linear fitProgThe intersection point of axis, is defined as VProg-min；
(4), the electric field strength E in electret is calculated according to the minimum program voltageTH, wherein ETH=VProg-min/(d1+
d2k1/k2)；
(5), according to the energy level difference of organic semiconductor layer material and electret, minimum tunneling barrier Δ φ is calculated；
(6), according to the minimum tunneling barrier and electric field strength, electret type organic field effect tube memory is calculated
Minimum memory depth dmin；The minimum memory depth dmin, it is defined as in certain thickness electret, in minimum programming electricity
Pressure, the depth capacity of charge tunnelling, wherein value dmin=Δ φ/ETH。
2. the calculating side of electret type organic field effect tube memory minimum memory depth according to claim 1
Method, it is characterised in that：Electret layer in the organic field effect tube memory is selected from polymer material and small molecule material
Material.
3. the computational methods of electret type organic field effect tube memory minimum memory depth according to claim 1,
It is characterized in that：Different program voltage V described in step (2)ProgInclude by aided programming means program it is a series of just,
The absolute value of negative gate voltage, program voltage is incremented by the form of arithmetic progression；The test system used is equipped with voltage pulse module
(SMU) semiconductor analysis instrument.
4. the calculating side of electret type organic field effect tube memory minimum memory depth according to claim 1
Method, it is characterised in that：Minimum tunneling barrier Δ φ described in step (5), is organic for calculating the system that carrier is electronics
The absolute difference of the lowest unoccupied molecular orbital (LUMO) of semiconductor layer and electret；It is hole for calculating carrier
System be organic semiconductor layer and electret highest occupied molecular orbital (HOMO) absolute difference.
5. the calculating side of electret type organic field effect tube memory minimum memory depth according to claim 2
Method, it is characterised in that：The electret type organic field effect tube memory, including include substrate, grid electricity from bottom to up
Pole, gate insulation layer, electret layer, organic semiconductor layer, source-drain electrode；
It is highly doped silicon chip, sheet glass or plastics PET that the material of the substrate, which is selected from,；
The material that the gate electrode uses is selected from highly doped silicon, aluminium, copper, silver, gold, titanium or tantalum；
The material that the gate insulation layer uses is selected from silica, aluminium oxide, zirconium oxide, polystyrene PS or polyvinylpyrrolidine
The film thickness of ketone PVP, the gate insulation layer are 300nm；
The film thickness of the electret layer is 30~100nm；
The material that the organic semiconductor layer uses is selected from pentacene, aphthacene, titan bronze, fluorination titan bronze, rubrene or simultaneously
Triphen；The organic semiconductor layer is formed a film using thermal vacuum evaporation film-forming method, is covered on electret layer surface and is formed conductive ditch
Road, thickness are 40~50nm；
The source-drain electrode materials are metal or organic conductor material, and thickness is 60~100nm；
6. the calculating side of electret type organic field effect tube memory minimum memory depth according to claim 5
Method, it is characterised in that：The material of the source-drain electrode is copper.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102823009A (en) * | 2010-03-04 | 2012-12-12 | 佛罗里达大学研究基金会公司 | Semiconductor devices including an electrically percolating source layer and methods of fabricating the same |
| WO2013043225A1 (en) * | 2011-02-23 | 2013-03-28 | University Of Utah Research Foundation | Organic spin transistor |
| CN104361908A (en) * | 2014-10-14 | 2015-02-18 | 中国科学院微电子研究所 | Method for extracting carrier transport channel of metal-oxide-based RRAM (resistive random access memory) |
| CN104993052A (en) * | 2015-06-25 | 2015-10-21 | 南京邮电大学 | OFET memory having porous-structure tunneling layer and manufacturing method thereof |
| CN105336860A (en) * | 2015-11-09 | 2016-02-17 | 南京邮电大学 | Flexible low-voltage organic field effect transistor and manufacturing method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102823009A (en) * | 2010-03-04 | 2012-12-12 | 佛罗里达大学研究基金会公司 | Semiconductor devices including an electrically percolating source layer and methods of fabricating the same |
| WO2013043225A1 (en) * | 2011-02-23 | 2013-03-28 | University Of Utah Research Foundation | Organic spin transistor |
| CN104361908A (en) * | 2014-10-14 | 2015-02-18 | 中国科学院微电子研究所 | Method for extracting carrier transport channel of metal-oxide-based RRAM (resistive random access memory) |
| CN104993052A (en) * | 2015-06-25 | 2015-10-21 | 南京邮电大学 | OFET memory having porous-structure tunneling layer and manufacturing method thereof |
| CN105336860A (en) * | 2015-11-09 | 2016-02-17 | 南京邮电大学 | Flexible low-voltage organic field effect transistor and manufacturing method thereof |
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