CN105810727B - A kind of bipolar junction transistor - Google Patents
A kind of bipolar junction transistor Download PDFInfo
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- CN105810727B CN105810727B CN201410851417.9A CN201410851417A CN105810727B CN 105810727 B CN105810727 B CN 105810727B CN 201410851417 A CN201410851417 A CN 201410851417A CN 105810727 B CN105810727 B CN 105810727B
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Abstract
The invention discloses a kind of bipolar transistors, including substrate；The first area with the first conduction type, the second area with the second conduction type and the third region with the first conduction type are formed in the substrate, the second area is around the periphery set on the first area, and the third region is around the periphery set on the second area；Wherein, an insulating regions extend from a side in the third region to the other side, and the first area and the second area are isolated into two relatively independent parts；The first area and segregate two parts of the second area are brought out as electrode, and the third region is brought out as electrode.The present invention can reduce chip area, while convenient to carry out.
Description
Technical field
The present invention relates to semiconductor fields, and in particular to a kind of novel bipolar junction transistor.
Background technique
Since first transistor of AT&T Labs of U.S. invention comes out, semiconductor has obtained development at full speed, brilliant
Body pipe, which has, can be used the ability that highly automated process is mass produced, and gradually penetrate into each of life at present
A field, above arrives aerospace field, lower to arrive medical communication field, and many accurate devices, which are all be unable to do without, is based on semiconductor material
Prepared transistor.
Triode, full name are transistor, also referred to as bipolar junction transistor, transistor, are a kind of current controls
The semiconductor devices of electric current.Its effect is small-signal to be zoomed into the biggish electric signal of spoke value, also serves as noncontacting switch.Three
Pole pipe is the PN junction that two close proximities are made on a block semiconductor substrate, and bulk semiconductor is divided into three by two PN junctions
Point, middle section is base area, and two side portions are emitter region and collecting zone, and arrangement mode has PNP and two kinds of NPN.
Requirement with people to semiconductor devices is higher and higher, and die size is particularly important.Semiconductor
The smaller integration degree for meaning device of chip size is higher, while smaller also imply that of device size can be in same area
It is lower to place more transistors, and then bring more excellent device performance.
Therefore, how constantly to reduce the direction that chip area is endeavoured always research by those skilled in the art.
Summary of the invention
The present invention provides a kind of bipolar junction transistor, it can be good at reducing chip area, in order to realize that the technology is imitated
Fruit, present invention employs following technical solutions:
A kind of bipolar transistor, wherein including substrate；
In the substrate formed the first area with the first conduction type, the second area with the second conduction type with
And the third region with the first conduction type, the second area is around the periphery set on the first area, the third
Region is around the periphery set on the second area；Wherein,
One insulating regions extend from a side in the third region to the other side, by the first area and described second
Region is isolated into two relatively independent parts；
Respectively segregate two parts in the first area and the second area draw as electrode, and
The third region is drawn and is used as electrode.
Above-mentioned bipolar junction transistor, wherein first conduction type is N-type, and second conduction type is p-type.
Above-mentioned bipolar junction transistor, wherein the substrate is silicon substrate.
Above-mentioned bipolar junction transistor, wherein using intrinsic silicon as the silicon substrate.
Above-mentioned bipolar junction transistor, wherein segregate two parts in first area draw as first
Emitter and the second emitter；
Segregate two parts of second area draw as the first ground level and the second ground level；
The third region is as collector；
First emitter, the first ground level and second emitter, the second ground level share the collector.
Above-mentioned bipolar junction transistor, wherein the insulating regions are gap and/or the insulating materials composition of strip.
Above-mentioned bipolar junction transistor, wherein the first area and the second area are heavy doping, the third
Region is to be lightly doped.
Above-mentioned bipolar junction transistor, wherein the first area, the second area and the third region bottom
There is certain distance with the bottom surface of the substrate.
Above-mentioned bipolar junction transistor, wherein the shape of the first area is circle, the second area and described the
The shape in three regions is ring-type.
Above-mentioned bipolar junction transistor, wherein by lead by the first area, the second area and described
It is drawn in third region.
The present invention is based on above-mentioned technical proposals, can effectively reduce chip area.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in all the attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is show the gist of the present invention.
Fig. 1 is a kind of bipolar junction transistor schematic diagram that the present invention provides in one embodiment；
Fig. 2 is the schematic diagram of corresponding diagram 1 of the present invention in another direction；
Fig. 3 is the circuit diagram of corresponding diagram 1.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
The present invention provides a kind of novel bipolar junction transistor design, compared to can greatly reduce compared with the prior art
Chip area, and then foundation is provided further to promote the accuracy of device.
The present invention provides a kind of bipolar transistors, shown referring to Figures 1 and 2, including substrate 1；
The first area 11 with the first conduction type, the second area with the second conduction type are formed in substrate 1
12 and the third region 13 with the first conduction type.Wherein, second area 12 is surround set on the periphery of first area 11, the
Three regions 13 are around the periphery set on second area 12.Wherein, second area 12 and first area 11, third region are respectively formed and connect
Touching.Further, an insulating regions 14 are additionally provided in substrate 1, the insulating regions 14 are from the side in third region 13 to another
Side extends, and first area 11 and second area 12 are isolated into two relatively independent parts；
Respectively segregate two parts in first area and second area draw as electrode, and by third area
Domain, which is drawn, is used as electrode.
In an optional embodiment of the invention, the first above-mentioned conduction type is N-type, and the second conduction type is p-type.
In an optional embodiment of the invention, above-mentioned substrate can be silicon substrate.It is further alternative, such as can adopt
Use intrinsic silicon material as silicon substrate.
In an of the invention optional embodiment, two parts that above-mentioned first area 11 is isolated by insulating regions 14 into
Row, which is drawn, is used as the first emitter (e1) 11a and the second emitter (e2) 11b；
Two parts that above-mentioned second area 12 is isolated by insulating regions 14 draw as the first ground level (b1) 12a
With the second ground level (b2) 12b；
And above-mentioned third region 13 then can be used as collector (c)；
First emitter 11a, the first ground level 12a and the second emitter 11b, the second ground level 12b share third region 13
As collector, as shown in Figure 3.
In an optional embodiment of the invention, above-mentioned insulating regions 14 are gap and/or the insulating materials group of strip
At.For example, first area 11 and second area 12 are divided into completely by the gap and insulating materials of strip in Fig. 2
Two independent parts, while one end of insulating regions 14 terminates in third region 13.Meanwhile two portions of first area 11
Branch forms a diffusion zone in centre, this not will cause the influence of any substance to the present invention.
In an optional embodiment of the invention, above-mentioned first area 11 and second area 12 are heavy doping, third
Region 13 is to be lightly doped.Wherein, the heavy doping of first area 11 and second area 12 is being lightly doped relative to third region 13
For namely the ion doping concentration of first area 11 and second area 12 be greater than the ion doping concentration in third region 13.
In an of the invention optional embodiment, above-mentioned first area 11, second area 12 and third region 13 bottom
There is certain distance namely each region to need to guarantee to be integrally located among substrate 10 for portion and the bottom surface of substrate 10, and then avoid base
The soldered ball of 10 bottom of plate influences the in electrical contact of each electrode.
In an optional embodiment of the invention, the shape of above-mentioned first area 11 can be circle, then being looped around
The second area 12 of 11 periphery of first area and the shape in third region 13 are ring-type.But those skilled in the art should manage
Solution is only a kind of preferred embodiment using the second area 12 of circular first area 11 and annular, third region 13, and
In other optional embodiments, first area 11 is not limited only to circle, for example, polygon or irregular component
Shape only guarantees that second area 12 is looped around first area 11, and third region 13 is surrounded on 12 periphery of second area,
It will not go into details for this.
In an of the invention optional embodiment, separated first area 11, second area 12 by lead two
Part is drawn respectively, and will be drawn third region 13 by lead.
In conclusion since present invention employs technical solutions as above, by the way that ground level is arranged around emitter, and current collection
Pole is arranged around ground level again, while ground level and emitter are divided into two regions and common collector, and this structure being capable of pole
The big area for reducing chip and occupying, and then more devices can be placed on the same substrate, be conducive to promote device performance.This hair
Bright structural change is small, convenient to carry out.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (10)
1. a kind of bipolar junction transistor, which is characterized in that including substrate；
The first area with the first conduction type, second area and tool with the second conduction type are formed in the substrate
There is the third region of the first conduction type, the second area is around the periphery set on the first area, the third region
Around the periphery set on the second area；Wherein,
One insulating regions extend from a side in the third region to the other side, by the first area and the second area
Two relatively independent parts are isolated into, while one end of the insulating regions terminates in the third region；
The first area and segregate two parts of the second area are brought out as electrode, and third region quilt
It draws and is used as electrode.
2. bipolar junction transistor as described in claim 1, which is characterized in that first conduction type be N-type, described second
Conduction type is p-type.
3. bipolar junction transistor as described in claim 1, which is characterized in that the substrate is silicon substrate.
4. bipolar junction transistor as claimed in claim 3, which is characterized in that using intrinsic silicon as the silicon substrate.
5. bipolar junction transistor as described in claim 1, which is characterized in that segregate two parts in first area into
Row, which is drawn, is used as the first emitter and the second emitter；
Segregate two parts of second area draw as the first base stage and the second base stage；
The third region is as collector；
First emitter, the first base stage and second emitter, the second base stage share the collector.
6. bipolar junction transistor as described in claim 1, which is characterized in that the insulating regions be strip gap and/or
Insulating materials.
7. bipolar junction transistor as described in claim 1, which is characterized in that the first area and the second area are
Heavy doping, the third region are to be lightly doped.
8. bipolar junction transistor as described in claim 1, which is characterized in that the first area, the second area and institute
The bottom surface of the bottom and the substrate of stating third region has certain distance.
9. bipolar junction transistor as described in claim 1, which is characterized in that the shape of the first area is circle, described
The shape in second area and the third region is ring-type.
10. bipolar junction transistor as described in claim 1, which is characterized in that by lead by the first area, institute
It states second area and the third region is drawn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410851417.9A CN105810727B (en) | 2014-12-30 | 2014-12-30 | A kind of bipolar junction transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410851417.9A CN105810727B (en) | 2014-12-30 | 2014-12-30 | A kind of bipolar junction transistor |
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| CN105810727A CN105810727A (en) | 2016-07-27 |
| CN105810727B true CN105810727B (en) | 2019-01-22 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1181631A (en) * | 1996-10-14 | 1998-05-13 | 夏普株式会社 | Power Transistor |
| US5818088A (en) * | 1995-09-11 | 1998-10-06 | Analog Devices, Inc. | Electrostatic discharge protection network and method |
| US6737721B1 (en) * | 1999-10-18 | 2004-05-18 | Nec Electronics Corporation | Shallow trench isolation structure for a bipolar transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100925128B1 (en) * | 2008-03-27 | 2009-11-04 | 레이디오펄스 주식회사 | Combined type Bipolar Transistor implemented with CMOS fabrication process and Electric Circuit using the same |
| KR101174764B1 (en) * | 2010-08-05 | 2012-08-17 | 주식회사 동부하이텍 | bipolar junction transistor based on CMOS technology |
-
2014
- 2014-12-30 CN CN201410851417.9A patent/CN105810727B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5818088A (en) * | 1995-09-11 | 1998-10-06 | Analog Devices, Inc. | Electrostatic discharge protection network and method |
| CN1181631A (en) * | 1996-10-14 | 1998-05-13 | 夏普株式会社 | Power Transistor |
| US6737721B1 (en) * | 1999-10-18 | 2004-05-18 | Nec Electronics Corporation | Shallow trench isolation structure for a bipolar transistor |
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| CN105810727A (en) | 2016-07-27 |
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