CN105808502A - System on chip - Google Patents
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- CN105808502A CN105808502A CN201410842545.7A CN201410842545A CN105808502A CN 105808502 A CN105808502 A CN 105808502A CN 201410842545 A CN201410842545 A CN 201410842545A CN 105808502 A CN105808502 A CN 105808502A
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Abstract
An embodiment of the present invention discloses a system on chip. The system on chip comprises a processor core, a switching controller, a protocol processor and a segmentation cache. The segmentation cache is electrically connected to the switching controller, the protocol processor and the processor core separately, and the protocol processor is electrically connected to the processor core; the switching controller is used for, when a target address of a network data packet received by an NIC is a local host, storing the network data packet to the segmentation cache; and the protocol processor is used for, when a first transmission protocol of a segmentally cached data packet in the segmentation cache is supported, extracting a message payload from the cached data packet for the processor core to further process the message payload, so as to obtain a processor result. With adoption of the system on chip provided by the embodiment of the present invention, the problem of low I/O performance when the processor processes data packets can be solved.
Description
Technical field
The present invention relates to data processing field, particularly relate to SOC(system on a chip).
Background technology
Along with the development of Internet technology and big data technique, the data-cold data seldom used again after occurring in that a large amount of generation.Owing to cold data bulk is generally bigger, it is therefore desirable to special server stores cold data.
Existing server is mainly made up of processor, memorizer and NIC (NetworkInterfaceCard is called for short NIC), and the main data processing operation of server is in that input and output and storage two aspects of data.Such as, packet incoming on network cable, receiving and storing in data procedures, is sent to processor by adapter by server；Processor first parses message payload from the packet received, and then again message payload is carried out process and obtains result, be i.e. data itself, finally carries out the storage operation of data.
It can thus be seen that in the cold data procedures of server process, the calculating resource of processor therein consumes in a large number in the process of resolution data packet voice payload, thus causing that the I/O performance of processor is low.
Summary of the invention
Embodiments provide SOC(system on a chip), the problem that during to solve processor processes data bag, I/O performance is low.
First aspect, embodiments provides a kind of SOC(system on a chip), and this SOC(system on a chip) includes:
Processor core, exchange control unit, protocol processor and Segment-based caching；Wherein, described Segment-based caching is electrically connected with described exchange control unit, described protocol processor, described processor core respectively, and described protocol processor is electrically connected with described processor core；Described exchange control unit, for when the destination address of NIC institute receiving network data bag is the machine, storing described network packet to described Segment-based caching；Described protocol processor, for when supporting the first host-host protocol of Segment-based caching packet in described Segment-based caching, outgoing packet payload is won, in order to described processor core processes described message payload further, obtains processor result from described data cached bag.
In conjunction with first aspect, in the first possible implementation of first aspect,
Described processor core, is additionally operable to when the quantity of the described packet of Segment-based caching is beyond the disposal ability of described exchange control unit, described in process in Segment-based caching packet beyond the part of the disposal ability of described exchange control unit, obtain processor result.
In conjunction with first aspect, in the implementation that first aspect the second is possible,
Described processor core, is additionally operable to when the first host-host protocol of bag data cached described in described protocol processor is not supported, described in process, data cached bag, obtains processor result.
In conjunction with first aspect, in the third possible implementation of first aspect,
Described exchange control unit, is additionally operable to, when the destination address of described network packet is for other equipment, forward described network packet.
In conjunction with first aspect, in the 4th kind of possible implementation of first aspect,
Described SOC(system on a chip) also includes the high-speed cache being electrically connected with described protocol processor；Described high-speed cache is message payload described in buffer memory, in order to adopts direct memory access dma mode to be stored to internal memory by described message payload, processes described message payload for processor core further.
In conjunction with the implementation that the first possible implementation of first aspect or first aspect the second are possible, in the 5th kind of possible implementation of first aspect,
Described SOC(system on a chip) also includes the preprocessor being electrically connected between described Segment-based caching and described processor core；Described preprocessor, for the data cached bag in described Segment-based caching is carried out commodity ethernet Layer 2 data process, so that the data cached bag processed through commodity ethernet Layer 2 data is processed by described processor core further, obtain processor result.
In conjunction with first aspect, in the 6th kind of possible implementation of first aspect,
Described protocol processor, is additionally operable to, when supporting the second host-host protocol that data to be sent need to adopt, use described second host-host protocol that described data to be sent are carried out packing and obtain packet to be sent；Described exchange control unit, is additionally operable to send to NIC described packet to be sent, in order to described NIC sends described packet to be sent.
In conjunction with the 6th kind of possible implementation of first aspect, in the 7th kind of possible implementation of first aspect,
Described processor core, is additionally operable to when described protocol processor does not support described second host-host protocol, uses described second host-host protocol that described packet to be sent is carried out packing and obtains packet to be sent.
In conjunction with the 6th kind of possible implementation of first aspect or the 7th kind of possible implementation of first aspect, in the 5th kind of possible implementation of first aspect,
Described Segment-based caching, is additionally operable to packet to be sent described in buffer memory.
Second aspect, the embodiment of the present invention additionally provides another kind of SOC(system on a chip), and this SOC(system on a chip) includes:
Exchange control unit, protocol processor, processor core and the Segment-based caching being electrically connected respectively with described exchange control unit, described protocol processor, described processor core, described protocol processor and the electrical connection of described processor core；Described protocol processor, for when supporting the second host-host protocol that data to be sent need to adopt, using described second host-host protocol that described data to be sent are carried out packing and obtain packet to be sent；Described exchange control unit, for sending described packet to be sent to NIC, in order to described NIC sends described packet to be sent.
In conjunction with second aspect, in the first possible implementation of second aspect,
Described processor core device, is additionally operable to when described protocol processor does not support described second host-host protocol, uses described second host-host protocol that described packet to be sent is carried out packing and obtains packet to be sent.
In conjunction with second aspect or the first possible implementation of second aspect, in the implementation that second aspect the second is possible,
In conjunction with the implementation that second aspect, the first possible implementation of second aspect or second aspect the second are possible, in the third possible implementation of second aspect,
Described exchange control unit, is additionally operable to, when the destination address of NIC institute receiving network data bag is the machine, store described network packet to described Segment-based caching；Described protocol processor, when being additionally operable to the first host-host protocol of Segment-based caching packet in supporting described Segment-based caching, outgoing packet payload is won, in order to described processor core processes described message payload further, obtains processor result from described data cached bag.
In the embodiment of the present invention, SOC(system on a chip) includes processor core, exchange control unit, protocol processor and Segment-based caching；Described Segment-based caching is electrically connected with described exchange control unit, described protocol processor, described processor core respectively, and described protocol processor is electrically connected with described processor core；Described exchange control unit, for when the destination address of NIC institute receiving network data bag is the machine, storing described network packet to described Segment-based caching；Described protocol processor, for when supporting the first host-host protocol of Segment-based caching packet in described Segment-based caching, outgoing packet payload is won, in order to described processor core processes described message payload further, obtains processor result from described data cached bag.Compared with prior art, the SoC in the embodiment of the present invention, it is possible to by the message payload in protocol processor resolution data bag, and by processor core, message payload is processed.Adopt this mode, it is possible to reduce processor core computational resource consumption in the process of resolution data packet voice payload, so that processor core has the more resource that calculates to process for message payload, such that it is able to promote the I/O performance of processor core.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, for those of ordinary skills, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of mono-embodiment of SoC of the present invention；
Fig. 2 is the structural representation of another embodiment of SoC of the present invention.
Detailed description of the invention
Along with 64 bit data process the version issue of bandwidth, performance and the extensibility of ARM (AdvancedRISCMachine) processor core are greatly improved, and can meet the calculated performance of the application such as similar cold data and the demand of memory space support gradually.When using arm processor, it is possible to the controller needed for computer system, memorizer and arm processor are integrated, constitute SOC(system on a chip) (SystemonChip is called for short SoC).The present invention is by modules such as integrated processor cores, exchange control unit, protocol processor and Segment-based caching in SoC, it is achieved receive and send the function of data.Complete the reception of data such that it is able to enable SoC to substitute the conventional processors in existing server and send work.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete description, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
Referring to Fig. 1, for the structural representation of mono-embodiment of SoC of the present invention.As it is shown in figure 1, this SoC can be made up of processor core 101, exchange control unit 102, protocol processor 103 and Segment-based caching 104.Wherein, described Segment-based caching 104 is electrically connected with described exchange control unit 102, described protocol processor 103, described processor core 101 respectively, and described protocol processor 103 is electrically connected with described processor core 101.
Wherein, protocol processor 103 is a programmable FPGA module, can configure according to demand so that it is support the process to different network protocol, can for be specifically designed for the chip circuit that packet is packaged, resolves by procotol inside it.
SoC all NIC105 on the server be connected to exchange control unit 102 such as through interconnected bus.NIC105 externally provides the communications line interface connecting network, different cord adaptor can be connected to as required, such as cable interface, optical fiber interface or infinite bandwidth technology (InfiniBand) interface, it is achieved the reception of data signal and the function of transmission.
Receive the process of data below in conjunction with SoC, SoC modules does and carries out a step explanation.
This SoC is when receiving data, and data signal incoming on network cable is resolved by NIC105 becomes network packet, and network packet is sent to exchange control unit 102.
When the destination address of described network packet is other equipment, network packet can be returned to NIC105 by exchange control unit 102, so that described network data is forwarded a packet to its destination address by NIC105.When the destination address of NIC105 institute receiving network data bag is the machine, described network packet is stored to described Segment-based caching 104 by exchange control unit 102.In actual use, if protocol processor 103 supports the host-host protocol of described network packet, then this network packet can be put into the hardware unloading segmentation of Segment-based caching 104 by exchange control unit 102, in order to protocol processor 103 processes this network packet；If protocol processor 103 does not support the host-host protocol of described network packet, or protocol processor 103 does not have free processing capacity to process this network packet, so this network packet can be put into the software unloading segmentation of Segment-based caching 104 by exchange control unit 102, in order to processor core 101 processes this network packet.
Described protocol processor 103, for when supporting the first host-host protocol of Segment-based caching 104 packet in described Segment-based caching 104, outgoing packet payload is won, in order to described processor core 101 processes described message payload further, obtains processor result from described data cached bag.In actual use, protocol processor 103 directly can unload segmentation from the hardware of Segment-based caching 104 and obtain data cached bag, and the data cached bag got is carried out protocol processes, wins outgoing packet payload.
Described processor core 101, except may be used for processing described message payload, obtain outside processor result, can be also used for when the quantity of described Segment-based caching 104 packet exceeds the disposal ability of described exchange control unit 102, described in directly processing in Segment-based caching 104 packet beyond the part of the disposal ability of described exchange control unit 102, obtain processor result；Or, it is also possible to for when the first host-host protocol of data cached bag described in described protocol processor 103 is not supported, described in process, data cached bag, obtains processor result.In actual use, processor core 101 directly can unload segmentation from the software of Segment-based caching 104 and obtain data cached bag, and the data cached bag got is carried out protocol processes, wins outgoing packet payload.
Described SoC for ease of processor core 101, data cached bag processed, as in figure 2 it is shown, can also include a preprocessor 106.Described preprocessor 106 is electrically connected to described segmentation and delays between described processor core 101.
Described preprocessor 106, the data cached bag that may be used for described Segment-based caching 104 software is unloaded in segmentation carries out commodity ethernet Layer 2 data process, so that the data cached bag processed through commodity ethernet Layer 2 data is processed by described processor core 101 further, obtain processor result.
For ease of processor core 101, message payload being processed, as described in Figure 2, described SoC can also include a high-speed cache 107.Described high-speed cache 107 and the electrical connection of described protocol processor, message payload described in buffer memory, so that adopting direct memory access (DirectMemoryAccess, it being called for short DMA) described message payload stores to internal memory 108 by mode, processes described message payload further for processor core 101.
Send the process of data below in conjunction with SoC, SoC modules does and carries out a step explanation.
This SoC is when sending data, if described protocol processor 103 supports the second host-host protocol that data to be sent need to adopt, described protocol processor 103 can also use described second host-host protocol that described data to be sent are carried out packing to obtain packet to be sent, be then stored in by packet to be sent in the segmentation to be sent of described Segment-based caching 104.
If described protocol processor 103 does not support the second host-host protocol that data to be sent need to adopt, described processor core 101 can also use described second host-host protocol that described data to be sent are carried out packing to obtain packet to be sent, be then stored in by packet to be sent in the segmentation to be sent of described Segment-based caching 104.
This SoC when sending data, exchange control unit 102, be additionally operable to send to NIC105 described packet to be sent, in order to described NIC105 sends described packet to be sent.Packet to be sent, after receiving packet to be sent, is converted to data signal, and is transmitted by network cable by NIC105.
SoC in the embodiment of the present invention, it is possible to by the message payload in protocol processor resolution data bag, and by processor core, message payload is processed.Adopt this mode, it is possible to reduce processor core computational resource consumption in the process of resolution data packet voice payload, so that processor core has the more resource that calculates to process for message payload, such that it is able to promote the I/O performance of processor core.
Those skilled in the art is it can be understood that can add the mode of required general hardware platform by software to the technology in the embodiment of the present invention and realize.Based on such understanding, the part that prior art is contributed by technical scheme in the embodiment of the present invention substantially in other words can embody with the form of software product, this computer software product can be stored in storage medium, such as ROM/RAM, magnetic disc, CD etc., including some instructions with so that a computer equipment (can be personal computer, server, or NIC etc.) perform the method described in some part of each embodiment of the present invention or embodiment.
Each embodiment in this specification all adopts the mode gone forward one by one to describe, between each embodiment identical similar part mutually referring to, what each embodiment stressed is the difference with other embodiments.Especially for system embodiment, owing to it is substantially similar to embodiment of the method, so what describe is fairly simple, relevant part illustrates referring to the part of embodiment of the method.
Invention described above embodiment, is not intended that limiting the scope of the present invention.Any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within protection scope of the present invention.
Claims (13)
1. a SOC(system on a chip) SoC, including processor core, it is characterised in that also include:
Exchange control unit, protocol processor and Segment-based caching；
Wherein, described Segment-based caching is electrically connected with described exchange control unit, described protocol processor, described processor core respectively, and described protocol processor is electrically connected with described processor core；
Described exchange control unit, for when the destination address of NIC institute receiving network data bag is the machine, storing described network packet to described Segment-based caching；
Described protocol processor, for when supporting the first host-host protocol of Segment-based caching packet in described Segment-based caching, outgoing packet payload is won, in order to described processor core processes described message payload further, obtains processor result from described data cached bag.
2. SoC as claimed in claim 1, it is characterised in that
Described processor core, is additionally operable to when the quantity of the described packet of Segment-based caching is beyond the disposal ability of described exchange control unit, described in process in Segment-based caching packet beyond the part of the disposal ability of described exchange control unit, obtain processor result.
3. SoC as claimed in claim 1, it is characterised in that
Described processor core, is additionally operable to when the first host-host protocol of bag data cached described in described protocol processor is not supported, described in process, data cached bag, obtains processor result.
4. SoC as claimed in claim 1, it is characterised in that
Described exchange control unit, is additionally operable to, when the destination address of described network packet is for other equipment, forward described network packet.
5. SoC as claimed in claim 1, it is characterised in that also include:
The high-speed cache being electrically connected with described protocol processor；
Described high-speed cache is message payload described in buffer memory, in order to adopts direct memory access dma mode to be stored to internal memory by described message payload, processes described message payload for processor core further.
6. SoC as claimed in claim 2 or claim 3, it is characterised in that also include:
It is electrically connected to the preprocessor between described Segment-based caching and described processor core；
Described preprocessor, for the data cached bag in described Segment-based caching is carried out commodity ethernet Layer 2 data process, so that the data cached bag processed through commodity ethernet Layer 2 data is processed by described processor core further, obtain processor result.
7. SoC as claimed in claim 1, it is characterised in that
Described protocol processor, is additionally operable to, when supporting the second host-host protocol that data to be sent need to adopt, use described second host-host protocol that described data to be sent are carried out packing and obtain packet to be sent；
Described exchange control unit, is additionally operable to send to NIC described packet to be sent, in order to described NIC sends described packet to be sent.
8. SoC as claimed in claim 7, it is characterised in that
Described processor core, is additionally operable to when described protocol processor does not support described second host-host protocol, uses described second host-host protocol that described packet to be sent is carried out packing and obtains packet to be sent.
9. SoC as claimed in claim 7 or 8, it is characterised in that
Described Segment-based caching, is additionally operable to packet to be sent described in buffer memory.
10. a SOC(system on a chip) SoC, it is characterised in that including:
Exchange control unit, protocol processor, processor core and the Segment-based caching being electrically connected respectively with described exchange control unit, described protocol processor, described processor core, described protocol processor and the electrical connection of described processor core；
Described protocol processor, for when supporting the second host-host protocol that data to be sent need to adopt, using described second host-host protocol that described data to be sent are carried out packing and obtain packet to be sent；
Described exchange control unit, for sending described packet to be sent to NIC, in order to described NIC sends described packet to be sent.
11. SoC as claimed in claim 10, it is characterised in that
Described processor core, is additionally operable to when described protocol processor does not support described second host-host protocol, uses described second host-host protocol that described packet to be sent is carried out packing and obtains packet to be sent.
12. the SoC as described in claim 10 or 11, it is characterised in that
Described Segment-based caching, is additionally operable to packet to be sent described in buffer memory.
13. the SoC as described in any one of claim 10 to 12, it is characterised in that
Described exchange control unit, is additionally operable to, when the destination address of NIC institute receiving network data bag is the machine, store described network packet to described Segment-based caching；
Described protocol processor, when being additionally operable to the first host-host protocol of Segment-based caching packet in supporting described Segment-based caching, outgoing packet payload is won, in order to described processor core processes described message payload further, obtains processor result from described data cached bag.
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| CN201410842545.7A CN105808502B (en) | 2014-12-29 | 2014-12-29 | System on chip |
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| CN201410842545.7A CN105808502B (en) | 2014-12-29 | 2014-12-29 | System on chip |
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| CN105808502B CN105808502B (en) | 2019-09-13 |
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| CN1761222A (en) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | Storage network adapter of supporting virtual interface |
| CN1910571A (en) * | 2003-07-25 | 2007-02-07 | 国际商业机器公司 | A single chip protocol converter |
| CN102769574A (en) * | 2012-08-06 | 2012-11-07 | 华为技术有限公司 | Device capable of conducting business hardware acceleration and method thereof |
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2014
- 2014-12-29 CN CN201410842545.7A patent/CN105808502B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030105906A1 (en) * | 2001-11-15 | 2003-06-05 | Nokia Corporation | Data processor architecture employing segregated data, program and control buses |
| CN1910571A (en) * | 2003-07-25 | 2007-02-07 | 国际商业机器公司 | A single chip protocol converter |
| CN1761222A (en) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | Storage network adapter of supporting virtual interface |
| CN102769574A (en) * | 2012-08-06 | 2012-11-07 | 华为技术有限公司 | Device capable of conducting business hardware acceleration and method thereof |
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