CN105808502B - System on chip - Google Patents
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- CN105808502B CN105808502B CN201410842545.7A CN201410842545A CN105808502B CN 105808502 B CN105808502 B CN 105808502B CN 201410842545 A CN201410842545 A CN 201410842545A CN 105808502 B CN105808502 B CN 105808502B
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Abstract
The embodiment of the invention discloses systems on chip.The system on chip includes: processor core exchange control unit, protocol processor and Segment-based caching；Wherein, the Segment-based caching is electrically connected with the exchange control unit, the protocol processor, the processor core respectively, and the protocol processor and the processor core are electrically connected；The exchange control unit, for the destination address in NIC institute receiving network data packet be the machine when, the network packet is stored to the Segment-based caching；The protocol processor, for in supporting the Segment-based caching when the first transport protocol of Segment-based caching data packet, outgoing packet payload is won from the data cached packet, in order to which the processor core is further processed the message payload, obtains processor result.Using system on chip provided by present aspect embodiment, I/O performance low problem when can solve processor processes data packet.
Description
Technical field
The present invention relates to data processing field more particularly to systems on chip.
Background technique
With the development of Internet technology and big data technology, there are the data-seldom used again after a large amount of generations
Cold data.Since cold data quantity is usually larger, it is therefore desirable to which special server stores cold data.
Existing server is mainly by processor, memory and network interface card (Network Interface Card, abbreviation
NIC it) constitutes, the main data processing operation of server is two aspect of input and output and storage of data.For example, server exists
It receives and stores in data procedures, the data packet being passed on network cable is sent to processor by adapter；Processor
Message payload is first parsed from the data packet received, then message payload is handled again to obtain processing result, that is, is counted
According to itself, the storage operation of data is finally carried out.
It can thus be seen that the computing resource of processor therein largely consumes during server process cold data
It is low so as to cause the I/O performance of processor during parsing data packet messages payload.
Summary of the invention
The embodiment of the invention provides systems on chip, and I/O performance is low when solving the problems, such as processor processes data packet.
In a first aspect, the embodiment of the invention provides a kind of system on chip, which includes:
Processor core, exchange control unit, protocol processor and Segment-based caching；Wherein, the Segment-based caching respectively with institute
State exchange control unit, the protocol processor, processor core electrical connection, the protocol processor and the processor
Core electrical connection；The exchange control unit, for the destination address in NIC institute receiving network data packet be the machine when, by institute
Network packet is stated to store to the Segment-based caching；The protocol processor, for being segmented in supporting the Segment-based caching
When the first transport protocol of data cached packet, outgoing packet payload is won from the data cached packet, in order to the processing
Device core is further processed the message payload, obtains processor result.
With reference to first aspect, in a first possible implementation of that first aspect,
The processor core is also used to the quantity in the data packet of Segment-based caching beyond the exchange control unit
When processing capacity, the part of the processing capacity beyond the exchange control unit, is obtained in the processing Segment-based caching data packet
Processor result.
With reference to first aspect, in a second possible implementation of that first aspect,
The processor core is also used to not support the first transmission of the data cached packet in the protocol processor
When agreement, the data cached packet is handled, processor result is obtained.
With reference to first aspect, in first aspect in the third possible implementation,
The exchange control unit is also used to when the destination address of the network packet is other equipment, described in forwarding
Network packet.
With reference to first aspect, in the 4th kind of possible implementation of first aspect,
The system on chip further includes the cache with protocol processor electrical connection；The cache is used for
The message payload is cached, in order to which the message payload is stored in memory using direct memory access dma mode, for
Processor core is further processed the message payload.
The first possible implementation or second of first aspect possible implementation with reference to first aspect, first
In the 5th kind of possible implementation of aspect,
The system on chip further includes the pretreatment being electrically connected between the Segment-based caching and the processor core
Device；The preprocessor, for carrying out the processing of commodity ethernet Layer 2 data to the data cached packet in the Segment-based caching,
In order to which the processor core is further handled the data cached packet by the processing of commodity ethernet Layer 2 data,
Obtain processor result.
With reference to first aspect, in the 6th kind of possible implementation of first aspect,
The protocol processor is also used in the second transport protocol for supporting data to be sent that need to use, using described
Second transport protocol is packaged to obtain data packet to be sent to the data to be sent；The exchange control unit, be also used to by
The data packet to be sent is sent to NIC, in order to which the NIC sends the data packet to be sent.
6th kind of possible implementation with reference to first aspect, in the 7th kind of possible implementation of first aspect,
The processor core is also used to use institute when the protocol processor does not support second transport protocol
It states the second transport protocol the data packet to be sent is packaged to obtain data packet to be sent.
The 7th kind of possible implementation of 6th kind of possible implementation or first aspect with reference to first aspect, first
In the 5th kind of possible implementation of aspect,
The Segment-based caching is also used to cache the data packet to be sent.
Second aspect, the embodiment of the invention also provides another system on chip, which includes:
Exchange control unit, protocol processor, processor core and with the exchange control unit, the protocol processor, institute
The Segment-based caching that processor core is electrically connected respectively is stated, the protocol processor and the processor core are electrically connected；Institute
Protocol processor is stated, for using second transport protocol in the second transport protocol for supporting data to be sent that need to use
The data to be sent are packaged to obtain data packet to be sent；The exchange control unit is used for the data to be sent
Packet is sent to NIC, in order to which the NIC sends the data packet to be sent.
In conjunction with second aspect, in second aspect in the first possible implementation,
The processor core device is also used to when the protocol processor does not support second transport protocol, is used
Second transport protocol is packaged to obtain data packet to be sent to the data packet to be sent.
In conjunction with second aspect or second aspect the first possible implementation, in second of second aspect possible realization
In mode,
In conjunction with second aspect, the first possible implementation of second aspect or second of second aspect possible realization side
Formula, in second aspect in the third possible implementation,
The exchange control unit is also used to when the destination address of NIC institute receiving network data packet is the machine, by the net
Network data packet is stored to the Segment-based caching；The protocol processor is also used to be segmented in supporting the Segment-based caching slow
When the first transport protocol of deposit data packet, outgoing packet payload is won from the data cached packet, in order to the processor
Core is further processed the message payload, obtains processor result.
In the embodiment of the present invention, system on chip includes that processor core, exchange control unit, protocol processor and segmentation are slow
It deposits；The Segment-based caching is electrically connected with the exchange control unit, the protocol processor, the processor core respectively, institute
It states protocol processor and the processor core is electrically connected；The exchange control unit, in NIC institute receiving network data packet
Destination address be the machine when, the network packet is stored to the Segment-based caching；The protocol processor, for propping up
When holding in the Segment-based caching the first transport protocol of Segment-based caching data packet, wins out and report from the data cached packet
Literary payload obtains processor result in order to which the processor core is further processed the message payload.With prior art phase
Than SoC in the embodiment of the present invention can be parsed the message payload in data packet by protocol processor, and by processor core
Message payload is handled.Using this mode, processor core can be reduced during parsing data packet messages payload
Computational resource consumption, thus make processor core have more computing resources for message payload processing, so as to mention
Rise the I/O performance of processor core.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, for those of ordinary skill in the art
Speech, without any creative labor, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of SoC one embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another embodiment of SoC of the present invention.
Specific embodiment
As the version of 64 data processing bandwidths is issued, ARM (Advanced RISC Machine) processor core
Performance and scalability are greatly improved, and have gradually been able to satisfy the calculated performance and memory space of the applications such as similar cold data
The demand of support.It, can be by controller, memory and the arm processor collection needed for computer system when using arm processor
At together, constitute system on chip (System on Chip, abbreviation SoC).The present invention passes through the integrated processor core in SoC
The modules such as the heart, exchange control unit, protocol processor and Segment-based caching realize the function of sending and receiving data.So as to so that
SoC, which can substitute conventional processors in existing server, to be completed data and sends and receivees work.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Whole description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It is the structural schematic diagram of SoC one embodiment of the present invention referring to Fig. 1.As shown in Figure 1, the SoC can be by processor
Core 101, exchange control unit 102, protocol processor 103 and Segment-based caching 104 are constituted.Wherein, the Segment-based caching 104 is distinguished
It is electrically connected with the exchange control unit 102, the protocol processor 103, the processor core 101, the protocol processes
Device 103 and the processor core 101 are electrically connected.
Wherein, protocol processor 103 is a programmable FPGA module, can be configured according to demand, its support is made
Processing to different network protocol, inside can be the chip that is packaged, parses to data packet specifically for network protocol
Circuit.
SoC all NIC 105 on the server can be connected to exchange control unit by interconnected bus
102.NIC 105 externally provides the communications line interface of connection network, can be connected to different cord adaptors, example as needed
Such as cable interface, optical fiber interface or infinite bandwidth technology (InfiniBand) interface, sending and receiving for data-signal is realized
Function.
The process of data is received below with reference to SoC, SoC modules, which are done, carries out a step explanation.
When receiving data, the data-signal being passed on network cable parsing is become network data to the SoC by NIC 105
Packet, and exchange control unit 102 is sent by network packet.
When the destination address of the network packet is other equipment, exchange control unit 102 can be by network packet
NIC 105 is returned to, so that the network data is forwarded a packet to its destination address by NIC 105.In the received network of NIC 105
When the destination address of data packet is the machine, exchange control unit 102 stores the network packet to the Segment-based caching 104.
In actual use, if protocol processor 103 supports the transport protocol of the network packet, exchange control unit 102
The network packet can be put into the hardware unloading segmentation of Segment-based caching 104, in order to which protocol processor 103 handles the network
Data packet；If protocol processor 103 does not support the transport protocol of the network packet or protocol processor 103 not to have
Free processing capacity handles the network packet, then the network packet can be put into Segment-based caching by exchange control unit 102
104 software unloads segmentation, in order to which processor core 101 handles the network packet.
The protocol processor 103, for the of 104 data packet of Segment-based caching in supporting the Segment-based caching 104
When one transport protocol, outgoing packet payload is won from the data cached packet, further in order to the processor core 101
The message payload is handled, processor result is obtained.In actual use, protocol processor 103 can be directly from Segment-based caching
Data cached packet is obtained in 104 hardware unloading segmentation, and protocol processes are carried out to the data cached packet got, is won
Outgoing packet payload.
The processor core 101 obtains may be used also outside processor result in addition to can be used for handling the message payload
With for the quantity in 104 data packet of Segment-based caching exceed the exchange control unit 102 processing capacity when, directly place
The part of the processing capacity beyond the exchange control unit 102, obtains processor knot in reason 104 data packet of Segment-based caching
Fruit；Alternatively, can be used for when the protocol processor 103 does not support the first transport protocol of the data cached packet,
The data cached packet is handled, processor result is obtained.In actual use, processor core 101 can be directly from segmentation
Data cached packet is obtained in the software unloading segmentation of caching 104, and protocol processes are carried out to the data cached packet got,
Win outgoing packet payload.
To handle convenient for processor core 101 data cached packet, as shown in Fig. 2, the SoC can also be wrapped
Include a preprocessor 106.The preprocessor 106 is electrically connected to the segmentation and delays between the processor core 101.
The preprocessor 106 can be used for unloading 104 software of Segment-based caching the data cached packet in segmentation
The processing of commodity ethernet Layer 2 data is carried out, in order to which the processor core 101 is further to by two layers of commodity ethernet
The data cached packet of data processing is handled, and processor result is obtained.
To handle convenient for processor core 101 message payload, as described in Figure 2, the SoC can also include one
A cache 107.The cache 107 is electrically connected with the protocol processor, for caching the message payload, with
Convenient for the message payload is stored to interior using direct memory access (Direct Memory Access, abbreviation DMA) mode
It deposits in 108, device core 101 for processing is further processed the message payload.
The process of data is sent below with reference to SoC, SoC modules, which are done, carries out a step explanation.
The SoC when sending data, if the protocol processor 103 supports the second transmission that data to be sent need to use
Agreement, the protocol processor 103 can also use second transport protocol to be packaged to obtain to the data to be sent
Then data packet to be sent is stored in the segmentation to be sent of the Segment-based caching 104 by data packet to be sent.
If the protocol processor 103 does not support the second transport protocol that data to be sent need to use, the processor
Core 101 can also use second transport protocol to be packaged to obtain data packet to be sent to the data to be sent, so
Data packet to be sent is stored in afterwards in the segmentation to be sent of the Segment-based caching 104.
When sending data, exchange control unit 102 is also used to the data packet to be sent being sent to NIC the SoC
105, in order to which the NIC 105 sends the data packet to be sent.NIC 105, will be to after receiving data packet to be sent
It sends data packet and is converted to data-signal, and sent by network cable.
SoC in the embodiment of the present invention can be parsed the message payload in data packet by protocol processor, and by processor
Core handles message payload.Using this mode, processor core can be reduced in the mistake of parsing data packet messages payload
Computational resource consumption in journey, so that processor core is made to have more computing resources to handle for message payload, so as to
To promote the I/O performance of processor core.
It is required that those skilled in the art can be understood that the technology in the embodiment of the present invention can add by software
The mode of general hardware platform realize.Based on this understanding, the technical solution in the embodiment of the present invention substantially or
Say that the part that contributes to existing technology can be embodied in the form of software products, which can deposit
Storage is in storage medium, such as ROM/RAM, magnetic disk, CD, including some instructions are used so that computer equipment (can be with
It is personal computer, server or network interface card etc.) execute certain parts of each embodiment of the present invention or embodiment
The method.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for system reality
For applying example, since it is substantially similar to the method embodiment, so being described relatively simple, related place is referring to embodiment of the method
Part explanation.
The embodiments of the present invention described above are not intended to limit the scope of the present invention.It is any in the present invention
Spirit and principle within made modifications, equivalent substitutions and improvements etc., should all be included in the protection scope of the present invention.
Claims (12)
1. a kind of system on chip SoC, which is characterized in that including processor core, exchange control unit, protocol processor and segmentation are slow
It deposits；Wherein, the Segment-based caching electrically connects with the exchange control unit, the protocol processor, the processor core respectively
It connects, the protocol processor and the processor core are electrically connected；
The exchange control unit, for the destination address in network interface card NIC institute receiving network data packet be the machine when, by institute
Network packet is stated to store to the Segment-based caching；
The protocol processor, for when in the first Segment-based caching include the network packet cached to be processed when, from institute
It states and wins outgoing packet payload in the network packet cached, in order to which to be further processed the message net for the processor core
Lotus obtains processing result, wherein the Segment-based caching includes first Segment-based caching, and first Segment-based caching is for depositing
Store up the network packet for the transport protocol that the protocol processor is supported.
2. SoC as described in claim 1, which is characterized in that
The processor core is also used to exceed the place of the exchange control unit in the quantity of the network packet of Segment-based caching
When reason ability, the part of the processing capacity beyond the exchange control unit, is obtained everywhere in the processing Segment-based caching data packet
Manage result.
3. SoC as described in claim 1, which is characterized in that
The processor core is also used to handle described second point when there is buffer network data packet in the second Segment-based caching
The data cached packet, obtains processing result, wherein the Segment-based caching further includes described second point present in section caching
Section caching, second Segment-based caching be used for store the transport protocol that the protocol processor is not supported network packet or
The network packet that the protocol processor does not have spare capacity to handle.
4. SoC as described in claim 1, which is characterized in that
The exchange control unit is also used to forward the network when the destination address of the network packet is other equipment
Data packet.
5. SoC as described in claim 1, which is characterized in that further include:
With the cache of protocol processor electrical connection；
The cache is for caching the message payload, in order to use direct memory access dma mode by the message
Payload is stored in memory, and device core for processing is further processed the message payload.
6. SoC as claimed in claim 2 or claim 3, which is characterized in that further include:
The preprocessor being electrically connected between the Segment-based caching and the processor core；
The preprocessor, for being carried out at commodity ethernet Layer 2 data to the data cached packet in the Segment-based caching
It manages, at the data cached packet further handled process commodity ethernet Layer 2 data in order to the processor core
Reason, obtains processing result.
7. SoC as described in claim 1, which is characterized in that
The protocol processor is also used to use described second in the second transport protocol for supporting data to be sent that need to use
Transport protocol is packaged to obtain data packet to be sent to the data to be sent；
The exchange control unit is also used to the data packet to be sent being sent to NIC, in order to the NIC send it is described to
Send data packet.
8. SoC as claimed in claim 7, which is characterized in that
The processor core is also used to when the protocol processor does not support second transport protocol, uses described
Two transport protocols are packaged to obtain data packet to be sent to the data to be sent.
9. SoC as claimed in claim 7 or 8, which is characterized in that
The Segment-based caching is also used to cache the data packet to be sent.
10. a kind of system on chip SoC characterized by comprising
Exchange control unit, protocol processor, processor core and with the exchange control unit, the protocol processor, the place
The Segment-based caching that reason device core is electrically connected respectively, the protocol processor and the processor core are electrically connected；
The protocol processor, for being passed using described second in the second transport protocol for supporting data to be sent that need to use
Defeated agreement is packaged to obtain data packet to be sent to the data to be sent, when in the first Segment-based caching include it is to be processed
When the network packet of caching, outgoing packet payload is won from the network packet cached, in order to the processor
Core is further processed the message payload, obtains processing result, wherein the Segment-based caching includes that first segmentation is slow
It deposits, first Segment-based caching is used to store the network packet for the transport protocol that the protocol processor is supported；
The exchange control unit, for the data packet to be sent to be sent to NIC, in order to which NIC transmission is described pending
Send data packet.
11. SoC as claimed in claim 10, which is characterized in that
The processor core is also used to when the protocol processor does not support second transport protocol, uses described
Two transport protocols are packaged to obtain data packet to be sent to the data to be sent.
12. SoC as described in claim 10 or 11, which is characterized in that
The Segment-based caching is also used to cache the data packet to be sent.
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| CN201410842545.7A CN105808502B (en) | 2014-12-29 | 2014-12-29 | System on chip |
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| CN201410842545.7A CN105808502B (en) | 2014-12-29 | 2014-12-29 | System on chip |
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| CN105808502A CN105808502A (en) | 2016-07-27 |
| CN105808502B true CN105808502B (en) | 2019-09-13 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1761222A (en) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | Storage network adapter of supporting virtual interface |
| CN1910571A (en) * | 2003-07-25 | 2007-02-07 | 国际商业机器公司 | A single chip protocol converter |
| CN102769574A (en) * | 2012-08-06 | 2012-11-07 | 华为技术有限公司 | Device capable of conducting business hardware acceleration and method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7013398B2 (en) * | 2001-11-15 | 2006-03-14 | Nokia Corporation | Data processor architecture employing segregated data, program and control buses |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1910571A (en) * | 2003-07-25 | 2007-02-07 | 国际商业机器公司 | A single chip protocol converter |
| CN1761222A (en) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | Storage network adapter of supporting virtual interface |
| CN102769574A (en) * | 2012-08-06 | 2012-11-07 | 华为技术有限公司 | Device capable of conducting business hardware acceleration and method thereof |
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